VL Bus Configuration and Signals
Of course, the path to a “standard” local bus was not an easy one. In 1991 and 1992, a fewchip set suppliers and manufacturers implemented non-standard high-performance I/O buses. For example, some OPTi chip sets were designed to support an OPTi local bus.Unfortunately, the OPTi local bus was supported by only a small handful of manufactur-ers, and because the OPTi approach was specific to their chip sets, few (if any) I/O cardswere ever actually developed for these buses and few manufacturers provided them. Thus,OPTi and other proprietary buses met the same fate as all other non-standardized ap- proaches in the PC industry—they disappeared. However, the failure of proprietary local bus designs did not prevent industry acceptance of a “standard” VL bus design developed by
VESA (Video Electronics Standards Association)
in late 1992. By placing the VL ex-tension connectors in-line with standard ISA connectors, the VL board can also serve as anISA board—only with far higher data throughput.The essential advantage of a VL bus is direct access to the CPU’s main busses. This al-lows a VL device to rapidly transfer the large quantities of data that are vital for high-per-formance video under Windows (and now Windows 95). Further, the VL bus operates atthe motherboard’s bus speed, rather than a fixed 8.3MHz, like the ISA bus. As a result,faster CPU speed will result in faster bus speed. Unfortunately, this is where the advan-tages end.Although virtually direct connection to the CPU might seem like a real asset, you should understand the serious drawbacks. Processor dependence can ultimately become a disad-vantage for the VL bus. Because higher processor speed results in higher bus capacitance,VL signals can lose reliability at high CPU clock frequencies. Further, the processor signalswere intended to attach to only a few chips (such as the RAM controller) and have very pre-cise timing rules. In fact, each type of Intel i486 chip (i.e., i486SX, i486DX, and i486DX/2)has slightly different timing requirements. When additional capacitance loads are added byadding multiple connectors and multiple local-bus chips, all sorts of undesirable things canhappen. The two most likely problems are: data “glitches” caused by slowed processor bussignals and out-of-spec timing for different I/O cards with different loading characteristics.Although the VL specification does not list an upper frequency limit, the potential load problems dictate a practical limit. With a clock speed of 33MHz, a VL motherboard should be able to support two VL devices reliably. At 40MHz, only one VL device should be used. Above 40MHz, the chances of unreliable operation with even one VL device be-come substantial. If you find yourself working on a fast VL system with random systemerrors, see if the problem goes away when the VL device(s) are removed (and replaced with ISA equivalents, if necessary).Another problem is the lack of concurrency. For a PCI bus, the CPU can continue oper-ating when a PCI device takes control of the system busses. VL architecture also allows
S Y S T E M DAT AANDT R O UBL E S H O OT I N G
i486-type CPUs are listed in this paragraph because the VL bus had largely fallen intodisuse by the time Pentium processors arrived. You will only rarely (if ever) find a Pen-tium motherboard fitted with VL bus slots.