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VL Bus Operation

VL Bus Operation

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Published by Drift Gee

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Published by: Drift Gee on Feb 11, 2012
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he demands of data transfer across the expansion bus have continued to evolvefaster than the throughput of classic ISA/EISA bus architectures allow. The volumesof data required by graphic user interfaces (such as Microsoft’s Windows) present se-rious challenges to conventional video adapter and memory design. Early in 1992, the
Video Electronics Standards Association (VESA)
 proposed a new local bus standard called the
VESA Local bus
VL bus
, also dubbed the
Video Local bus
) intended to im- prove the performance of graphics and video sub-systems. In general terms, a “local bus” is a pathway that allows peripherals to access the system’s main memory quickly.For the VL bus, such improved access means higher data throughput and performancefor video information at the speed of the CPU itself. By using a stand-alone bus for video, ISA or EISA busses can be implemented for backward system compatibility.That is, users can upgrade to a new motherboard and graphics card, but all other pe-ripherals and software remain compatible.
VLBus Configuraton and Signals
VLbus layoutKnowing the VLsignals
General Bus Troubleshooting
VL-specific issues
Further Study
VL Bus Configuration and Signals
Of course, the path to a “standard” local bus was not an easy one. In 1991 and 1992, a fewchip set suppliers and manufacturers implemented non-standard high-performance I/O buses. For example, some OPTi chip sets were designed to support an OPTi local bus.Unfortunately, the OPTi local bus was supported by only a small handful of manufactur-ers, and because the OPTi approach was specific to their chip sets, few (if any) I/O cardswere ever actually developed for these buses and few manufacturers provided them. Thus,OPTi and other proprietary buses met the same fate as all other non-standardized ap- proaches in the PC industry—they disappeared. However, the failure of proprietary local bus designs did not prevent industry acceptance of a “standard” VL bus design developed  by
VESA (Video Electronics Standards Association)
in late 1992. By placing the VL ex-tension connectors in-line with standard ISA connectors, the VL board can also serve as anISA board—only with far higher data throughput.The essential advantage of a VL bus is direct access to the CPU’s main busses. This al-lows a VL device to rapidly transfer the large quantities of data that are vital for high-per-formance video under Windows (and now Windows 95). Further, the VL bus operates atthe motherboard’s bus speed, rather than a fixed 8.3MHz, like the ISA bus. As a result,faster CPU speed will result in faster bus speed. Unfortunately, this is where the advan-tages end.Although virtually direct connection to the CPU might seem like a real asset, you should understand the serious drawbacks. Processor dependence can ultimately become a disad-vantage for the VL bus. Because higher processor speed results in higher bus capacitance,VL signals can lose reliability at high CPU clock frequencies. Further, the processor signalswere intended to attach to only a few chips (such as the RAM controller) and have very pre-cise timing rules. In fact, each type of Intel i486 chip (i.e., i486SX, i486DX, and i486DX/2)has slightly different timing requirements. When additional capacitance loads are added byadding multiple connectors and multiple local-bus chips, all sorts of undesirable things canhappen. The two most likely problems are: data “glitches” caused by slowed processor bussignals and out-of-spec timing for different I/O cards with different loading characteristics.Although the VL specification does not list an upper frequency limit, the potential load  problems dictate a practical limit. With a clock speed of 33MHz, a VL motherboard should be able to support two VL devices reliably. At 40MHz, only one VL device should  be used. Above 40MHz, the chances of unreliable operation with even one VL device be-come substantial. If you find yourself working on a fast VL system with random systemerrors, see if the problem goes away when the VL device(s) are removed (and replaced with ISA equivalents, if necessary).Another problem is the lack of concurrency. For a PCI bus, the CPU can continue oper-ating when a PCI device takes control of the system busses. VL architecture also allows
i486-type CPUs are listed in this paragraph because the VL bus had largely fallen intodisuse by the time Pentium processors arrived. You will only rarely (if ever) find a Pen-tium motherboard fitted with VL bus slots.
for bus-mastering operation, but when a VL device takes control of the bus, the CPU must be stopped. Although this is technically not a defect, it clearly limits the performance of high-end devices (e.g., SCSI controllers) that might attempt to use a VL architecture. Fi-nally, the VL bus has several other disadvantages. It is a +5-Vdc architecture (where PCIcan support +3.3-Vdc). Unlike PCI, no “auto-configuration” capability is in the VL bus(jumpers and DIP switches are required), so Plug-and-Play operation is not supported.
The VL bus uses a 116-pin card edge connector with small contacts (similar in appearanceto MicroChannel contacts), as shown in Fig. 46-1. The most recent VL bus release (2.0)offers a 32-bit data path with a maximum data throughput of about 130MB/sec. The pinout for a VL bus is illustrated in Table 46-1. Interestingly, the VL bus has an extensionto the standard ISA/EISA bus. The two right connectors are standard 16-bit ISA bus con-nectors. The two right-most connectors provide the VL compatibility. The long VL con-nector portion provides the 32-bit VL support. This is different than the PCI bus, whichdoes not use any part of the ISA bus.
 VL segment5864-bit areaISA segment484532-bit area1
A simplified drawing of a VL card and bus.
A01Data 00B01Data 01A02Data 02B02Data 03A03Data 04B03GroundA04Data 06B04Data 05A05Data 08B05Data 07A06GroundB06Data 09A07Data 10B07Data 11A08Data 12B08Data 13A09+VCCB09Data 15A10Data 14B10GroundA11Data 16B11Data 17A12Data 18B12+VCCA13Data 20B13Data 19A14GroundB14Data 21

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