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Published by: EVANS on Feb 13, 2012
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08/11/2014

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Controlled NOT Gate:Controlled V Gate:Controlled V+ Gate:
 
module wallace_tree( multiplicand, multiplier, product );output [15:0] product ;input [7:0] multiplicand ;input [7:0] multiplier ;wire [7:0] x ;wire [7:0] y ;wire p [7:0][7:0] ;wire [127:0] g ;wire [17:1] Cout;wire [31:1] S ;wire [31:1] C ;wire [13:1] Sr ;wire [13:1] Cr ;assign x = multiplicand ;assign y = multiplier ;assign product[0] = p[0][0] ;assign product[1] = S[1] ;assign product[2] = S[19] ;assign product[15:3] = Sr[13:1] ;//**********PARTIAL PRODUCT GENERATION **********peres gate0(x[0], y[0] , 0, g[0], g[1], p[0][0] );peres gate1(x[0], y[1] , 0, g[2], g[3], p[0][1] );peres gate2(x[0], y[2] , 0, g[4], g[5], p[0][2] );peres gate3(x[0], y[3] , 0, g[6], g[7], p[0][3] );peres gate4(x[0], y[4] , 0, g[8], g[9], p[0][4] );peres gate5(x[0], y[5] , 0, g[10], g[11], p[0][5] );peres gate6(x[0], y[6] , 0, g[12], g[13], p[0][6] );peres gate7(x[0], y[7] , 0, g[14], g[15], p[0][7] );
 
//********************x[1]**********************//********************x[2]**********************//********************x[3]**********************//********************x[4]**********************//********************x[5]**********************//********************x[6]**********************//********************x[7]**********************//**********PARTIAL PRODUCT COMPRESSION **********//**********COMPRESSION STAGE 1**********half_adder adder_1(p[1][0], p[0][1], S[1], C[1]);full_adder adder_2(p[2][0], p[1][1], p[0][2], S[2], C[2]);compressor adder_3(p[3][0], p[2][1], p[1][2], p[0][3], 0, S[3], C[3], Cout[1] );compressor adder_4(p[4][0], p[3][1], p[2][2], p[1][3], Cout[1], S[4], C[4], Cout[2] );compressor adder_5(p[5][0], p[4][1], p[3][2], p[2][3], Cout[2], S[5], C[5], Cout[3] );compressor adder_6(p[6][0], p[5][1], p[4][2], p[3][3], Cout[3], S[6], C[6], Cout[4] );compressor adder_7(p[7][0], p[6][1], p[5][2], p[4][3], Cout[4], S[7], C[7], Cout[5] );compressor adder_8(0 , p[7][1], p[6][2], p[5][3], Cout[5], S[8], C[8], Cout[6] );full_adder adder_9(p[7][2], p[6][3], Cout[6], S[9], C[9]);half_adder adder_10(p[1][4], p[0][5], S[10], C[10]);full_adder adder_11(p[2][4], p[1][5], p[0][6], S[11], C[11]);compressor adder_12(p[3][4], p[2][5], p[1][6], p[0][7], 0, S[12], C[12], Cout[7] );compressor adder_13(p[4][4], p[3][5], p[2][6], p[1][7], Cout[7], S[13], C[13], Cout[8] );compressor adder_14(p[5][4], p[4][5], p[3][6], p[2][7], Cout[8], S[14], C[14], Cout[9] );compressor adder_15(p[6][4], p[5][5], p[4][6], p[3][7], Cout[9], S[15], C[15], Cout[10] );compressor adder_16(p[7][4], p[6][5], p[5][6], p[4][7], Cout[10], S[16], C[16], Cout[11] );compressor adder_17(0 , p[7][5], p[6][6], p[5][7], Cout[11], S[17], C[17], Cout[12] );full_adder adder_18(p[7][6], p[6][7], Cout[12], S[18], C[18]);//**********COMPRESSION STAGE 2**********//**********FINAL SUMMATION **********endmodule

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