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60970867 a Matlab to Vhdl Conversion Toolbox for Digital Control

60970867 a Matlab to Vhdl Conversion Toolbox for Digital Control

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Published by: Pankaj Kumar on Feb 27, 2012
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Department of Electronic and Computer Engineering,University of Limerick, Limerick, IrelandAbstract: This paper will describe the development of a prototype software toolboxthat can analyze and process a
block diagram model in order to produce a
representation of the model. The derived VHDL model will consist of acombination of behavioural, RTL and structural definitions mapped directly from the
model. This approach may enable a user to develop and simulate a digitalcontrol algorithm using
and once complete, convert this to VHDL code. Thiswould then be synthesized into digital logic hardware for implementation on devicessuch as FPGAs (Field Programmable Gate Arrays) and ASICs (Application SpecificIntegrated Circuits).
Copyright 2000
Keywords: Closed-loop controllers, Computer-aided control system design,Conversion, Digital control, Hardware1. INTRODUCTIONMany automatic control systems utilise a digitalcontrol algorithm (IEE, 1998) for the control of adesired plant. In many cases, the digital controltechnique is based on Z–transform algorithms, andallows for standard (e.g. digital PID (Astrom K. andWittenmark B., 1990)) and novel control techniquesto be employed. Fuzzy logic (Chang H. and Gau J.,1997) techniques, for example, have also beensuccessfully developed and are used in manyapplications. These utilise digital logiccircuits/systems in order to implement the requiredalgorithms and may be implemented as either ahardware-software or hardware only based system. Inaddition to this, the hardware may be dedicated or re-programmable (e.g. with an FPGA (FieldProgrammable Gate Array) or PLD (ProgrammableLogic Device)). Both the software (TexasInstruments, 1991) and re-programmable logicapproaches allow for flexibility in the ability toreadily modify the algorithm for different plant types.A hardware design Application Specific IntegratedCircuit (ASIC) (Winsby A., et al., 1998) may also beconsidered to replace a hardware-software approachin scenarios where the advantages that an ASICsolution may provide benefit the final designsolution. Where the solution is considered for anASIC or FPGA/PLD device, dedicated hardware maybe considered as a cell within the overall distributedcontrol system that will operate under its own set of instructions, but under the supervision of a suitablehost processor system, either on- or off-chip.Hardware Description Languages (HDLs) are utilisedwithin the design process for these digital circuitsand systems.The approaches taken in creating the control systemand controller implementations can take a number of forms, from an ad-hoc design approach which isessentially re-invented on each new design problemencountered, through to formalised approaches whichhave the ability to provide repeatable results.Formalised approaches may provide a solution whose
effectiveness can be analysed and whereimprovements to both the design approach andchosen implementation architectures can bepredicted. The approaches that may be adopted willin many cases be realised by a software suite, ortoolbox.As an example,
 figure 1
identifies a simplifiedclosed-loop control system in which such a digitaldevice is to operate. Here, the digital controller is atthe core of a mixed-technology system that isanalogue in nature. In many cases, the topology of the control system would contain more complexity,with additional command input and feedback sensorsignals to process within a set time.This paper will describe the development of a
software toolbox that can analyze andprocess a
(The MathWorks Inc.) block diagram model in order to produce a
(SjoholmS. and Lindh L., 1997) representation of the originalmodel.
The toolbox is considered as a
as itallows for future development to be undertaken. Thisis considered integral to the creation of a largerdevelopment platform, for use in the development of custom silicon hardware solutions for digital controlapplications.
is a software tool integratedwithin
(The MathWorks Inc.) for modeling,simulating and analyzing dynamical systems. VHDL,the VHSIC Hardware Description Language (IEEEStandard 1076-1993), is used in the modeling,simulation and synthesis of digital circuits andsystems.The overall intention is to enable the behaviour of adigital algorithm to be modeled in
and, withgiven user-defined parameters, convert thisautomatically to VHDL code for logic simulation andsynthesis.The paper is presented as follows.
Section 1
, thissection,
provides an introduction for the designapproach adopted.
Section 2
will provide anoverview of relevant aspects of the VHDL languageused for simulation and synthesis of the resultingdigital system. The conversion toolbox will beintroduced in
Section 3
and this is utilised in a simplecase study in
section 4
Section 5
provides a set of conclusions to the paper and identifies future work.2. VHDL FOR DIGITAL CIRCUITS/SYSTEMSThe VHSIC Hardware Description Language(VHDL) is an industry standard language used withinthe design of digital circuits and systems. Toolsetsbased on the language allow the designer to model,simulate and ultimately synthesise into hardwarelogic complex digital designs commonly encounteredin modern electronic devices.
Figure 2
identifies howVHDL is utilised in a typical approach to the designprocess.Using a top-down design methodology and startingfrom a high level description at the system/algorithmlevel, the models are analysed for functionalcorrectness. More detailed models are generated,increasing the description detail and considering thehardware implementation aspects. These models aredeveloped to be suited for synthesis, by typicallydeveloping RTL (Register Transfer Level) code. Thefunctionally correct code, describing the
, may then be synthesised into actualhardware. This paper considers the above basic steps,taking the system/algorithm from the
block diagram and converting this to synthesisable VHDLcode based on mapping model blocks to pre-definedFig. 1. Simplified example system utilising acustom digital core
PoweramplifierDigital core(Algorithm)DACADCSynthesizedVHDL modelSensor
Command input 
Fig. 2. Design using VHDL: ASIC Design Route
System/algorithmspecification andsimulationRTL codeRTL codesynthesis
Simulationand resultscomparisonSimulationtoensurecorrect unctionality
Place &Route layoutDesign toASIC vendorPhysicalDesignDesignentryandverification
entity/architecture constructs. Where required, theseconstructs are parameterisable for the particulardesign scenario.In the final circuit, adequate consideration must alsobe given to the testability aspects of the circuit (adesign-for-test (DfT) approach). Whilst testability isconsidered from the outset of the design process,detailed implementation and optimisation of thecircuit architecture and test structures would be aprocess of circuit enhancement, both pre- and post-synthesis. This would be required to ensure anadequate test coverage whilst minimising the impacton circuit performance and cost. The entities andarchitectures are by default generated with ports toenable scan-path testing, but not the actual hardwareto enable this. If required, the designer may, with asmall modification to the final design, realise scanpath testing.3. CONVERSION TOOLBOX OVERVIEWThe conversion routine is to be considered as part of a larger design flow and development system. Anoverview of the design process is shown in
 figure 3
.Here, the main steps from initial modelling throughto design data output for design realisation areshown.At each stage in the creation/conversion process,simulation is used to ensure that the models functioncorrectly. In
 figure 3
stage 1
models of thebehaviour of the overall system and defines abehavioural model of the controller core. Thesimulation for this is in terms of the system’sdynamics and response to a range of test stimuli(step, sinusoidal, ramp, etc.). In
stages 2
, onthe other hand, the simulation is in terms of thedigital logic behaviour and the flow of logic signals(logic 0 and 1, along with propagation delays)through the controller core. Care must be taken toensure that the viewed data flow is as expected.Although only a small sub-set of blocks maycurrently be processed, the toolbox has been arrangedto allow for additional blocks to be added at a laterstage. The resulting data will be a model (.
) filefor the complete system, and a second model file forthe blocks for processing. It is this second model filethat is processed to create the VHDL code: describedin terms of VHDL entities
and architectures. Twostages in the conversion are considered. The first,primarily described here, shows the first stage inconversion that maps
blocks to VHDLentities
and architectures. The second, performs an
routine to map the functions to apredefined architecture. Both solutions may beconsidered in order to determine a solution thatattains the required functionality whilst occupyinga small silicon area. The toolbox has been set-upto operate in one of two ways. Firstly, directlyfrom the UNIX command line where the user willbe prompted to enter configuration informationfrom the keyboard. This would allow for theprogram to be integrated into other toolsets.Secondly, the toolbox may be called from the
command line as a
function.Once conversion and optimization have beencompleted, the VHDL (.
) files are used withina suitable design flow to compile the entities
andarchitectures into VHDL design units, to simulatethe digital logic behaviour of the hardware designand, if conversion and the simulation resultsprovide a design that has been verified throughdigital logic simulation, to synthesize this codeinto a netlist for producing:
A target FPGA configuration data
The mask data to fabricate a semi-custom(digital, cell based) ASIC for a suitable targetfabrication process: this may be integrated into amixed-signal ASIC containing also analoguesignal conditioning, ADC and DAC macrosThe choice of whether to target an FPGA or ASICcould be made at any point within the initialdesign stages, provided that the resultinghardware was to meet the design requirements.Additionally, prior to synthesis, it may also be arequirement for the user to intervene and modifyFig. 3. Overview of conversion routine within adesign process
Simulink model(.
file)Simulink model(.
SystemDigital part forconversionConversionutilityVHDL models(.
files)OptimisationSynthesisVHDL models(.
files)Netlist/schematic:simulationLayout place &routeFPGA/PLD: configurationdataLogicsimulation123ASIC: silicon foundryinterface

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