VLSI Design Lecture 5: Design Rules and Fabrication

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by author (from Prentice Hall PTR)

Topics
Design rules and fabrication SCMOS scalable design rules Stick diagrams

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Why we need design rules

Masks are tooling for manufacturing. Manufacturing processes have inherent

limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. Design rules are determined by experience.

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Manufacturing problems
Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.
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Transistor problems
Variations in threshold voltage:
oxide thickness; ion implantation; poly variations.

Changes in source/drain diffusion overlap. Variations in substrate.

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Wiring problems
Diffusion: changes in doping
in resistance, capacitance. Poly, metal: variations in height, width variations in resistance, capacitance. Shorts and opens: variations

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Oxide problems
Variations in height. Lack of planarity step coverage.
metal 2 metal 2 metal 1

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Via problems
Via may not be cut all the way through. Undersize via has too much resistance. Via may be too large and create short.

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MOSIS SCMOS design rules

1. Designed to scale across a wide range
of technologies. 2. Designed to support multiple vendors. 3. Designed for educational use. Therefore, fairly conservative.

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 and design rules

is the size of a minimum feature. Specifying particularizes the scalable

rules. Parasitics are generally not specified in units.

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Scaling
Scale all chip parameters by x:
I/I = 1/x.

W -> W/x, L -> L/x, V -> V/x, etc. Transistor current shrinks:

But capacitance shrinks more, so chip

speeds up: smaller.

Shrinking makes chip faster and

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(CV/I)/(CV/I) = 1/x.

Wires
6 3 3 3 2 metal 3 metal 2 metal 1 pdiff/ndiff poly

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Transistors
2 3 2 3 1 5

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Vias
Types of via: metal1/diff, metal1/poly,
metal1/metal2.

4 1 2

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Metal 3 via
Type: metal3/metal2. Rules:
cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2

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Tub tie

4 1

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Spacings
Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4
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Overglass
Cut in passivation layer. Minimum bonding pad: 100 m Pad overlap of glass opening: 6 Minimum pad spacing to unrelated
metal2/3: 30 Minimum pad spacing to unrelated metal1, poly, active: 15

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Stick diagrams
A stick diagram is a cartoon of a layout. Does show all components/vias (except
possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

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Stick layers
metal 3 metal 2 metal 1 poly ndiff pdiff

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Dynamic latch stick diagram

VDD

in

out

VSS phi
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phi
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Sticks design of multiplexer

Start with NAND gate:
+

out b a

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NAND sticks
VDD a

out

VSS
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One-bit mux sticks

VDD
ai bi select a out a out select a out

N1 (NAND)
b

N1 (NAND)
b

N1 (NAND)
b

VSS
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3-bit mux sticks

select select a2 b2 ai bi select a1 b1 ai bi select a0 b0 ai bi select select select select VDD oi VSS VDD oi VSS VDD oi VSS

m2(one-bit-mux)

o2

m2(one-bit-mux)

o1

m2(one-bit-mux)

o0

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Layout design and analysis tools

Layout editors are interactive tools. Design rule checkers are generally batch--identify DRC errors on the layout. Circuit extractors extract the netlist from the layout. Connectivity verification systems (CVS) compare extracted and original netlists.

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Automatic layout
Cell generators (macrocell generators)
create optimized layouts for ALUs, etc. Standard cell/sea-of-gates layout creates layout from pre-designed cells + custom routing.
Sea-of-gates allows routing over the cell.

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Standard cell layout

routing area routing area routing area

routing area

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