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 Version 4.1
11/18/2011
NVIDIA CUDA 
™
 
NVIDIA CUDA CProgramming Guide
 
 
ii
CUDA C Programming Guide Version 4.1
 
Changes from Version 4.0
 
Documented the
cudaAddressModeBorder
and
cudaAddressModeMirror
texture address modes in Section3.2.10.1.2andSection3.2.10.1.3. 
 
 Added Sections3.2.10.1.6,3.2.10.1.7,B.8.7,andB.8.8on cubemap textures and cubemap layered textures.
 
Updated Section3.2.10.2.1to mention the change in how surface references aredeclared.
 
 Added Sections3.2.10.2.3, 3.2.10.2.4,B.9.5,B.9.6, B.9.7, B.9.8, B.9.9,B.9.10,  B.9.11, B.9.12, B.9.13,andB.9.14on three-dimensional, cubemap, layered, and cubemap layered surfaces.
 
Mentioned the new function
cudaGLGetDevices()
in Section3.2.11.3. 
 
Mentioned in SectionB.8.1that
tex1Dfetch()
only works with non-normalized coordinates, so only the border and clamp addressing modes aresupported.
 
Shortened the description of the driver API and moved it toAppendix G. 
 
Specified in SectionB.12that the warp vote functions operate on the activethreads of the warp.
 
 Added new SectionB.14on assertions.
 
Deleted fromAppendix Cthe descriptions of a few functions that have beenmoved to the reference manual.
 
 Added mathematical functions
erfcxf()
and
erfcx()
toTable C-1and Table C-2. 
erfcx()
is the scaled complementary error function:
erfcx(x) = exp(x*x) * erfc(x)
.
 
 Added the Bessel functions
j0()
,
j1()
,
jn()
,
y0()
,
y1()
, and
yn()
to Table C-1and
j0f()
,
j1f()
,
jnf()
,
y0f()
,
y1f()
, and
ynf()
to TableC-2. 
 
Removed Section D.2.4.5 since
 __global__ 
functions can now be defined within an anonymous namespace.
 
 Added toTable F-2the maximum sizes for cubemap textures, cubemap layeredtextures, three-dimensional surfaces, cubemap surfaces, and cubemap layeredsurfaces.
 
Updated the maximum width and height of a texture bound to linear memory in Table F-2. 
 
Updated the maximum number of instructions per kernel for devices of compute capability 2.x from 2 million to 512 million inTable F-2. 
 
 
CUDA C Programming Guide Version 4.1
 
iii
 
Table of Contents
Chapter 1. Introduction ................................................................................... 1
 
1.1
 
From Graphics Processing to General-Purpose Parallel Computing ................... 1
 
1.2
 
CUDA 
™
: a General-Purpose Parallel Computing Architecture .......................... 3
 
1.3
 
 A Scalable Programming Model .................................................................... 4
 
1.4
 
Document’s Structure
................................................................................. 6
 
Chapter 2. Programming Model ....................................................................... 7
 
2.1
 
Kernels ...................................................................................................... 7
 
2.2
 
Thread Hierarchy ........................................................................................ 8
 
2.3
 
Memory Hierarchy .................................................................................... 10
 
2.4
 
Heterogeneous Programming .................................................................... 11
 
2.5
 
Compute Capability ................................................................................... 14
 
Chapter 3. Programming Interface ................................................................ 15
 
3.1
 
Compilation with NVCC ............................................................................. 15
 
3.1.1
 
Compilation Workflow ......................................................................... 16
 
3.1.1.1
 
Offline Compilation ...................................................................... 16
 
3.1.1.2
 
Just-in-Time Compilation .............................................................. 16
 
3.1.2
 
Binary Compatibility ........................................................................... 17
 
3.1.3
 
PTX Compatibility ............................................................................... 17
 
3.1.4
 
 Application Compatibility ..................................................................... 17
 
3.1.5
 
C/C++ Compatibility .......................................................................... 18
 
3.1.6
 
64-Bit Compatibility ............................................................................ 18
 
3.2
 
CUDA C Runtime ...................................................................................... 19
 
3.2.1
 
Initialization ....................................................................................... 19
 
3.2.2
 
Device Memory .................................................................................. 20
 
3.2.3
 
Shared Memory ................................................................................. 22
 
3.2.4
 
Page-Locked Host Memory .................................................................. 28
 
3.2.4.1
 
Portable Memory ......................................................................... 29
 
3.2.4.2
 
Write-Combining Memory ............................................................. 29
 
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