Journal of the Korean Physical Society, Vol. 38, No. 3, March 2001, pp.

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Application of Dynamic Pass-Transistor Logic to an 8-Bit Multiplier

Jong Duk Lee , Yong Jin Yoon , Kyoung Hwa Lee and Byung-Gook Park
Inter-University Semiconductor Research Center (ISRC) and School of Electrical Engineering, Seoul National University, Seoul 151-742 (Received 12 April 2000) Dynamic pass-transistor logic (PTL), which combines pass-transistor logic with dynamic logic, is proposed for high-performance VLSI circuit design. The dynamic PTL holds the merits of fast evaluation characteristics as dynamic logic. Moreover, because a pre-charged scheme solves the weak logic high problem of a static PTL, an additional level restoration circuit is not needed. An 8-bit multiplier is designed using dynamic PTL for the evaluation of its characteristics. The multiplier consists of a Booths partial product generator and a [4 : 2] compressor for a partial product reduction tree. For the comparison of performance, the multiplier is also designed using conventional static CMOS logic. An HSPICE simulation is carried out with the 0.25 m CMOS device model parameters used in Samsung Electronics Co. From the simulation, the delay of multiplier is 206.2 psec, and the power consumption is 117.5 mW with a 3.3 V supply voltage, a 1 GHz operation and a 60 o C temperature. The results show that the multiplier designed by using dynamic PTL improves the speed by 2.5 times but consumes more power by 21 %; hence, the power delay product is improved by 50 % compared with a static CMOS.

I. INTRODUCTION Pass-transistor logic (PTL) was reported as another alternative logic that can enhance circuit performance [1]. Since PTL can propagate signals using both the source (or drain) and the gate, its high functionality can reduce the number of transistors in the critical path. As a PTL-based circuit can consist of only one type of MOS transistor (generally an nMOS transistor), it has a low node capacitance. As a result, PTL enables high-speed and low-power circuits. However, due to the threshold voltage drop, PTL has a weak logic high, so additional level restoration circuits are needed. As a result, the performance of PTL is degraded, and the circuit structure is more complicated. In this paper, a dynamic PTL that replaces the weak logic high with a pre-charged level is proposed. Because of the pre-charged scheme, dynamic PTL can operate without level restoration circuits, so the circuit performance can be improved. An 8-bit multiplier is designed using dynamic PTL, and the performance is veried by using an HSPICE simulation.
E-mail: jdlee@snu.ac.kr, Tel:+82-2-880-7268, Fax:+82-2-871-7323 E-mail: mbyoon@smdl.snu.ac.kr, Tel:+82-2-880-7282, Fax:+82-2-871-7323 E-mail: keich@smdl.snu.ac.kr, Tel:+82-2-880-7282, Fax:+82-2-871-7323 -220

II. DESIGN USING DYNAMIC PASS-TRANSISTOR

Fig. 1. Two-input multiplexer circuit using (a) dynamic PTL scheme and (b) CPL. Dynamic PTL needs no level restoration.

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Table 1. Operation of multiplexer based partial product generator using Radix-4 Booths algorithm. Multiplier Bit Pattern Bj+1 Bj Bj1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Operation 0 A A 2A 2A A A 0 Patial Product 0 Ai Ai Ai1 Ai1 Ai Ai 1

Fig. 2. Local reset signal(LRS) generator for dynamic PTL.

Figure 1 shows the multiplexer circuit using dynamic PTL and complementary pass-transistor logic (CPL). CPL is chosen because of its superior performance among the conventional static PTLs [2]. The output nodes of dynamic PTL are pre-charged by a local reset (LRS) signal generated by the inputs and the system clock, and then they are discharged conditionally by input signals. Because the nMOS transistor of dynamic PTL operates only to discharge the nodes, there is no threshold voltage drop problem. Additional level restoring circuits and a complementary output like CPL are not needed. LRS generator circuit is displayed at Figure 2. One complementary inputs are logically dynamic ANDed with the system clock. When the input transits to L from normal H , LRS terminates its pre- charge state and it make the node enter into evaluation mode. Research on the synthesis of high speed PTL has been carried out using double pass-transistor logic (DPL) [3].

However, because the DPL uses the same number of pMOS transistors as nMOS transistors, there is a limit to reducing the number of transistors. The synthesis method of dynamic PTL is dierent from that of DPL. For example to make XOR, DPL needs both nMOS transistors for neighbor 0 group and pMOS transistors for neighbor 1 group separately on the Karnaugh-map. It needs four transistors to construct 2-input XOR. But dynamic PTL is looping only 0 for nMOS transistor. As shown in Figure 3, the loop 1 and loop 2 build basic transistor blocks of (b) and (c), respectively. By wiring these circuits simply, the logic function XOR using dynamic PTL is completed. For the cascade connection of the dynamic PTL, a dynamic inverter is used. The inverter in the PTL scheme is necessary to de-couple the input/output signals and to re-generate the signal for every three or four pass transistors.

III. DESIGN OF 8-BIT MULTIPLIER USING

Fig. 3. Example of minimized dynamic PTL implementation for 2-input XOR (a) loops on Karnough map, (b) basic block by loop 1, (c) basic block by loop 2, and (d) completed dynamic PTL 2- input XOR.

Fig. 4. Design of the multiplexer based Booths partial product generator.

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Journal of the Korean Physical Society, Vol. 38, No. 3, March 2001

Fig. 5. Partial product generator expressed by dynamic PTL.

DYNAMIC PTL The multiplier consists of a partial product generator (PPG) and a partial product reduction tree (PPRT). Because the multiplexer structure is proper to PTL, the PPG is designed to generate a partial product through an 8 : 1 multiplexer under the rules of the radix-4 Booths algorithm [4]. Booths rule is arranged in Table 1. According to the bit patterns of the multiplier B, the PPG selects a proper type of multiplicand A. Negative partial products are made through 2s complement. In Figure 4, the multiplexer-based PPG is illustrated, and in gure 5, the multiplexer in the dotted region of Figure 4 is expressed by dynamic PTL. The multiplexer-structured PPG has the merits that it generates partial products without Booths encoding circuits and can equalize the arrival times of all the partial products at the input of the next stage. The pre-charge pMOS is not shown for simplicity in Figure 5. Because a wider bit multiplier has a large partial product reduction tree (PPRT), the fast reduction method is the key to high performance. Partial products may be reduced using one of the various compressor and counter

Fig. 7. [4 : 2] compressor for the partial product reduction tree designed by using dynamic PTL.

schemes. Many papers report that a [4 : 2] compressor is the optimal leaf cell of a PPRT in the trade-o of design simplicity and wiring complexity [5]. In this research [4 : 2] compressor scheme was chosen for the PPRT. Figure 6 shows the [4 : 2] compressor, which consists of a 4-input XOR, AND-OR (A-O), OR-AND (O-A) and 2input multiplexer. The compressed outputs, X and Y, may become the inputs of the successive carry propagation adder or another compressor for the nal multiplication results. Because the internal output carry (CO) is not a function of the input carry (CIN) from the previous bit, internal carries are not propagated to the next weight. Therefore, fast reduction is possible. The input signals from previous pass transistor block may arrive at next block-PPRT- respectively. By the skew of these signal pre-charged node may be discharged

Fig. 6. Schematic diagram of the [4 : 2] compressor chosen for the multiplier.

Fig. 8. Simulated delay of the 8-bit multiplier designed by using dynamic PTL and static CMOS logic.

Application of Dynamic Pass-Transistor Logic to an 8-bit Multiplier Jong Duk Lee et al. Table 2. Simulated results of the 2-input multiplexer designed by dynamic PTL and CPL. Power (mW) 2.5 V 3.3 V 1.90 3.47 1.98 3.60 Time Delay (psec) 2.5 V 3.3 V 103 87 127 109

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Dynamic PTL CPL

Power Delay (fJ) 2.5 V 3.3 V 195.7 301.9 251.5 392.4

Table 3. Simulated results of the 8-bit multiplier designed by dynamic PTL with temperature of 60 and operation frequency of 1 GHz. Logic Dynamic PTL Static CMOS Power (mV) 2.5 V 3.3 V 71.33 117.05 48.28 96.99 Time Delay (psec) 2.5 V 3.3 V 290.4 206.2 602.0 510.7 Power Delay (pJ) 2.5 V 3.3 V 20.7 24.1 29.1 49.5

to a lower than VCC level. For preventing incorrect operation of the PPRT due to the skews of the PPG outputs the compressor is designed by pre-discharged dynamic PTL while the PPG is designed using a pre-charged dynamic PTL. Pre-discharge dynamic PTL scheme uses small discharging nMOSs to discharge the nodes by the LRS. The detailed design of PPRT using the predischarged dynamic PTL scheme is illustrated in Figure 7.

V. CONCLUSIONS Since dynamic PTL has the merits both of conventional PTL and dynamic logic, it needs no additional restoration circuit, and high performance is expected, which is veried using an HSPICE simulation. Dynamic PTL outperforms CPL both in power and delay. An 8-bit multiplier that consists of a PPG and a PPRT is selected for evaluating the performance of dynamic PTL. For a stable interface between the PPG and PPRT blocks, a pre-discharge dynamic PTL with a dynamic inverter is also proposed. The dynamic PTL-based multiplier presents high performance compared with the static CMOS-based one. The speed of the multiplier designed using dynamic PTL is faster by 2.5 times than the static CMOS. The power delay product is improved by half. Therefore, dynamic PTL is proved to be a highperformance circuit design logic.

IV. SIMULATION RESULTS An HSPICE simulation is carried out with the 0.25 m CMOS device model parameters used at Samsung Electronics Co. The thickness of the gate oxide / threshold voltage of the pMOS and the nMOS are 6.2 nm / 0.43 V and 6.0 nm / 0.35 V, respectively. First of all, the performance of the 2- input multiplexer designed by using dynamic PTL is veried through a simulation and is compared with static PTL-CPL. The simulation results are summarized in Table 2. The dynamic PTL-based multiplexer improves both the power consumption and speed. Because the dynamic PTL removes the overlap current through pMOS it has the fast evaluation characteristics of dynamic logic. The simulation of the 8-bit multiplier is carried out for dynamic PTL and static CMOS logic. The results are depicted in Figure 8. At a 3.3 V supply voltage, the dynamic PTL-based multiplier reveals a propagation delay of 206.2 psec, which is 2.5 times faster than a static CMOS one. However, the dynamic PTL-based multiplier consumes more power than a static CMOS one by 21%. The delay and power consumption data for various supply voltages are summarized in Table 3. The power delay product is improved by 50 %. At a lower supply voltage of 2.5 V, the improvement is decreased to 30 % because the eect of the threshold voltage drop in the pre-discharge scheme is more signicant at low supply voltage.

ACKNOWLEDGMENTS This research was supported by a contract from the Inter-university Semiconductor Research Center to Samsung Electronics Co. under Grant No. ISRC-98-X-5505. REFERENCES
[1] K. Yano, Y. Sasaki, K. Rikino and K. Seki, IEEE J. Solid State Cir. 31, 792 (1996). [2] R. Zimmermann and W. Fichtner, IEEE J. Solid State Cir. 32, 1079 (1997). [3] V. G. Oklobdzija and B. Duchene, IEEE Trans. on Cir. and Sys.-II: Analog and Digital Signal Processing, 44, 974 (1997). [4] I. Koren, Computer Arithmetic Algorithm (Prentice-Hall, 1993). [5] H. A. Al-Twaijary and M. J. Flynn, IEEE Trans. on Computers 47, 1201 (1998).