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Compare Performance of Bruijn and Mesh Architectures in Network-On-Chip
Compare Performance of Bruijn and Mesh Architectures in Network-On-Chip
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Abstract Various network topologies such as meshes and bruijn used for Network on Chip (NoCs). In particular, much attention has focused on mesh-based topologies that was a project studies and develops a Network-on-Chip (NoCs). In this paper, we consider four parameters, such as their relatively short hop-count that enables lower latency and effect on the time of transfer data between cores, impact of fault and bandwidth utilization for evaluation of mesh and bruijn architectures. We also carry out the high-level simulation of on chip network using NS-2 to verify the analytical analysis. Index TermsNetwork on chip (NoC), Bruijn,mesh, MPSoC (Multiprocessor Systems-on-Chip), performance.
1 INTRODUCTION
Current core based on SOC methodologies will not respond to the needs of the billion transistor era. Network on Chip (NOC), a new chip design paradigm concurrently proposed by many research groups[1],[2],[3] is expected to be an important architectural choice for future SOCs. The proposed NOC architectures offer a general but fixed communication platform which can be reused for a large number of SOC designs. A concept of computer network in layers based on the classical OSI reference model is used by all of proposed NOC architectures. We predict that NOC architecture would facilitate reuse at various levels of system design, thus reducing the time to design and test. However, NOC research is still in its infancy. A higher-level modelling will give us the insight of knowing more about its architecture. We would use the tool, Network Simulator ns-2 [4],[5] which has been extensively used in the research for design and evaluation of public domain computer network, to evaluate various design options for NOC architecture, including the design of router, communication protocol, routing algorithms. This paper reports some experimental results based on the simulation of NOC using ns-2. In the following, we give a brief overview of our NOC architecture and introduction to ns-2. In section II, we describe how various aspects of our NOC architecture was modelled using ns-2. As semiconductor technology improves, the number of processing cores integrated on a single chip has continually increased. To connect many cores on a chip, Network-on-Chips (NoCs) [6, 7, 8] that introduce a packetswitched network structure have been widely employed instead of traditional bus-based on-chip interconnects. The performance bottleneck imposed by on-chip interconnects in the deep submicron regime of process technology has been widely documented [9], as have the benefits of standardization of on-chip communication [10]. Implementing a standardized communication architecture such as a packet-switched NoC for massively integrated multiprocessor systems provides an abstraction of the global interconnection link and can greatly reduce design effort, potentially at the cost of some area and possibly power and performance penalties. The suitability of the NoC as a communication architecture depends on the overall system; i.e. the number of autonomous functioning blocks, the degree of parallelism, and area and performance requirements dictate its usefulness [11].
2 BACKGROUND
On-chip interconnection is a widely studied research field and good overviews are presented [12],[13], which illustrate the various interconnection schemes available for present ICs and emerging Multiprocessor Systems-onChip (MPSoC) architectures. A NoC-based interconnection is able to provide an efficient and scalable infrastructure, which is able to handle the increased communication needs. The network architecture, or topology, describes the physical organization of the interconnections network. A network topology can be classified as being either direct or indirect. A node in a network can be a terminal node, which acts as a source and sink for data, a switch that routes data, or both. In a direct network, every node acts as a terminal node. In an indirect network, a node is either a terminal or a switch node. A direct network can be redrawn as indirect by redrawing each node as two nodes and showing the switch and terminal nodes separately. Designers of large-scale SoCs must be aware of the advantages and disadvantages of each architecture in order to select an appropriate candidate for their implementations. The metrics that are of interest can be broadly categorized as [14]: performance (latency, throughput, cross-section bandwidth), Energy consumption, Reliability (error detection and/or correction), Scalability,
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link failure and scrambled messages, a fault-tolerant communication protocol suite, including error-resilient coding schemes, are needed to ensure the reliable delivery of on-chip messages on top of an unreliable on-chip communication substrate. Time to Failure Faults, can occur throughout the lifetime of an IC. Using the point when the chip is packaged and tested as the watershed event, we distinguish between before-shelf faults and after-shelf faults. Currently, chips with before shelf faults, i.e., defects which are discovered during testing, are invariably discarded. Only dies with no discovered defects are shipped out as products. With the shrinking feature size, it is becoming increasingly difficult to achieve decent yield with reasonable cost. The low yield problem will become more acute for the 90nm technology and beyond. On the other hand, the potential yield of the manufacturing process can increase tremendously if some defects on the die can be tolerated in the ICs after-shelf life. Static fault masking and isolation techniques, both hardware and software based, can be used to use these previously deemed Bad chips in commercial products, such as Pico Chip [18]. For after-shelf faults, dynamic fault detection and recovery means are needed to ensure the correct function of the chip as long as possible. Furthermore, graceful degradation of system performance is necessary for some mission-critical Applications.
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SIMULATION FRAMEWORK
These topologies simulated by NS2 (a network simulator). We reduce all parameters as multiply of 1000 to support the simulation time. To compare of these architectures in term of packet forwarding we consider the bandwidth between switches is one megabit/Sec and all link in mentioned topologies was duplex link. The bandwidth between resources and switches is ten times bigger than the bandwidth of switches to switches. We consider the traffic source for each communicated core was UDP, and the bandwidth of cores that needs was equal to one Megabit/Sec and the delay of switch-to-switch or resource to switch is equal to 10 milliseconds.
In this section, four parameters communication load, Fault-Tolerant, End-to-End Delay and Hop count defined for evaluation performance of our architectures.
5.1 Throughput and communication load We consider that two resources 0 and 126 are communicating together that have the maximum distance in diameter of network. A permanent fault between switches 5 and 7 has occurred at time 1.0. This permanent fault occurs in places that we have communication, as shown in fig .3, the communication load has reduces in both topologies.
5.2 Fault-Tolerant The faults that occur in NoC have two types as below: Permanent Faults. Transient Faults. Depend the nature of fault that was when and where tacked place, we consider a permanent fault that occurs in time 1.0, with three hops distance from the
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As shown in fig.6, the Bruijn has fewer hop count related mesh architecture. These hop count has not effect on fault or bandwidth. The hop count effects on the time of transfer data between resources.
As shown in fig .4, when a permanent fault occurs in communication path, the number of lost packets in Bruijn topology was less than mesh topology.
Through details simulation-based analysis of the reliability and network performance, we can conclude the Bruijn NoC in this paper could empower high throughput of data transmission with dramatic lower hop-Count.
REFERENCES
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As shown in fig .5, the average end to end delay between of mentioned cores in Bruign is fewer than Mesh architecture. This means the transfer rate in Bruijn NoC is faster than mesh NoC, with equal switches and resources.
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interconnection networks. In Proc. DAC, pages 684689, 2001. [11] A. Y. Weldezion, M. Grange, D. Pamunuwa, Zhonghai Lu, A. Jantsch, R. Weerasekera, H. Tenhunen, "Scalability of Networkon-Chip Communication Architecture for 3-D Meshes," Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NOCS'09), San Diego, pp. 114-123, May 2009. [12] J.Duato, S. Yalamanchili, andN. Lionel, InterconnectionNetworks:An Engineering Approach. San Francisco, CA: Morgan Kaufmann Publishers Inc., 2002. [13] W. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann Publishers Inc, 2003. [14] D. Bertozzi, Network architecture: Principles and examples, in Networks on Chips: Technology and Tools, ser. The Morgan Kaufmann Series in Systems on Silicon, G. D. Micheli and L. Benini, Eds. Morgan Kaufmann, Jul. 2006, ch. 5, pp. 147202. [15] B. Feero and P. Pande, Performance evaluation for threedimensional networks-on-chip, in IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI07, pp. 305310, 2007. [16] D. K. Pradhan. Fault-Tolerant Computer System Design. PrenticeHall, Inc., 1996. [17] T. Dumitras, "On-Chip Stochastic Communication", Electrical and Computer Engineering, May 1st, 2003. [18] W. Robbins. Redundancy and binning of picoChip processors. Fall Processor Forum, 2004, San Jose, CA. [19] E. Beyne, 3D system integration technologies, In International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, April 2006, 19. [20] E. Beyne, The rise of the 3rd dimension for system integration, In Proc. of International Interconnect Technology Conference, Burlingame, CA 57 June, 2006, 15. [21] J. Joyner, R. Venkatesan, P. Zarkesh-Ha, J.Davis, and J.Meindl, Impact of three dimensional architectures on interconnects in gig scale integration, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9 (Dec. 2001) (6): 922928. [22] Nostrum, http://www.imit.kth.se/info/FOFU/Nostrum. [23] Y-R. Sun, S. Kumar, and A. Jantsch, "Simulation and evaluation of a network on chip architecture using ns-2", In Proceedings of the IEEE NorChip Conference, November 2002.