limits of the technology imposed by the laws of physics (Hoeneisen and Mead, 1972;Keyes, 1987). We thus find that VLSI technology is well matched to neural networks fortwo principal reasons (Boser et al., 1992):
The high functional density achievable with VLSI technology permits the implemen
tation of a large number
identical, concurrently operating neurons on a single chip,thereby
it possible to exploit the inherent parallelism of neural networks.
The regular topology of neural networks and the relatively small number
defined arithmetic operations involved in their learning algorithms greatly simplifythe design and layout of VLSl circuits.Accordingly, we find that there is a great deal
research effort devoted worldwide toVLSI implementations of neural networks on many fronts. Today, there are general
purpose chips available for the construction of multilayer perceptrons, Boltzmannmachines, mean
theory machines, and self
organizing neural networks. Moreover,various special
purpose chips have been developed for specific information
processingfunctions.VLSI technology not only provides the medium for the implementation of complexinformation
processing functions that are neurobiologically inspired, but also can be seento serve a complementary and inseparable role as a synthetic element to build test bedsfor postulates of neural organization (Mead, 1989). The successful use of VLSI technologyto create a bridge between neurobiology and information sciences will have the followingbeneficial effects: deeper understanding of information processing, and novel methods forsolving engineering problems that are intractable by traditional computer techniques(Mead, 1989). The interaction between neurobiology and information sciences via thesilicon medium may also influence the very
of electronics and VLSI technology itself by having to solve new challenges posed by the interaction.With all these positive attributes of VLSI technology, it is befitting that we devote thisfinal chapter of the
as the medium for hardware implementations of neuralnetworks. The discussion will, however, be at an introductory level.'
The material of the chapter is organized as follows. In Section 15.2 we discuss the basicdesign considerations involved in the VLSI implementation of neural networks. In Section15.3 we categorize VLSI implementations of neural networks into analog, digital, andhybrid methods. Then, in Section 15.4 we describe commercially available general
purpose chips for hardware implementations of neural networks. Section 15.5on concluding remarks completes the chapter and the book.
Major Design Considerations
The incredible functional density, ease of use, and low cost of industrial
make CMOS technology as the technology of choice for VLSI implementations of neural networks (Mead, 1989). Regardless of whetherwe are considering the development of general
purpose chips for neuralnetworks, there are a number of major design issues that would have to be considered in
For detailed treatment of analog
systems, with emphasis on neuromorphic networks, see the book by Mead (1989).
specialized aspects of the subject, see the March 1991, May 1992, and May 1993 SpecialIssuesof the
Transactions on Neural Networks.
The report by Andreou (1992) provides an overview
systems with emphasis on circuit models of neurons, synapses, and neuromorphic functions.