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Table Of Contents

1.2 Tutorial Design Example
1.3 Manual Conventions
2.1 Copy A Sample Synthesis Setup File
2.2 Verify/Edit the Synthesis System Variables
2.3 Setup the Synopsys VSS Simulation (VHDL Only)
3.1 Setup the Design Test Bench for Cadence Cwaves
3.2 Run the Simulator and Open the Waveform Viewer
3.3 Load Data for the Waveforms
3.4 Select and Display Signals
4.1 Start the Synopsys Design Analyzer
4.2 Open the Design Analyzer Command Window
4.3 Analyze the RTL Model
4.4 Elaborate the Design
4.5 Specify Clock Constraints
4.6 Set Test Methodology and Scan Test Style
4.7 Set Other Design Constraints
4.8 Compile the Design
4.9 Check the Design Rules
4.10 Check the Test Design Rules
4.11 Estimate Test Fault Coverage
4.12 Perform Area and Timing Analysis
4.13 Insert Scan Test Circuitry
4.14 Optimize the Scan Design
4.15 Check Test Design Rules & Report Scan Path
4.16 Save the Core Design
4.17 Generate the Chip RTL Model (Verilog)
4.18 Generate the Chip RTL Model (VHDL)
4.19 Analyze, Elaborate and Constrain the Chip
4.20 Set Dont Touch Attribute on the Core
4.21 Set Pad Attributes
4.22 Insert Pads & Optimize the Design
4.23 Define the Chip Scan Input Pins
4.24 Define the Chip Scan Output Pin
4.25 Check Test, Report Scan Path & Save Design
4.26 Save the Design in HDL and Export Formats
4.27 Specify Test Timing Parameters
4.28 Generate Test Vectors
4.29 Analyze Fault Coverage
4.30 Format Test Vectors
4.31 Generate TestSim (Fault Simulation) Libraries
4.32 Fault Simulate ATPG Vectors in Parallel Mode
4.33 Compare TestSim & Test Compiler Fault Coverage
4.34 Fault Simulate ATPG Vectors in Serial Mode
5.1 Setup the Test Bench for Gate-Level Simulation
5.2 Run Simulation and View Waveforms
6.1 Start Cadence Tools
6.2 Create a Cadence Design Library
6.3 Import the Verilog File
6.4 Open the Schematic
6.5 Suppress Solder On CrossOver Warnings
6.6 Replace Shadow Library Cells
6.7 Add Power Pads
6.8 Check Supply I/O
6.9 Check and Save the Design Hierarchy
7.1 Open the Design in a Hierarchy Browser
7.2 Specify the Chip Global Signal Names
7.5 Start Cell Ensemble
7.6 Initialize the Layout
7.7 Place the Design
7.8 Insert I/O Corner Cells
7.9 Create Routing Channels
7.10 Set Net Properties
7.11 Route the Global Signals
7.12 Route the Whole Chip
7.13 Run the CMC Scripts
7.14 Create a Layout View
7.15 Save the Design
7.16 Place the CMC Logo
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Published by: Kesani Venkat Narsimha Reddy on Apr 09, 2012
Copyright:Attribution Non-commercial


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