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Phn 1: Cc ch th hp dch. Chng trnh dch Assembly lm vic trn file chng trnh ngun v mt file ngun bao gm : cc lnh , cc nhn v cc ch dn.Chng c xp tun t trong file ngun. Mt dng lnh c chiu di cc i l :120 k t. Mi dng lnh u c th t trc bi mt nhn,n l mt chui k t v kt thc bng du 2 chm.Nhn c s dng nh l ch cho cc lnh nhy, V cc ch th r nhnh.V cn c s dng nh l tn bin trong b nh chng trnh v b nh d liu. Mt dng lnh c th l mt trong bn dng sau: 1. [nhan: ] ch_th [ton_hng] [;li ch thch] 2. [nhan: ] lnh [ton_hng] [;li ch thch] 3. ;ch thch 4. dng trng (khng cha k t no) Mt li ch thch lun i sau du chm phy(;)v n khng c dch sang m my ch c tc dng cho ngi c chng trnh d hiu. Chng trnh Assembly h tr mt s cc ch th.Cc ch th ny khng c dch ra m nh phn (m my).V n c s dng iwuf khin qu trnh dch v c th l : iu khiu ghi lnh vo b nh chng trnh, nh ngha cc bin 1
1.3.DB: nh ngha cc hng s kiu byte c lu trong b nh chng trnh hac b nh EEPROM.V ch th ny lun theo sau mt nhn .Ch th ny thng c s dng trong vic lu gi cc bng v cc biu thc (nhng c th tnh ra gi tr cui cng) .Cc nhn chnh l a ch khi u cho gi tr ban u ca bng.Ch dn ny ch c th t c trong on m hoc on b nh EEPROM. Cc phn t trong bng c phn bit bng du phy. C php: Label: .DB danh_sach_biu_thc V d: .CSEG Sin: .DB 0,1,2,3,4,6,7 .ESEG const: .DB 1,2,3 Ch : Mt s hay mt biu thc (phi c kt qu) nm trong khong 128 n 255.Nu s l s m th s c lu di dng 8bit m b 2. 4.DEF: 3
Phn 2: Vit lnh cho VK Trc khi chng ta vit lnh cho VK th cn nm c cc vn sau: 1.Cu trc b nh chng trnh v b nh d liu. 2. Cc cch nh a ch. 3.Cc thanh ghi chc nng c bit. 4.Cc lnh c th 5.Mt chng trnh mu. 6.Lp trnh cu trc. 7.Chng trnh con v Macro. Ta ln lt tm hiu tng ni dung.
Ht vc t ngt.
ch d ny da ch ca thanh ghi c ly trc tip t vng cc thanh ghi (t 0 ti 31) V d: COM Rd NEG Rd 2.2.2. a ch hai thanh ghi trc tip: y l ch m trong mt lnh ALU truy nhp trc tip vo hai thanh ghi.
Ch ny hon ton tng tng nh ch trn. V d: ADD Rd,Rr 2.2.3. a ch trc tip cng vo ra:
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Trong a ch ca ton hng c cha trong 6 bit ca mt t lnh .n l a ch ca thanh ghi ngun hoc ch. V d: Out DDRB,R16 In R12, DDRB 2.2.4.Trc tip d liu: a ch ca d liu trong RAM c a trc tip vo lnh V d: LDS R12,0x0fff STS 0x0fff,R11 2.2.5. a ch d liu dn tip cng vi dch chuyn: V d: LDD R11,Y+10 a ch ca ton hng ngun hac ch c tr bi thanh ghi Y hoc Z cng thm mt ch s no 2.2.6. a ch gin tip d liu: y l cch m CPU truy nhp ti d liu trong RAM thng qua thanh ghi X,Y,Z a ch ca d liu c lu trong thanh ghi ny. V d: ST X,R11 LD R13,Y 2.2.7. a ch d liu dn tip cng vi tng hoc gim con tr: V d: LD R17,X+ LD -Y,R14 . 11
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2.5.Mt chng trnh mu ;chuong trinh dau tien ;khia bao thiet bi .DEVICE AT90S8535;khai bao thit b .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .def tam=R16 ;dinh nghia mot ten moi cho thanh ghi R16
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3.2.6. Lp trnh cu trc trong Assembly: Mi ngi thng ni y l im mnh cu ngn ng bc cao ! Vng ng vy.Nhng iu khng c ngha l ngn ng cp thp nh assembly li khng lm c. vit c cc dng cu trc nh trong cc ngn ng bc cao i hi cc bn phi vit nhiu v rt nhiu.Sau y ti s vit mt vi v d cc bn tham kho. 1. if (iu kin) { khi lnh } else { khi lnh } v c th nh sau: Nu R10 = 0xff th copy thanh ghi R10 vo thanh ghi R11 v nu khng bng th a gi tr 0 vo thanh ghi R11 ;doan chuong trinh viet theo cach 1: ldi R0,0xff cp R10,R0 brne else mov R11,R10 rjmp endif else: ldi R11,0x00 endif: ;doan chuong trinh viet bang cah 2: ldi R0,0xff cp R10,R0 breq then ldi R11,0x00 rjmp endif then: mov R11,R10 endif: 2. 17
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ret ;ket thuc chuong trinh con. Khi chng trnh chnh chy ti lnh gi chong trnh con (rcall sub16 th con tr PC s tr ti ni luugwx chng trnh con v c th l nhn sub16.Thc hin ht cc dng lnh cho ti khi gp lnh RET th con tr PC li tr ti lnh ngay sau lnh rcall.Qu trnh ct PC v khi phc PC th CPU s dng ngn xp.(S c ni sau) Macro: nh ngha Macro trc ht ta hy xt mt v d v Macro: .Macro sub16 ;khai bao macro ;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro ;ket thuc macro T v d cc bn c th thy mt macro c khai bo bng ch th macro ( ni trc) (Ti sao li l ch th?).Ti xin c nhc li mt cht l :Ch th l nhng ch dn gip cho chong trnh dich dch cc lnh trong file ngun m thi n khng phi l mt lnh ca vi diu khin (chng ta s li tr li vn ny sau) Nh vy vit mt macro cc bn dng ch dn MACRO khai bo.Tham s i ngay theo sau ch dn ny chnh l tn ca macro (N c ngha g ?)v theo sau tn c th l cc tham s hoc khng (chng c cch nhau bi du phy) Sau khi khai bo macro l khi lnh m cc bn mun thc hin. kt thc macro th cc bn dng ch dn .endmacro Macro s lm vic nh th no ?Ta s tm hiu qua v d sau: ;chuong trinh su dung macro ;khia bao thiet bi .DEVICE AT90S8535 .DSEG ;khai bao doan du lieu var1: .BYTE 2 .CSEG ;khai bao doan chuong trinh .Macro sub16 ;khai bao macro 21
.Macro sub16 ;khai bao macro ;Macro chu hai byte 16bit ;bien vao :xh,xl ; yh,yl ;bien ra:xh,xl va co C sub xl,yl sbc xh,yh .endmacro .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 rjmp start .org 0x0001 rjmp int_0 .org 0x0011 start: ldi xh,0x0 ldi xl,0xa ldi yh,0x0 ldi yl,0x5 sub16 rcall add16 here: rjmp here 24
.include "macro.asm" ;mo file chua cac modul va doc .include "8535def.inc" ;mo va doc tep nay (copy noi dung cua tep nay vao chuong trinh) .org 0x0000 rjmp start 25
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V tng thit b mt s c hi nu nh khng c nhu cu chao i d liu th CPU s hi thit b khc. u im ca phng php ny l: CPU ch ng v phn c quyn u tin.Nhng nhc im ca phng ohp ny l :Khng p ng c cc s kin tc thi xy ra (V nh c mt thit b c yu cu chao i d liu khn cp m vn ch ti lt c hi),v trong thi gian hi trng thi ca cc thit b th cpu khng th lm vic khc, iu ny lm lng ph ti nguyn x l ca CPU. 2.Phng php vo ra bng ngt. Ngt l nguyn tc cho php thit b ngoi vi bo cho CPU bit v kh nng sn sng chao i d liu ca mnh. Cc bn c th t tm thy u v nhc im ca phng php ny. Trn VK c 32 ng vo ra gm nhiu chc nng c th s dng lm cng vo ra s ,cho cc thit b ngoi vi tng t.Sau y ta s tm hiu tng thit b ngoi vi v cc cng vo ra.(mc ch ca phn ny l hiu c cu to v c th iu khin vo ra d liu c chng).
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Tm li: 1. c d liu t ngoi th ta phi thc hin cc bc sau: Da d liu ra thanh ghi iu khin DDRxn t cho PORT (hoc bit trong port) l u vo (xa thanh ghi ddr hoc bit) Sau kch hot in tr pull-up bng cch set thanh ghi PORT( bit) Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit) Sau y l mt v d: V d 1: c cng PA vo thanh ghi R16 ;chng trnh bt u ldi R17,0x00 sts $3a,R17 ; nh ngha port A l cng vo ser R17 ;set thanh ghi R17 sts $3b,R17 ;Kch hot in tr pull-up in R16,PINA V d 2 : t cng PA thanh hai na byte.Mt na thp l cng ra cn na cao l cng vo. Ldi R17,0x0f Out DDRA,R17 ; nh ngha SER R17 OUT PORTA,R17 IN R16,PINA
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Bn thy y bn a vo t ci mt mi ti ci th 3 v mun ly ci th 1 ra th bn khng th tho ra ly m phi ly ci th 3 ri n th 2 ri mi ly c ci th nht (Tm hiu nh th).Nhng trong ti liu ca hng sn xut khng thy ni ti b nh ngn xp?vng n l vng bt k trong SRAM t a ch 0x60 tr ln. truy nhp vo SRAM thng thng th bn dng con tr X,Y,Z v truy nhp vo SRAM theo kiu ngn xp th bn dng con tr SP.Con tr ny l mt thanh ghi 16 bit v c truy nhp nh hai thanh ghi 8 bit chung c a ch :SPL :0x3D/0x5D(IO/SRAM) V SPH:0x3E/0x5E. Khi chng trnh phc vu ngt hoc chng trnh con th con tr PC c lu vo ngn xp trong khi con tr ngng xp gim hai v tr.V con tr ngn xp s gim 1 khi thc hin lnh push.Ngc li khi thc hin lnh POP th con tr ngn xp s tng 1 v khi thc hin lnh RET hoc RETI th con tr ngn xp s tng 2.Nh vy con tr ngn xp cn c chng trnh t trc gi tr khi to ngn xp trc khi mt chng trnh con c gi 33
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iu khin khi giao tip SPI th chng ta c 3 thanh ghi. l 1 thanh ghi iu khin:SPCR(SPI control Register).Mt thanh ghi trang thi SPSR (SPI status Register) V cui cng l thanh ghi d liu SPDR(SPI Dt Register). 35
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y l s ghp ni gia hai b SPI song cng (nh ca 2 vi iu khin AVR). i vi VK AVR th cc chn SCK (Serial clock) l chn PB7,y l chn xung nhp ra trong trng hp n l Master v l chn xung nhp vo nu n l Slave.khi ghi d liu ln thanh ghi d liu SPDR ca khi Master s khi ng b to xung v d liu c dch v a ra chn MOSI (PB5) v vo chn MOSI ca slave (PB5 i vi AVR).Sau khi dch ht mt byte b to xung ngng hot ng,v c SPIF c pht bo kt thc truyn.Nu nh ngt ny c php th chng trnh phc vu ngt s c phc v v khi c s b xa.u vo la chn slave (SS v l chn PB4) c set mc tch cc thp la chn thit b SPI slave v c dng cho vic ghp ni nhiu VK.Hai thanh ghi dch ca hai b truyn v nhn (Master v slave) c xem nh l mt thanh ghi dch vng 16 bit.V trong mt ln chao i d liu th d liu thanh ghi ca Master v slave chao i cho nhau.Mt bSIP lm ng thi c hai nhim v truyn v nhn nhng chng li ch c mt b m khi truyn c hai b m khi nhn.Nh vy c ngha l d liu truyn i s khng c ghi ln thanh ghi d liu truyn nu nh byte 38
Hai VK AVR c ghp vi nhau theo giao din SPI .Vit chng trnh con lp mt VK l master v ci cn li l Slave.Ly 10 byte trong b nh SRAM k t v tr 0xff g sang vi iu khin th hai. vi iu khin th hai nhn 10 byte ny v ghi vo SRAM kt t v tr oxff.Bit chng hot ng cung xung nhp. Chng trnh vi master: ; on khi to cng sbi 0x17,7 ;set bit DDBR7 - t SCK l chn ra. cbi 0x17,6 ;xa bit DDBR6-t PB6 l cng vo. sbi 0x18,6 ;set bit PORTB6-Kch hot in tr ko. sbi 0x17,5 ;t PB5 l chn ra. sbi 0x17,4 cbi 0x18,4 ;t xong cu hnh cc chn ;Tc dng ln tng bit khng nh hng n cc chn khc. ;By gi tip tc t cu hnh cho SPI 39
3.5.Watchdog timer:
3.6. B nh ROM c th c xa bng in: EEPROM B nh EEPROM l mt b nh khng b mt d liu khi ngun in cung cp b ngt.D liu trong n c th c ghi v xa bng in v v vy vic ghi v c b nh ny VK c th lm trc tip. B nh ny c xem nh mt b nh d liu nhng chng khng c truy nhp nh mt b nh SRAM m c truy nhp nh mt thit b ngoi vi.Thi gian truy cp vit mt khong 2.5 n 4 ms,v ph thuc vo ngun in cung cp cho vi iu khin (Vcc). iu khin vo ra d liu vi EEPROM chng ta c th s dng 3 thanh ghi l:EEPROM address ,EEDR v EECR. 40
L thanh ghi 8 bit trong c 4 bit c nh ngha iu khin hot ng ghi c d liu b nh EEPROM. -Bit 3-EERIE :EEPROM ready interrupt enable Bit ny cho php ngt hat ng (thng bo cho CPU bit kh nng chao i d liu vi CPU.).Nu bit ny c set 1 th n c php hot ng.V ngc li. -Bit 2-EEMWE: EEPROM master write enable. Bit ny khi c set 1 s ghi d liu t thanh ghi EEDR vo nh c a ch lu trong thanh ghi EEAR ca EEPROM. Bit ny c set bng phn mm v c xa bng phn cng sau bn chu khi my. -Bit 1-EEWE: EEPROM write enable y l bit cho php ghi d liu vo EEPROM trnh trng hp ta ghi d liu khi m mt d liu trc cha c ghi xong.N c xo bng phn cng khi m s liu c ghi xong vo EEPROM. -Bit 0-EERE : EEPROM read enable Bit ny ra lnh cho CPU c d liu t b nh ny ra thanh ghi d liu vi a ch lu bn trong thanh ghi a ch.V n c xa bng phn cng khi m d liu c c ra thanh ghi d liu. Vy ghi d liu vo EEPROM ta lm cc bc sau: Bc1:ch i bit EEWE b xa cha ? Bc 2:Ghi d liu mi vo thanh ghi d liu (EEDR) Bc3:Set bit EEWE ri n bit EEMWE bt u ghi d liu. 41
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3.EEDR:EEPROM data register y l thanh ghi 8 bit lu d liu ly ra t EEPROM hoc d liu nh ghi vo EEPROM.
3.7. B so snh tng t: Analog comparator B so sanh tng t ca AVR c u vo li hai chn PB2 v PB3 (nh hnh v).Vi chn PB2 c ni vo cc dng ca b so snh v PB3 c ni vo cc m ca b so snh.N to ra hai mc logic nu V+>V- th tn hiu ra l 1 v ngc li l 0.
iu khin v qua st trng thi ca b so snh tng t ta c mt thanh ghi l thanh ghi ACSR.Trc khi tm hiu v nguyn tc hot ng ca n ti s gii thiu cho cc bn v thanh ghi ny. Thanh ghi ACSR l mt thanh ghi 8 bit c a ch trong cc thanh ghi I/O l 0x08 v c a ch trong khng gian b nh SRAM l 0x28.Trong 8 bit th c 7 bit c nh ngha v bit 6 khng c nh ngha.N ch c th c v lun c gi tr logic l 0. 1.Bit 7-ACD:Analog comparator disable y l bit iu khin. Bit ny ttrc tip iu khin hot ng ca AC(b so snh tng t).Nu nh bit ny c set ln 1 th ngun cung cp cho AC hot 43
T s khi cc bn c th thy: Tm u vo ca ADC l tm chn ca PORTA v chng c chn thng qua mt MUX. iu khin hot ng vo ra d liu ca ADC v CPU chng ta c 3 thanh ghi:ADMUX y l thanh ghi iu khin la chn knh u vo cho ADC . ADCSR y l thanh ghi iu khin v thanh ghi trng thi ca ADC. ADCD :y l thanh ghi d liu. Sau y l tng thanh ghi: 1.ADMUX: Multiplexer select register y l thanh ghi iu khin 8 bit:
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Ch :Nu nh ta thay i knh trong thi im m ADC anh chuyn i th khi qu trnh chuyn i hoang thinh th khn vo mi c thay i. 2.ADCSR :ADC control and status register y l thanh ghi iu khin v lu trng thi ca ADC:
Bit 7-ADEN:ADC enable y l bit iu khin hot ng ca ADC .Khi bit ny c set 1 th ADC c th hot ng v ngc li.Nu nh ta ngng hot ng ca ADC trong khi n ang chuyn i th n s kt thc qu trnh chuyn i.Mc d cha chuyn i xong. Bit 6-ADSC: ADC start conversion
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