1 The Hoanh

LI CM N
c c thi gian thc tp v lm vic hiu qu u tin cho em xin gi li cm n chn thnh n Trng i Hc Cng Ngh v Truyn Thng B mn Cng Ngh K Thut My Tnh to iu kin tt nht cho em c th hon thnh tt t thc tp ca mnh. Bn cnh , em xin cm n s hng dn tn tnh ca c Lu Th Liu gip em hon thnh tt t thc tp ny. Thiu s gip ca c em khng th c c kt qu nh ngy hm nay. Trong qu trnh thc tp, cng nh trong qa trnh lm bo co, em kh trnh khi sai st. Rt mong cc thy c trong b mn v c gio Lu Th Liu b qua v ch dn thm cho em. Em xin chn thnh cm n.

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Li Ni u
Trong thi i cng nghip ha hin i ha t nc, cng vi s pht trin vt bc v cng ngh l cc ng dng ca k thut vi iu khin, vi tc pht trin nhanh chng k thut vi iu khin mang n nhng thay i trong khoa hc cng ngh cng nh trong i sng hng ngy, cc sn phm ca vi iu khin ngy cng nhiu hn v c ng dng rng ri hn trong tt c cc lnh vc sinh hot hng ngy. Bin qung co in t ch l mt ng dng rt nh trong nhng ng dng ca vi iu khin v cng gp phn khng nh n i sng sinh hot hng ngy ca con ngi cng nh trong lnh vc qung co. V bin qung co in t tr thnh mt phn quan trng trong lnh vc qung co v n c th thu ht c s ch ca mi ngi, v bn hn hn cc bin qung co thng thng khc. ti ng dng AVR thit k bin qung co cho ca hng BOOK NEW ti H Ni l mt phn nh phc v trong vic thit k bin qung co. Thng qua ti ny trc tin em c th thit k c bin qung co cho ca hang BOOK NEW, sau em c th vn dng nhng g hc thit k bin qung co in t vi nhiu hnh thc khc nhau v nhng ng dng ca vi iu khin AVR vo thc t mt cc dng v tin li hn Do trnh v kinh nghim trong thc t ca em cn nhiu non km, nn ti ca em chc chn cn nhiu thiu st. V vy em rt mong nhn c nhng kin ng gp qu bu ca cc thy c v ton th cc bn. .

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CHNG 1: TNG QUAN

1.1 Gii thiu h thng bin qung co.
1.1.1 Qung co
Hng ngy, d bt c u chng ta cng u bt gp nhng loi hnh qung co khc nhau : trong nh th l trn ti vi, i radio, internet cn ngoi tri th l cc bng rn, bng, bin qung co v thm ch l c t ri na. Vy qung co l g v ti sao li phi qung co ? Qung co l hnh thc tuyn truyn, gii thiu thng tin v sn phm, dch v, cng ty hay tng. Qung co l nhng n lc nhm tc ng ti hnh vi, thi quen mua hng ca ngi tiu dng hay khch hng bng cch cung cp nhng thng ip bn hng theo cch thuyt phc v sn phm hay dch v ca ngi bn. Cc nh hng, cng ty, doanh nghip tham gia cc hot ng qung co khng ngoi mc ch qung b hnh nh, gii thiu sn phm, dch v, thng tin ca h t thu ht c thm cc khch hng tim nng, nng cao tnh cnh tranh v em li nhiu ngun li cho cng ty. Cc loi hnh qung co ph bin hin nay : Truyn hnh. Internet. Bo ch. Pht thanh. Qung co trc tuyn. Qung co bng s dng bin qung co

1.1.2 Qung co s dng bin qung cao bng ma den led.

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- Mt s c trng. LED (Light Emitting Diode i t pht quang) l cc loi i t c kh nng pht ra nh sng hay tia hng ngoi, t ngoi. Cng ging nh i t, LED c cu to t mt khi bn dn loi P ghp vi mt khi bn dn loi N. Hot ng ca LED cng ging nh nhiu loi i t bn dn khc : khi bn dn loi P cha nhiu l trng t do mang in tch dng nn khi ghp vi khi bn dn loi n cha cc in t t do th cc l trng ny c xu hng chuyn ng khuch tn sang khi N, cng lc khi P li nhn thm cc in t (in tch m) t khi N chuyn sang. Kt qu l khi P tch in m (thiu ht l trng v tha in t) trong khi khi n tch in dng (thiu ht in t v tha l trng). bin gii hai mt tip gip, mt s in t bi l trng thu ht v khi chng tin li gn nhau, chng c xu hng kt hp vi nhau to thnh cc nguyn t trung ha. Qu trnh ny c th gii phng nng lng di dng nh sng (hay cc bc x in t c bc sng gn ). Ty theo mc nng lng gii phng l cao hay thp m bc sng nh sng pht ra khc nhau (tc mu sc ca LED s khc nhau). Mc nng lng (v mu sc ca LED) hon ton ph thuc vo cu trc nng lng ca cc nguyn t cht bn dn. Thng thng LED c in th phn cc thun cao hn cc loi i t khc khong 1,5 n 3V nhng in th phn cc ngc LED li khng cao. Qung co bng n led n LED thc s l c cch t ph mi trong cng ngh cao ni chung v trong qung co ni ring. l cc bng hiu, bng ch dn, panel qung co c s dng n LED v mch in t to hiu ng nh sng. Qua tm hiu ta thy nhiu c im ni bt ca n nh bn ca n cao gp my chc ln bng n thng, v li rt t hao in, khng gy chy n, an ton tuyt i, chng rung ng tt, c bit l n vn sng r vo ban ngy v vy c th dng c nhng bin qung co trong nh (indoor) v ngoi tri (outdoor) cho hiu qu cao cng nh gy s ch ng thi truyn t thng tin n khch hng v ngi i ng.

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Bng in t c thng tin thay i c cn c gi l bng quang bo hay mn hnh in t LED, c nhiu mu sc, nhiu cch hin th sinh ng, d dng thu ht s ch ca mi ngi. Do d dng thay i thng tin trn bng in t nn y c xem l phng tin truyn t thng tin hin i, nhanh chng.

1.2 Kho st vn
Hin nay, nhng ng dng ca phn cng c s dng ngy cng nhiu v ph bin, i ti u chng ta cng c th nhn thy nhng bin qung co c s dng n led hin th thi gian, gi c,vv, thm ch hin nay v ang xut hin nhng bin qung co s dng cc ma trn led vi kch thc ln hoc s dng nhng tivi mn hnh led vo vic qung co. ti em chn xut pht t tng s dng vi iu khin AVR vo iu khin cho bin qung co ca hng BOOK NEW. Vi tng ny, ngi dng s c th thay th cc bin qung co thng thng v s khng cn phi quan tm n vn bin qung co ca mnh b m do vn thi tit, hoc thi gian...y ch l mt ng dng nh trong rt nhiu ng dng lin quan n vi iu khin AVR.

1.3 Cc vn cn gii quyt

Cc vn cn gii quyt ca tiTm hiu v ng dng vi iu khin AVR vo iu khin hin th ch trn LED ma trn nh sau: Ghp ni vi iu khin vi cc LED ma trn v cc IC dch 74HC154. C kh nng m rng v pht trin vo trong thc t. C an ton, bn cao. H thng chy n nh.

1.4 Mc ch ca ti
S cn thit, quan trng cng nh tnh kh thi v li ch ca mch s cng chnh l l do ti chn v thc hin n Tm hiu v ng dng vi iu khin AVR thit k bin qun co cho ca hng BOOK NEW nhm ng dng kin thc hc vo thc t.

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CHNG 2 VI IU KHIN AVR (ATMEGA 8), MA TRN LED 8x8, IC 74HC154.

2.1 Gii thiu vi iu khin AVR
Vi iu khin AVR l sn phm ca cng ty Atmel( Hoa k), y l mt b x l c kin trc kiu Harvard, ngha l n v x l trung tm c b nh chng trnh v mt b nh d liu tch bit. B vi iu khin AVR c nhiu kh nng gim nng lng tiu th. y l mt trong nhng im ln ca h vi iu khin ny. So vi cc chip vi iu khin 8 bits khc, AVR c nhiu c tnh hn hn, hn c trong tnh ng dng (d s dng) v c bit l v chc nng: Gn nh chng ta khng cn mc thm bt k mt linh kin ph no khi s dng AVR, thm ch khng cn ngun to xung clock cho chip (thng l khi thch anh). Thit b lp trnh (mch np) cho AVR rt n gin, c loi mch ch cn vi con in tr l c th lm c. Mt s chip cn h tr lp trnh on-chip bng bootloader khng cn mch np. Bn cnh lp trnh bng ASM, cu trc AVR c thit k tng thch vi ngn ng C. Ngun ti nguyn source code, ti liu trn internet rt ln. H vi iu khin AVR gm nhiu b iu khin vi cc ti nguyn khc nhau v b phn ngoi vi, b nh chng trnh v kiu ng v. Sau y l mt s vi iu khin h AVR v c im ca chng:

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B nh CT S B x l AT90S1200 AT90S2313 AT90S2323 AT90S2343 AT90S4433 AT90S8515 AT90S8535 ATTINY15L 20 20 8 10 8 40 40 8 4-6 4-6 4-6 4-6 8 4-6 4-6 2.7-5.5 12 10 10 10 8 8 8 1.6 1 2 2 2 4 8 8 1 Us Fmax (Kbyte

nhd liu flash 64 128 128 128 256 512 512 64

nhd

Cn g

A/D

32 128 128 128 128 512 512 . 1Kbyte 1Kbyte

15 15 3 5 20 32 32 6 6knh 6knh

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Hnh 1: Mt s vi iu khin v c im ca chng: AVR c rt nhiu dng khc nhau bao gm dng Tiny AVR (nh AT tiny 12, AT

tiny 22) c kch thc b nh nh, t b phn ngoi vi, ri n dng AVR ( chng hn AT90S8535, AT90S8515) c kch thc b nh vo loi trung bnh v mnh hn l dng Mega (nh Atmega32, Atmega128,) vi b nh c kich thc vi Kbyte n vi Kb cng vi cc b ngoi vi a dng c tch hp trn chp, cng c dng tch hp c LCD trn chip (dng LCD AVR). Tc ca dng mega cng cao hn cc dng khc, S khc nhau c bn gia cc dng chnh l cu trc ngoi vi, cn nhn th vn nh nhau.

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2.2 Kin trc ca vi iu khin AVR:

2.2.1 c im c bn ca AVR:
B nh flash c tch hp ngay trn chp c kh nng lp trnh ngay trn h thng c s dng lm b nh chng trnh. iu ny c ngha l ta khng cn phi dng n cc b nh EPROM hoc ROM bn ngoi cha m chng trnh. Hn na b nh chng trnh c th np c chng trnh trong khi b vi x l vn nguyn trn bn mch, khng cn nhc ra ngoi np. Cc thanh ghi lm vic a nng 32-X-8 . Mt tp hp bao gm rt nhiu thanh ghi c ngha l cc bin c th c l tr bn trong CPU ch khng phi lu tr cc bin trong b nh, v vic truy nhp ln b nh thng tn nhiu thi gian hn. Nh vy chng trnh s chy nhanh hn. B nh d liu ngay trn chip loi EEPROM v RAM c trong hu ht cc thnh vin ca h AVR. n v CPU c kin trc Harvard, cn cc b nh EEPROM v RAM c nhn nhn nh l b nh d liu v c dng ct gi cc hng v bin. Hot ng vi xung gi nhp c tn s t 0 n 10MHz. Hu ht cc lnh c thc hin trong mt chu k ng h lm cho tc x l ln hn khong 10 ln so vi 8051 cng tn s ca ng h gi nhp.C mch t li trng thi mi khi cp li in ngun cho h thng.

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C b nh thi ngay trn chp v lp trnh c vi mch chia tn s tch bit. B nh thi ny c s dng cho cc ng dng cn c s phn nh thi gian ca cc s kin. C cc ngun ngt bn trong v bn ngoi. C b nh thi watchdog ngay trn chip v lp trnh c vi b dao ng c lp. B phn ny c s dng khi phc li trng thi hot ng ca h thng trong trng hp xy ra li treo khi chy phn mm, ngoi ra cn c s dng cho mt vi ng dng khc. C cc ch hot ng nh: SLEEP v POWER DOWN( ngh hay gim dng tiu th khi khn cn thit). c im ny cho php tit kim nng lng khi b x l nhn ri. Nhiu chp c mch dao ng ng h RC ngay trn chp. Khi s dng b dao ng RC trn chp s lng cc linh kin ph tr s gim i.

H thng chp a dng t c nh n ln thun tin cho tn ng dng ring bit. 2.2.2 Kin trc h vi iu khin AVR
Cc b x l AVR c kin trc Harvard, ngha l c b nh d liu b nh chng trnh tch bit nhau:

B nh chng trnh l loi b nh flash. Dung lng ca b nh thay i

khc nhau gia cc b x l trong cng h. B nh ny c truy nhp theo tng chu k ng h, v mt lnh c np vo thanh ghi lnh. Thanh ghi lnh ni vi tp thanh ghi bng cch la chn xem thanh ghi no c ALU s dng thc thi lnh. Li ra ca thanh ghi lnh c gii m bng b gii m lnh quyt nh chn tn hiu iu khin no s c kch hot hon thnh lnh hin ti. B nh chng trnh, bn cnh cc lnh lu tr cng cha cc vect ngt bt u a ch $0000.

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Kin trc Harvard T chc b nh AVR:

Hnh 2: T chc b nh ca AVR. B nh d liu gm 5 thnh phn khc nhau: 1. Mt tp thanh ghi(register file) vi 32 thanh ghi c rng 8 bit. 2. 64 thanh ghi vo/ra mi thanh 8 bit. Cc thanh ghi ny thc cht l mt phn ca b nh SRAM trn chip v c th c truy nhp hoc nh b nh SRAM vi cc a ch gia $20 v $5F hoc nh cc thanh ghi I/O vi cc a ch gia $00 v $3F. S lng 64 thanh ghi ny c th thay i tu theo tng loi chip trong h AVR. 3. B nh SRAM bn trong: b nh ny c s dng cho ngn xp cng nh lu tr cc bin. Trong thi gian c ngt v gi on chng trnh, gi tr hin ti ca b

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m chng trnh c lu tr trong ngn xp. Kch thc ca ngn xp b gii hn bi b nh SRAM trn chip. V tr ca ngn xp c ch th bi con tr ngn xp. 4. B nh SRAM bn ngoi: c tnh ny ch c cc b x l c ln trong h vi iu khin AVR. 5. EEPROM: b nh EEPROM c sn trn hu ht cc b vi iu khin AVR v c truy nhp theo mt bn b nh tch bit. a ch bt u ca b nh EEPROM lun l $0000. Cc b x l khc nhau c t 64 byte n 4 Kbyte b nh EEPROM. B nh EEPROM c th ghi vo c khog 100000 ln.

2.2.3 Tp cc thanh ghi

Tt c cc b iu khin AVR u c 32 thanh ghi a nng. Mt s trong cc thanh ghi ny cn c cc chc nng ring, b sung. Cc thanh ghi c t tn t R0 n R31. Tp thanh ghi c tch thnh 2 phn, mi phn c 16 thanh ghi, nh s t R0 n R15 v R16 n R31. Tt c cc lnh thao tc trn cc thanh ghi u c th truy nhp trc tip v truy nhp trong chu trnh n n tt c cc thanh ghi. Nhng c mt ngoi l l cc lnh SBCI, SUBI, CPI, ANDI v ORI cng nh lnh WI, cc lnh ny ch tc ng n cc thanh ghi R16 n R31.

Hnh 3: Tp thanh ghi

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Cc thanh ghi R0 v R26 n R31 c cc chc nng b sung. Thanh ghi R0 c s dng trong cc lnh np b nh chng trnh LPM (Load Program Memory) , trong khi cc thanh ghi R26 n R31 c s dng lm cc thanh ghi con tr nh c minh ho trn hnh 2. Cc thanh ghi con tr nay c s dng trong nhiu lnh gin tip dng cho thanh ghi (register indirect instruction). 2.2.4 Khi logic s hc: Khi s hc lgic(ALU) thc hin cc thao tc nh thao tc bit; php tnh s hc v lgic trn ni dung ca cc thanh ghi c ch nh. Cc thao tc ny c thc hin trong mt chu k ngf h n l. Mi mt thao tc ALU u lm nh hng n cc c trong thanh ghi trng thi(STATUS), tu thuc vo lnh. 2.2.5 B nh EEPROM Tt c cc b vi iu khin AVR u c mt b nh EEPROM trn chip. Dung lng b nh EEPROM thay i t 64 byte trn b iu khin AT90S1200, Tiny10/12 n 4 Kbyte trn Mega103. Cc thanh ghi dng truy nhp EEPROM gm: thanh ghi a ch EEPROM(EEAR), thanh ghi d liu EEPROM(EEDR), v thanh ghi iu khin EEPROM(EECR). B nh EEPROM l mt b nh khng b mt d liu khi ngun in cung cp b ngt. D liu trong n c th c ghi v xa bng in v v vy vic ghi v c b nh ny c th lm trc tip. B nh ny c xem nh mt b nh d liu nhng chng khng c truy nhp nh mt b nh SRAM m c truy nhp nh mt thit b ngoi vi. Thi gian truy cp vit mt khong 2.5 n 4 ms, v ph thuc vo ngun in cung cp cho vi iu khin (Vcc). iu khin vo ra d liu vi EEPROM chng ta c th s dng 3 thanh ghi l:EEPROM address ,EEDR v EECR. ghi d liu vo EEPROM ta lm cc bc sau: - Bc 1: ch i bit EEWE b xa cha ?

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- Bc 2: Ghi d liu mi vo thanh ghi d liu (EEDR) - Bc 3: Set bit EEWE ri n bit EEMWE bt u ghi d liu. Ch : Nu nh dang ghi d liu EEPROM m xut hin ngt th d liu s khng c ghi mt cch an ton vo EEPOM. c d liu vo EEPROM th n gin hn. - Bc 1: kim tra bit EEWE nu nh c qu trnh ghi EEPROM th ch i. - Bc 2: a a ch cn c vo thanh ghi a ch EEAR - Bc 3: Set bit EERE ln 1 bt u qu trnh c. - Bc 4: Ch i oc xong bng cch kim tra bit EERE nu c xa th c d liu thanh ghi d liu. Sau c d liu.

2.2.6 B nh SRAM
B nh SRAM c trn hu ht cc b x l c gi thnh cao trong h AVR. Dung lng ca b nh SRAM thay i t 128 byte n 4 Kbyte. B nh SRAM c truy nhp bng cch s dng nhiu lnh truy nhp d liu trc tip hoc gin tip. B nh ny cng c s dng cho ngn xp. Thi gian truy nhp b h SRAM bng 2 chu k ng h. Trn cc b iu khin AVR c ln u c kh nng kt ni vi b nh SRAM bn ngoi. cho php truy nhp b nh SRAM ngoi trn PORTA v PORTC ca cc b iu khin cng nh tn hiu ALE dng cho vic phn knh a ch/d liu, bit SRE(bit 7) trong thanh ghi MCUCR c t thnh 1.

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Bng 4: Bn b nh d liu SRAM

2.2.7 Cc cng vo ra
Tt c cc b iu khin AVR u c mt lng ln cc cng vo/ra nm trong khong t 3 bit trn AT90S2323 n 48 bit trn Mega103. Tt c cc cng li ra ca cc b iu khin AVR c th chu dng in n 20 mA nn rt thch hp i vi vic iu khin trc tip cc LED v khng cn n mch b sung. Cc cng vo ra u c 3 a ch vo ra i km vi chng. Ba a ch vo/ra c cn n t cu hnh cho cc bit ring bit thnh li vo hoc li ra, a ch khc cn n xut ra d liu ti cc bit c t cu hnh thnh li ra, v a ch th 3 c cn n c d liu t cc chn c cu hnh thnh li vo.

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2.2.8 Truy nhp b nh v thc thi lnh

B x l AVR c iu khin bi ng h h thng, ng h ny c th bn ngoi hoc, nu c tn ti v c php, mt ng h RC bn trong c th c s dng. ng h h thng ny khng qua bt k b chia no v c s dng trc tip cho tt c cc thao tc truy nhp bn trong b x l. B x l c mt ng ng hai tng, v lnh tm np/gii m (fetch/ decode) c thc hin ng thi vi vic thc thi lnh. C mi ln lnh c tm np (fetch), nu y l mt lnh lin quan n ALU, n c th c tc thi bi khi ALU cho mt chu trnh n l. Mt khc, vic truy nhp b nh SRAM chim mt 2 chu k. Nguyn nhn l vic truy nhp b nh SRAM s dng mt thanh ghi con tr dng cho a ch b nh RAM. Thanh ghi con tr ny ch l mt trong cc thanh ghi con tr (cc cp thanh ghi X, Y , hoc Z) c trn chip. Chu trnh ng h th nht c cn n truy nhp tp thanh ghi v thao tc trn thanh ghi con tr. thi im kt thc ca chu k ng h th nht, khi ALU thc hin php tnh ny, v sau a ch ny (hoc c ra t vo thanh ghi ch).

2.2.9 Ngt trn AVR

Hnh 5: S ngt

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Interrupts, thng c gi l ngt, l mt tn hiu khn cp gi n b x l, yu cu b x l tm ngng tc khc cc hot ng hin ti nhy n mt ni khc thc hin mt nhim v khn cp no , nhim v ny gi l trnh phc v ngt isr (interrupt service routine ). Sau khi kt thc nhim v trong isr, b m chng trnh s c tr v gi tr trc b x l quay v thc hin tip cc nhim v cn dang d. Nh vy, ngt c mc u tin x l cao nht, ngt thng c dng x l cc s kin bt ng nhng khng tn qu nhiu thi gian. Cc tn hiu dn n ngt c th xut pht t cc thit b bn trong chip (ngt bo b m timer/counter trn, ngt bo qu trnh gi d liu bng RS232 kt thc) hay do cc tc nhn bn ngoi (ngt bo c 1 button c nhn, ngt bo c 1 gi d liu c nhn). Ngt l mt c cu iu khin dng lnh, c cu ny c thit k trn hu ht cc b iu khin. Trong qu trnh giao tip ca h thng b x l vi th gii bn ngoi, nhiu s vic xy ra theo cch khng ng b, chng hn ngi dng c th nhn mt cng tc thc hin mt cng vic no , trong khi mt byte d liu i n cng ni tip. iu ny gy kh khn cho hot ng ca b x l khi m n phi kim tra tt c cc thit b gim st s di chuyn ca d liu. Ngc li mi vic s tt hn nu cc thit b ny c th loan bo s n ni ca d liu. y l tt c nhng g m c ch ngt phi thc hin. Thit b ngoi vi s ngt vic thc thi ca chng trnh chnh, v b x l tm ngng vic thc thi chng trnh bnh thng thm tra ngun ngt v thc hin nhng thao tc p ng cn thit. Sau khi hon thnh nhng thao tc p ng cm thit vic thc thi chng trnh b ngt li tip tc. Chng trnh ngt ch n gin ging ht mt cng trnh con bnh thng ngoi tr mt c im l vic thc thi ca chng trnh ny khng b b x l chn trc l s xut hin mt thi im c th no. Th t cc s vic xut hin khi xy ra ngt: 1. Thit b ngoi vi ngt b x l. 2. Thc hin nt lnh hin ti. 3. a ch lnh tip theo c lu tr vo ngn xp.

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4. a ch ca chng trnh con phc v ngt c np vo b m chng trnh. 5. B x l thc thi chng trnh con phc v ngt. 6. Tr li chng trnh b ngt bng lnh RETI. 7. B x l np b m chng trnh vi gi tr c lu tr trn ngn xp v vic thc thi chng trnh bnh thng li tip tc. Bi v ngt c th xut hin bt c lc no nn trng thi b x l cn phi c lu tr sao cho vic thc thi chng trnh bnh thng c th tip tc ngay sau khi on chng trnh ISR c hon tt. Trng thi ca b x l c cha trong thanh ghi SREG. Thanh ghi ISR cn phi lu tr SREG trc khi thc thi bt k mt lnh no khc, v trc khi tr li vi vic iu khin chng trnh chnh cn phi khi phc li thanh ghi SREG. Yu cu ny c th c thc hin theo hai cch: hoc l SREG c sao chp sang mt thanh ghi khc k hiu l RI, thanhghi ny cn phi khng c phc v cho bt k mt mc ch no khc v trc khi ISR thc thi lnh RETI, RI c sao chp ngc tr li SREG. Mt cch khc lu tr SREG l lu n trn ngn xp(bng cch dng lnh PUSH SREG) v sau trc khi thc hin lnh RETI, gi tr SREG c sao chp ngc tr li t ngn xp(lnh POP SREG). Phng php ny ch c th p dng cho nhng b x l c ngn xp t chc bng phn mm. Cng c kh nng ngt mt ISR nu mt ngt khc xut hin v c ngt ton cc c t thnh 1 bn trong ISR dng cho ngt 1(bng cch s dng lnh SEI). Trong trng hp ny, ngt ISR1 b ngt v ISR khc, ISR2 thc thi. Vic thc thi ISR1 li tip tc sau khi ISR2 kt thc, v sau khi thc thi xong ISR1 chng trnh chnh li tip tc. Bnh thng sau khi mt ngt xut hin v ang oc phc v bi thanh ghi ISR tng ng, cc ngt ton cc b cm(tng ng vic thc hin lnh CLI), tuy nhin vn c kh nng cho php cc ngt trong khi mt ISR ang thc thi bng vic thc hin lnh SEI trong ISR.. Nu nh cc ngt khc xut hin trong khong thi gian khi mt ISR ang hot ng th n s c thc hin bng vic ngt on chng trnh ISR ban u.

19 The Hoanh

Tnh u tin ca ngt: oc quy nh bi cch gn cc vect ngt. Mt vect ngt a ch thp hn trong b nh chng trnh c mc u tin cao hn. Mc u tin ca ngt dng quyt nh xem ngt no c phc v trc nu nh c nhiu ngt ang ch x l cng mt thi im. Mt iu rt ng quan tm khi s dng cc ngt l b vi x l c th p ng ngt nhanh n mc no. Cu tr li ph thuc rt nhiu vo kin trc ca b vi x l. i vi cc b iu khin AVR, vic thc thi ngt p ng i vi tt c cc ngt AVR c cho php t nht l 4 chu k ng h. Bn chu k ng h sau khi c ngt c t, chng trnh vect a ch dng cho on chng trnh x l ngt hin ti c thc thi. Trong khong thi gian 4chu k my b m chng trnh(2 byte) c y ln ngn xp, v con tr ngn xp th gim i 2. Vct thng l mt lnh nhy tng i n hng trnh ngt, v thao tc nhy ny chim 2 chu k ng h. Nu nh mt ngt xut hin trong khi ang thc thi mt lnh chim hiu chu k, lnh ny c hon thnh trc khi ngt c phc v. Vic quay tr li t mt chng trnh x l ngt chim 4 chu k ng h. Trong bn chu k ng h ny, b m chng trnh (2 byte) c y tr li ngn xp, con tr ngn xp oc tng thm 2 v c I trong SREG c t. Khi vi iu khin AVR thot ra khi mt ngt n s lun tr v vi chng trnh chnh v chp hnh lnh k tip trc khi c ngt mi c x l.

2.2.10 Timer Counter

Timer/Counter l cc module c lp vi CPU. Chc nng chnh ca cc b Timer/Counter, nh tn gi ca chng, l nh th (to ra mt khong thi gian, m thi gian) v m s kin. Trn cc chip AVR, cc b Timer/Counter cn c thm chc nng to ra cc xung iu rng PWM (Pulse Width Modulation), mt s dng AVR, mt s Timer/Counter cn c dng nh cc b canh chnh thi gian (calibration) trong cc ng dng thi gian thc. Cc b Timer/Counter c chia theo rng thanh ghi cha gi tr nh thi hay gi tr m ca chng, c th trn chip Atmega8 c 2 b Timer 8 bit (Timer/Counter0 v Timer/Counter2) v 1 b 16 bit (Timer/Counter1). Ch hot ng

20 The Hoanh

v phng php iu khin ca tng Timer/Counter cng khng hon ton ging nhau, v d chip Atmega8: - Timer/Counter0: B nh thi (timer/counter0) l mt module nh thi/m 8 bit, c cc c im sau: B m mt knh Xa b nh thi khi trong mode so snh (t ng np)

PWM

To tn s B m s kin ngoi B chia tn 10 bit Ngun ngt trn b m v so snh S cu trc ca b nh thi:

Hnh 6: S cu trc b nh thi

AVR Atmega8 c tch hp b timer/counter. Ta bt u phn ny bng s khi sau:

21 The Hoanh

Hot ng ca b Timer/Couter

+ Mch m ln lm thanh ghi TCNTn tng 1 n v mi khi c xung clkTn, khi t gi tr ln nht (8bit=255), c TOVn c set (logic 1) v b m trn, gi tr b n TCNTn tr v 00 v tip tc m. + Xung clkTn c th c la chn t nhiu ngun khc nhau. Khi chn xung ni (system clock), Timer/Counter l mt Timer. Khi chn xung ngoi (thng qua chn Tn) Timer/Counter l Counter. Hot ng ny c th din t bng gin xung sau:

Hnh 7: Gii xung ca b Timer/Couter Cng ging nh b timer/counter trong cc vi iu khin khc, chng ta quan tm n 2 thanh ghi: Timer/Counter Control v Timer/Counter Value. Trong AVR, l thanh ghi TCCRn v TCNTn.

22 The Hoanh

Hnh 8: Thanh ghi TCCRn v TCNTn Clock Select Bit Description

TCNT0 - Timer/C TCNT0 v OCR0 l cc thanh ghi 8 bit. Cc tn hiu yu cu ngt u nm trong thanh ghi TIFR. Cc ngt c th c che bi thanh ghi TIMSK. B nh thi c th s dng xung clock ni thng qua b chia hoc xung clock ngoi trn chn T0. Khi chn xung clock iu khin vic b nh thi/b m s dng ngun xung no tng gi tr ca n. Ng ra ca khi chn xung clock c xem l xung clock ca b nh thi (clkT0). Thanh ghi OCR0 lun c so snh vi gi tr ca b nh thi/b m. Kt qu so snh c th c s dng to ra PWM hoc bin i tn s ng ra ti chn OC0.

23 The Hoanh

- Timer/Counter1: s khi v mt s c im

Hnh 9: S khi v mt s c im B nh thi (timer/counter1) l mt module nh thi/m 16 bit, c cc c im sau: True 16-bit Design (i.e., allows 16-bit PWM) 2 n v ng vo so snh c lp(Two Independent Output Compare Units) i thanh ghi so snh ng ra m(Double Buffered Output Compare Registers) 1 n v cht ng vo(One Input Capture Unit) B chng nhiu li vo(Input Capture Noise Canceler) Xa timer trong Compare Match (Clear Timer on Compare Match (Auto Reload)) chng nhiu sc ngang(Glitch-free, Phase Correct Pulse Width Modulator (PWM) Gi tr chu k PWM B pht tn s chung B m s kin ngoi

24 The Hoanh

4 ngun ngt c lp (TOV1, OCF1A, OCF1B, and ICF1) Mt s nh ngha

BOTTOM B m t ti BOTTOM khi co gi tr 0x0000 MAX B m t ti MAXimum khi khi t gi tr 0xFFFF (decimal 65535). TOP B m t ti TOP khi n bng vi gi tr ln nht ca chui m. Gi tr ny c th c gn bi cc gi tr c nh : 0x00FF, 0x01FF, or 0x03FF,hoc gi tr trong b nh ca cc thanh ghi OCR1A ,ICR1 . l b nh thi, m a nng 16 bit. B Timer/Counter ny c 5 ch hot ng chnh. Ngoi cc chc nng thng thng, Timer/Counter1 cn c dng to ra xung iu rng PWM dng cho cc mc ch iu khin. C th to 2 tn hiu PWM c lp trn cc chn OC1A (chn 15) v OC1B (chn 16) bng Timer/Counter1. Cc b Timer/Counter kiu ny c tch hp thm kh nhiu trong cc chip AVR sau ny, v d Atmega128 c 2 b, Atmega2561 c 4 b - Timer/Counter2: tuy l mt module 8 bit nh Timer/Counter0 nhng Timer/Counter2 c n 4 ch hot ng nh Timer/Counter1, ngoi ra n n cn c s dng nh mt module canh chnh thi gian cho cc ng dng thi gian thc (ch asynchronous).

2.2.11 Cc ch truy nhp a ch AVR:

- a ch thanh ghi n trc tip: ch ny a ch cc thanh ghi c ly trc tip t vng cc thanh ghi (t vng 0 n 31).

25 The Hoanh

V d:

COM Rd NEG Rd

- a ch hai thanh ghi trc tip: y l ch m trong mt lnh ALU truy nhp trc tip vo hai thanh ghi. Ch ny hon ton tng t nh ch trn. V d: ADD Rd, Rr - a ch trc tip cng vo ra: Trong a ch ton hng c cha trong 6 bit cu mt t lnh l a ch ca thanh ghi ngun hoc ch. V d: Out DDRB, R16 In - a ch trc tip d liu: R12, DDRB

- a ch ca d lit trong RAM c a trc tip vo lnh V d: RDS R12,0x0fff STS 0x0fff,R11 - a ch d liu gin tip cng vi dch chuyn: a ch ca ton hng ngun hoc ch c tr bi thanh ghi Y hoc Z cng thm 1 ch s no V d: LDD,Y + 10

- a ch gin tip d liu:

26 The Hoanh

y l cch m CPU nhp d liu trong RAM thong qua thanh ghi X,Y,Z. a ch ca d liu c lu trong thanh ghi ny. V d: ST LD X,R11 R13,Y

- a ch d liu gin tip cng vi tng hoc gim con tr: V d: LD R17, X+ LD -Y,R14 - a ch ca hng s trong b nh chng trnh: Cch ny ch s dng cho lnh LPM: ch cu hng s c lu trong thanh ghi Z. V d: LDIR 30,0x07 ; dia chi truc tiep du lieu 0x07 LDI LPM - a ch b nh chng trnh gin tip: a ch on m c tr bi thanh ghi Z s dung trong cc lnh IJMP, ICALL. V d: Label: LDI R29,high(label) LDI R28,low(label) R31,0xFF

ICALL

2.3 Vi iu khin Atmega 8:

2.3.1 S vi iu khin Atmega 8:

27 The Hoanh

Hnh 10: S chn ca Atmega 8.

28 The Hoanh

Hnh 11: S khi ca Atmega 8.

29 The Hoanh

ATMega 8 nggidngPDIP28chn.Trongc23chnI/O. (in put/ out put) chia thnh 3 Port: B,C,D; Mi mt chn c th mnhn nhiu vai tr. C th nh sau: VCC (chn 7): Chn in p. GND (chn 8): Chn tip t. Cc cng vo ra ca Atmega 8 gm c 3 PortB, PortC, PortD, PortB( PB7PB0) XTAL2/TOSC2 Port B, Bit 7 XTAL2: Chn 2 dao ng to clock. S dng chn clock thch anh,hoc dao ng thch anh tn s thp. Khi dng chn lm dao ng th khng th lm chn nhp xut c na. TOSC2: Chn 2 l dao dng Timer. Nu PB7 c dng lm clock pin, DDB7, PORTB7 and PINB7 s s hiu l mc 0 XTAL1/TOSC1 Port B, Bit 6 XTAL1: Chip clock Oscillator pin 1. TOSC1: Timer Oscillator pin 1. Nu PB6 dng lm chn clock, DDB6, PORTB6 and PINB6 s hiu l mc 0.

30 The Hoanh

Hnh 12: Chc nng PortB. SCK Port B, Bit 5 SCK: Master Clock output, Slave Clock input pin for SPI channel. Khi SPI c kch hot l Slave, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB5. MISO Port B, Bit 4 MISO: Master Data input, Slave Data output pin for SPI channel. Khi SPI c kch hot l Master, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB4. MOSI/OC2 Port B, Bit 3 MOSI: SPI Master Data output, Slave Data input for SPI channel. Khi SPI c kch hot l Slave, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB3. Khi SPI c kch hot l Master, d liu trc tip ca chn ny c iu khin bi DDB3. SS/OC1B Port B, Bit 2 SS: Slave Select ng vo. Khi SPI c kch hot l Slave, chn ny c cu hnh l 1 chn ng vo bt chp s iu chnh t DDB2. OC1A Port B, Bit 1

31 The Hoanh

OC1A, Output Compare Match output:Chn PB1 c th x l nh 1 ng ra bn ngoi Timer/Counter1 Compare Match A. ICP1 Port B, Bit 0 ICP1 chn gi(cht) ng vo : Chn PB0 c th tc ng lm 1 chn gi cho Timer/Counter1. PortC( PC6PC0) RESET Port C, Bit 6 RESET, Reset pin: Khi cu ch RSTDISBL lp trnh, chc nng ca chn ny l vo ra binh thng,v 1 phn s phi da vo Power-on Reset v Brown-out Reset nh l ngun reset ca n. Nu chn PC6 dng l chn reset , DDC6, PORTC6 v PINC6 s hiu l mc 0.

Hnh 13: Chc nng PortC.

SCL/ADC5 Port C, Bit 5 SCL, giao din ni tip hai dy Xung nhp: Khi bit TWEN trong TWCR set (one) bt giao din ni tip hai dy, pin PC5 b ngt t port v tr thnh chn Serial Clock I/O cho Two-wire Serial Interface. SDA/ADC4 Port C, Bit 4

32 The Hoanh

SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. ADC3 Port C, Bit 3 PC3 cng c th dng l ADC input Channel 3. Ch l ADC input channel 3 dng ngun xoay chiu. ADC2 Port C, Bit 2 PC2 cng c th dng l ADC input Channel 2. Ch l ADC input channel 2 dng ngun xoay chiu. ADC1 Port C, Bit 1 PC1 cng c th dng l ADC input Channel 1. Ch l ADC input channel 1 dng ngun xoay chiu. ADC0 Port C, Bit 0 PC0 cng c th dng l ADC input Channel 0. Ch l ADC input channel 0 dng ngun xoay chiu PortD (PD7-PD0)

Hnh 14: Chc nng Port D. AIN1 Port D, Bit 7 AIN1,b so snh tng t th ng ng vo. Cu hnh chn ca port l nhp vo vi ngt pull-up bn trong trnh nhiu t port s vi chc nng ca b so snh tng t.

33 The Hoanh

AIN0 Port D, Bit 6 AIN0,B so snh tng t ng vao tch cc. Cu hnh chn ca port l nhp vo vi ngt pull-up bn trong trnh nhiu t port s vi chc nng ca b so snh tng t. T1 Port D, Bit 5 T1, s lng m ngun Timer/Counter1. XCK/T0 Port D, Bit 4 XCK, USART xung nhp ngoi. T0, s lng m ngun Timer/Counter0. INT1 Port D, Bit 3 INT1, Ngt ngun bn ngoi 1: Chn PD3 c th lm chc nng nh 1 ngun ngt ngoi. INT0 Port D, Bit 2 INT0, Ngt ngun bn ngoi 0: Chn PD2 c th lm chc nng nh 1 ngun ngt ngoi. TXD Port D, Bit 1 TXD, Truyn ti d liu (chn d liu ra ca USART). Khi b truyn USART c kch hot ,chn ny c cu hnh nh l mt ng ra bt k gi tr ca DDD1. RXD Port D, Bit 0 RXD, Nhn d liu (chn d liu vo ca USART). Khi b nhn USART c kch hot, chn ny c cu hnh nh l mt ng vo bt k gi tr ca DDD0 M t thanh ghi ca port I/O The Port B Data Register PORTB

The Port B Data Direction Register DDRB

The Port B Input Pins Address PINB

34 The Hoanh

The Port C Data Register PORTC

The Port C Data Direction Register DDRC

The Port C Input Pins Address PINC

The Port D Data Register PORTD

The Port D Data Direction Register DDRD

The Port D Input Pins Address PIND

Tm li: 1. c d liu t ngoi th ta phi thc hin cc bc sau:

35 The Hoanh

a d liu ra thanh ghi iu khin DDRxn t cho PORTx (hoc bit n trong port) l u vo (xa thanh ghi DDRx hoc bit). Sau kch hot in tr pull-up bng cch set thanh ghi PORTx ( bit). Cui cng c d liu t a ch PINxn (trong x: l cng v n l bit). 2. a d liu t vi iu khin ra cc cng cng c cc bc hon ton tng t. Ban u ta cng phi nh ngha l cng ra bng cch set bit tng ng ca cng .v sau l ghi d liu ra bit tng ng ca thanh ghi PORTx.

2.4 Gii thiu v IC 74HC154

2.4.1 Gii thiu v IC 74HC154.
- IC 74HC154 l loi IC dng gii m, gii a hp vi cc tnh nng chnh Gii a hp c 16 ng ng ra. Gi m nh phn 4 bt u vo thnh 16 ng ng ra tng ng. Hai ng vo cho php kha hoc m rng chn ca IC 74HC154.

2.4.2 S chn ca IC 74HC154

36 The Hoanh

Hnh 15: S chn ca IC 74HC154.

Hnh 16: S bn trong IC 74HC154

Chc nng cc chn ca IC 74HC154. Chn 24, 12 (VCC, GND) dng cp ngun cho IC hot ng. Chn 18,19 (G1,G20 cc ng vo cho pht IC hot ng trong mt thi im ch c 1 IC hot ng, IC b cm hot ng th tt c cc ng ra u mc logic cao.. Chn 23,22,21,20 (A,B,C,D) Cc ng vo quy nh trn thi ng ra Chn 1-11, 13-15 (O0-O15) Cc ng ra ca IC.

37 The Hoanh

Ty thuc vo trng thi ca cc ng a ch m ta c ng ra tng ng, khi c hai ng vo G1, G2 mc logic thp th IC hot ng bnh thng, ti mt thi im ch c mt ng ra mc logic thp, tt c cc ng cn li u mc cao.

2.4.3 Nguyn tc hot ng ca IC 74HC154.

Hnh 17: Bng ch nng ca IC 74HC154. Da vo bng trng thi ta thy: Ch cn chn G1,G2 trng thi cm (khng cho php IC hot ng) th tt c ng ra ca IC 74HC154 u mc cao bt chp trng thi cc chn a ch (A,B,C,D), Chng hn nh khi chn G1 mc logic cao th tt c cc ng ra ca IC u mc logic cao bt chp trng thi ca cc chn cong li nh G2,A,B,C,D. V khi chn G2 mc cao th cng tng t nh th.

38 The Hoanh

Khi cc ng a ch vo t 00h-07H th mc logic thp duy nht ng ra s di chuyn t ng ra (00_07)

2.5 Ma trn led.

2.5.1 Cu trc v nguyn l cp ngun cho led ma trn.
Led ma trn bao gm cc led n c xp thnh hng v ct . Cc led n trong cng mt hng th c ni chung anot (catot) cn trong cng mt ct th c ni chung catot (anot). Do cc led c th sng ta phi cp ngun cho led nh sau : cp mc cao (thp) cho hng v mc thp (cao) cho ct.

Hnh 18: Led ma trn chung anot

Vi cch sp xp nh trn ti mt thi im ta khng th hin th mt k t (vi trn 2 hng 2 ct) trn ma trn. Do c th hin th mt k t trn led ma trn th ta phi li dng hin tng lu nh trn vng mc. Ta phi cho tng hng (ct) ca k t ln lt kin th trn led ma trn vi tn s cao. Trc tin ta phi xc nh mc logic cn cp cho tng hng (ct) ca led ma trn hin th k t ri lu cc gi tr logic ny

39 The Hoanh

li. Sau khi cn hin th k t th ta ln lt a cc gi tr ny ra cc chn cp ngun cho hng (ct) ng thi cp ngun cho ct (hng) tng ng vi n.

2.5.2 Nguyn tc to font ch hin th

c th hn ta xt v d hin th ch R trn led ma trn 8x8 theo cch qut ln lt tng ct ma trn. Do qut theo tng ct nn ta s phi xc nh mc logic cn cp cho tt c cc led trong tng ct. Gi thit cc led cng hng mc chung anot, cc led trong cng mt ct mc chung catot. Khi nu mun mt led no trong ct sng th ta phi cp in p mc cao vo hng tng ng. H H Hnh 19: To font ch cho k t H H H H H H H H H H H H H H H H

Nhn vo bng trn ta thy mun hin th ch R phi cp ngun cho cc led trong tng ct nh sau : Ct 5: L , H , H , L , L , L , H , L Ct 4: H , L , L , H , L , H , L , L Ct 3: H , L , L , H , H , L , L , L Ct 2: H , L , L , H , L , L , L , L Ct 1: H , H , H , H , H , H , H , L

40 The Hoanh

Cc led trong cc ct khc c cp in p mc thp . Cc gi tr ny cn c lu li trong b nh ca vi iu khin khi cn ta c th ly ra. Ta c th lu cc gi tr ny thnh tng byte trong b nh theo trt t t hng 1 ti hng 8 hay ngc li. V d ct 1 ta lu theo th t t hng mt ti 8 th lu gi tr 0F8H cn nu ngc li th l 7FH . Vic m ha font ph thuc vo cch cp ngun cho ma trn led. Nu ta cp ngun cho tng ct ca ma trn led sng ln lt th font ch phi lu cc gi tr logic m ha cch cp ngun cho tt c cc led trong ct . Gi s ta m ha font 6 ct 8 hng ( 5 ct m ha ch 1 ct to khong cch 2 ch k tip) nh nu trong nguyn tc iu khin led th mi k t cn 6 byte d liu lu.

2.5.3 iu khin hin th led ma trn

tin cho vic truy xut d liu ta c th khai bo 1 mng trong b nh Flash ca Atmega16 lu cc d liu ny. Khi a ch u ca d liu m ha 2 k t gn nhau th cch nhau cch nhau 6. V vy khi bit c v tr ca 1 k t trong font th ta c th xc nh a ch ca d liu m ha k t . Trn c s ta c th d dng xut d liu ca k t cn hin th ra . Sau khi xc nh c cc mc logic cn cp cho ma trn led th ta c th tin hnh iu khin qu trnh cp ngun cho led ma trn c c hnh nh nh mun. Vic cp ngun cho led ma trn ph thuc vo cch m ha d liu (theo tng hng hay theo tng ct ca ma trn). Nu d liu m ha l cc hng trong 1 ct (hng) th ti mt thi im ta ch cp ngun cho mt ct (hng . Qu trnh iu khin hin th led ma trn 8x8 theo tng ct (hng) bao gm cc bc sau : B1: Ly mu d liu : ly cc d liu v mc logic cn cp cho cc ct (hng) ca ma trn B2: Bt u vi ct i=1. B3: Cp ngun cho ct i

41 The Hoanh

B4: Xut d liu tng ng vi ct ( c ly mu t trc) cp ngun cho cc hng ca ma trn B5: i=i+1 ; quay li bc 2 nu i>8 ,nu khng th quay li bc 3

Hnh 20: Lu thut ton cp ngun cho ma trn led Nu ch iu khin 1 s lng led ma trn nh th ta c th dng trc tip cc chn ca vi iu khin iu khin vic cp ngun cho led ma trn. Nu ma trn ln hn th ta phi dng cc b ghi dch cp ngun cho led ma trn. hnh nh trn led ma trn hin th r rng khng b nhy ta cn phi iu khin tn s qut led ma trn. C th dng cc b nh thi ca vi iu khin iu khin thi im cp ngun cho led ma trn to tn s qut. Tm li iu khin led ma trn ta u tin ta cn phi xc nh c phng php cp ngun cho ma trn ( cp ngun theo tng ct hay tng hng ). Sau khi xc nh c phng php cp ngun ta cn phi xy dng font ch cho ph hp vi cch

42 The Hoanh

cp ngun. T y ta c th tin hnh iu khin vic cp ngun cho ma trn dng ch trn ma trn hin th nh mong mun.

CHNG 3: THIT K CHNG TRNH V M PHNG BNG PROTEUS

3.1 S khi v lu thut ton

43 The Hoanh

Khi x l

Khi gii m

Khi hin Th

Begin

Ngui Nui
Khai bo bin, mng k t

Hnh 21: S khi Chc nng, vai tr ca tng khi nh ngha

mng k t

Khi x l: c d liu c lp trnh sn cho vi iu khin, x l d liu v a ra bn ngoi thng qua cc chn trao i d liu.
nh ngha mng qut vi iu khin. Khi hin Th: Hin th thng tin nhn t ct

Khi gii m: Nhn d liu u vo t vi iu khin lm nhim v gii m a ra ngoi.

X l qut k t

Khi ngun: Cp ngun hot ng cho h thng.

a d liu vo Atmega8

y d liu ra LED ma trn

44 The Hoanh

Hnh 22: Lu thut ton:

45 The Hoanh

3.2 S ghp ni iu khin bin qung co.

Hnh 23: S ghp ni h thng

46 The Hoanh

Hnh 24: Khi hin thi.

3.3 Code chng trnh.

#include <mega8.h> #include <string.h> Unsigned char s[200]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,0}; const char AA[]={248,36,34,36,248,0}; const char BB[]={254,146,146,146,108,0}; const char CC[]={124,130,130,130,68,0}; const char DD[]={254,130,130,130,124,0}; const char EE[]={254,146,146,146,146,0}; const char FF[]={254,18,18,18,18,0}; const char GG[]={124,130,146,146,116,0}; const char HH[]={254,16,16,16,254,0}; const char II[]={130,130,254,130,130,0};

47 The Hoanh

const char JJ[]={66,130,254,2,2,0}; const char KK[]={254,16,40,68,130,0}; const char LL[]={254,128,128,128,128,0}; const char MM[]={254,8,16,8,254,0}; const char NN[]={254,8,16,32,254,0}; const char OO[]={124,130,130,130,124,0}; const char PP[]={254,18,18,18,12,0}; const char QQ[]={124,130,162,66,188,0}; const char RR[]={254,18,50,82,140,0}; const char SS[]={76,146,146,146,100,0}; const char TT[]={2,2,254,2,2,0}; const char UU[]={126,128,128,128,126,0}; const char VV[]={62,64,128,64,62,0}; const char WW[]={254,32,16,32,254,0}; const char XX[]={198,40,16,40,198,0}; const char YY[]={6,8,240,8,6,0}; const char ZZ[]={194,162,146,138,134,0};

const char S0[]={124,130,130,130,124,0}; const char S1[]={136,132,254,128,128,0}; const char S2[]={242,146,146,146,158,0}; const char S3[]={146,146,146,146,254,0}; const char S4[]={30,16,16,16,254,0};

48 The Hoanh

const char S5[]={158,146,146,146,242,0}; const char S6[]={254,146,146,146,242,0}; const char S7[]={2,2,2,2,254,0}; const char S8[]={254,146,146,146,254,0}; const char S9[]={158,146,146,146,254,0};

unsigned char i,j; unsigned int n=1,k=0; char str[]={0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, 0,0,0,248,36,34,36,248,0,248,36,34,36,248,0,248,36,34,36,248,0,248,36,34,36,248,0,248,3 6,34,36,248,0}; unsigned char chu[]=" book new";

void chip(unsigned char t) //void select chip (select colunm) { if (t==1) { PORTC.0=0; PORTC.1=1; PORTC.2=1; } else if (t==2)

49 The Hoanh

{ PORTC.0=1; PORTC.1=0; PORTC.2=1; } else { PORTC=0xFF; } } void scan(void) { if (n==32) n=0; if (n<16) { chip(0); PORTD=n; chip(1); } else if (n<32) { chip(0); PORTD=(n-16);

50 The Hoanh

chip(2); } } void hienthi(void) { scan(); //PORTB=str[n+k]; PORTB=s[n+k]; } interrupt [TIM0_OVF] void timer0_ovf_isr(void) { TCNT0=0xDC; PORTB=0x00; n++; hienthi(); // Place your code here } // Timer 1 overflow interrupt service routine interrupt [TIM1_OVF] void timer1_ovf_isr(void) { // Reinitialize Timer 1 value TCNT1H=0xF7; TCNT1L=0x03;

51 The Hoanh

for(i=0;i<strlen(chu)6;i++) { if (k<strlen(chu)*6) k++;

else k=0; } for (i=strlen(chu)6;i>0;i++) {if (k>0) k--; else k=strlen(chu)6; } // Place your code here } // Declare your global variables here

void main(void) { // Declare your local variables here // Input/Output Ports initialization // Port B initialization // Func7=Out Func6=Out Func5=Out Func4=Out Func3=Out Func2=Out Func1=Out Func0=Out // State7=0 State6=0 State5=0 State4=0 State3=0 State2=0 State1=0 State0=0 PORTB=0x00;

52 The Hoanh

DDRB=0xFF; // Port C initialization // Func6=In Func5=In Func4=In Func3=In Func2=Out Func1=Out Func0=Out // State6=T State5=T State4=T State3=T State2=1 State1=1 State0=1 PORTC=0x07; DDRC=0x07; // Port D initialization // Func7=Out Func6=Out Func5=Out Func4=Out Func3=Out Func2=Out Func1=Out Func0=Out // State7=0 State6=0 State5=0 State4=0 State3=0 State2=0 State1=0 State0=0 PORTD=0x00; DDRD=0xFF; // Timer/Counter 0 initialization // Clock source: System Clock // Clock value: 125.000 kHz TCCR0=0x03; TCNT0=0xDC; // Timer/Counter 1 initialization // Clock source: System Clock // Clock value: 7.813 kHz // Mode: Normal top=FFFFh // OC1A output: Discon. // OC1B output: Discon.

53 The Hoanh

// Noise Canceler: Off // Input Capture on Falling Edge // Timer 1 Overflow Interrupt: On // Input Capture Interrupt: Off // Compare A Match Interrupt: Off // Compare B Match Interrupt: Off TCCR1A=0x00; TCCR1B=0x05; TCNT1H=0xF7; TCNT1L=0x03; ICR1H=0x00; ICR1L=0x00; OCR1AH=0x00; OCR1AL=0x00; OCR1BH=0x00; OCR1BL=0x00;

// Timer/Counter 2 initialization // Clock source: System Clock // Clock value: Timer 2 Stopped // Mode: Normal top=FFh // OC2 output: Disconnected ASSR=0x00;

54 The Hoanh

TCCR2=0x00; TCNT2=0x00; OCR2=0x00; // External Interrupt(s) initialization // INT0: Off // INT1: Off MCUCR=0x00; // Timer(s)/Counter(s) Interrupt(s) initialization TIMSK=0x05; // Analog Comparator initialization // Analog Comparator: Off // Analog Comparator Input Capture by Timer/Counter 1: Off ACSR=0x80; SFIOR=0x00 // Global enable interrupts for (i=0;i<strlen(chu);i++) { switch (chu[i]) { case 'a': for (j=0;j<6;j++) s[i*6+j]=AA[j]; break; case 'b': for (j=0;j<6;j++) s[i*6+j]=BB[j]; break; case 'c': for (j=0;j<6;j++) s[i*6+j]=CC[j]; break; case 'd': for (j=0;j<6;j++) s[i*6+j]=DD[j]; break;

55 The Hoanh

case 'e': for (j=0;j<6;j++) s[i*6+j]=EE[j]; break; case 'f': for (j=0;j<6;j++) s[i*6+j]=FF[j]; break; case 'g': for (j=0;j<6;j++) s[i*6+j]=GG[j]; break; case 'h': for (j=0;j<6;j++) s[i*6+j]=HH[j]; break; case 'i': for (j=0;j<6;j++) s[i*6+j]=II[j]; break; case 'j': for (j=0;j<6;j++) s[i*6+j]=JJ[j]; break; case 'k': for (j=0;j<6;j++) s[i*6+j]=KK[j]; break; case 'l': for (j=0;j<6;j++) s[i*6+j]=LL[j]; break; case 'm': for (j=0;j<6;j++) s[i*6+j]=MM[j]; break; case 'n': for (j=0;j<6;j++) s[i*6+j]=NN[j]; break; case 'o': for (j=0;j<6;j++) s[i*6+j]=OO[j]; break; case 'p': for (j=0;j<6;j++) s[i*6+j]=PP[j]; break; case 'q': for (j=0;j<6;j++) s[i*6+j]=QQ[j]; break; case 'r': for (j=0;j<6;j++) s[i*6+j]=RR[j]; break; case 's': for (j=0;j<6;j++) s[i*6+j]=SS[j]; break; case 't': for (j=0;j<6;j++) s[i*6+j]=TT[j]; break; case 'u': for (j=0;j<6;j++) s[i*6+j]=UU[j]; break; case 'v': for (j=0;j<6;j++) s[i*6+j]=VV[j]; break; case 'w': for (j=0;j<6;j++) s[i*6+j]=WW[j]; break; case 'x': for (j=0;j<6;j++) s[i*6+j]=XX[j]; break; case 'y': for (j=0;j<6;j++) s[i*6+j]=YY[j]; break; case 'z': for (j=0;j<6;j++) s[i*6+j]=ZZ[j]; break;

56 The Hoanh

case '0': for (j=0;j<6;j++) s[i*6+j]=S0[j]; break; case '1': for (j=0;j<6;j++) s[i*6+j]=S1[j]; break; case '2': for (j=0;j<6;j++) s[i*6+j]=S2[j]; break; case '3': for (j=0;j<6;j++) s[i*6+j]=S3[j]; break; case '4': for (j=0;j<6;j++) s[i*6+j]=S4[j]; break; case '5': for (j=0;j<6;j++) s[i*6+j]=S5[j]; break; case '6': for (j=0;j<6;j++) s[i*6+j]=S6[j]; break; case '7': for (j=0;j<6;j++) s[i*6+j]=S7[j]; break; case '8': for (j=0;j<6;j++) s[i*6+j]=S8[j]; break; case '9': for (j=0;j<6;j++) s[i*6+j]=S9[j]; break; default: } } #asm("sei") break;

while (1) { // Place your code here

}; }

57 The Hoanh

KT LUN

58 The Hoanh

ti lm bin qung co tuy khng phi l mt ti mi v cng khng phi l mt ti ln nhng kh thng dng v tin ch trong cuc sng hng ngy ca chng ta. Thng qua ti ln ny em hc c rt nhiu kin thc b ch, v cng rt ra c rt nhiu kinh nghim c gi tr. Kt qu t c: Tm hiu c c bn vi iu khin AVR Atmega8, IC 74HC154, ma trn LED8x8. Thc hin m phng c bin qung co cho ca hang BOOK NEW p dng ngn ng lp trnh C vit chng trnh iu khin cho h thng. Hn ch: Bin qung co cn n gin, cha c p mt, cha c sn phm tht ng dng trong cuc sng. Hng phat trin: t ti ln ny c to cho em c nhng kin thc c bn v thit k bin qung co t c th p dng to ra c nhng bin qung co a dng phc tp hn. V cng l tin em c th to ra c nhng sn phm tht su ny ng dng nhiu hn trong thc t.

Ti liu tham kho

1. Nguyn Trung ng Bi Th Mai Hoa K thut vi x l, Nh xut bn khoa hc

v k thut. 2. Datasheet ca chip AVR Atmega8, IC 74HC154 3. Website: 1. www.hocavr.com 2. www.dientuvietnam.net 3.www.tailieu.vn 4. www.google.com 5.

59 The Hoanh

NHN XT CA GIO VIN HNG DN