METHODS FOR IMPROVING TRANSITION DELAY FAULT COVERAGE USING BROADSIDE TESTS

N. Devtaprasanna1, A. Gunda2, P. Krishnamurthy2, S.M. Reddy1 and I. Pomeranz3 1. Department of ECE, University of Iowa, Iowa City, IA 52242 2. LSI Logic Corp., Milpitas, CA 95035 3. School of ECE, Purdue University, West Lafayette, IN 47907
at faults can be easily adapted to generate tests for TDF faults. Testing for delay faults requires the application of two-pattern tests. There are two methods of testing for delay faults [4-5] in scan designs. In both methods an appropriate first pattern called the initialization pattern is scanned in. The two methods differ in how the second pattern called the launch pattern is obtained. In broadside testing, the launch pattern is derived from the circuit response to the first pattern. In skewed-load testing, the launch pattern is obtained by a one-bit shift of the first pattern. The test response to the second pattern is captured by applying a system clock pulse. The two methods also differ in the design and operation of the scan enable (SEN) signal as explained later. The restrictions in obtaining the launch pattern in both the above approaches result in delay fault coverage that is smaller than the stuck-at fault coverage. Enhanced scan [6] is a scan technique that can improve the delay fault coverage. Scan cells with three latches are used [6-10] that can store two independent values through scan shifting. Enhanced scan cells using three latches [6-10] require a fast control signal or a separate clock for scan. This requirement is similar to that of a fast SEN signal required in applying skewed-load tests. Methods have also been proposed to improve delay fault coverage whilst using broadside tests [12] and skewed-load tests [1, 11, 13]. In this paper, we propose replacing some of the flip-flops in scan designs that use the same clock for scan and functional operation (often known as multiplexer based scan design) with new types of flipflops. The proposed flip-flops do not require a fast signal switching between launch and test response capture. We also give procedures for selecting a subset of the flip-flops in the scan chains that are to be replaced by the proposed flip-flops in order to achieve higher delay fault coverage. The rest of the paper is organized as follows. Section 2 includes review of broadside and skewedload testing methods and brief descriptions of two previous works to which the proposed methods to

Abstract
Testing of delay faults require two pattern tests. Broadside and skewed-load testing are two approaches to test for delay faults in scan designs. The broadside approach is often preferred over the skewed-load approach in designs that also use the system clock for scan operations, since skewed-load requires a fast (atspeed) scan enable signal while broadside testing does not. In this paper, we propose new scan flip-flops to improve delay fault coverage for circuits with scan using broadside tests. The proposed flip-flops do not require a control signal to switch at-speed. This is a distinct advantage as the design effort required for timing closure of such control signals is significant. We also propose a circuit topology based flip-flop selection procedure that offers a scalable method for increasing the transition fault coverage. Experimental results on industrial circuits are included.

1. Introduction
With the advent of DSM technologies, verifying atspeed performance of fabricated integrated circuits is important to ensure a satisfactory shipped part quality level (SPQL). In the past, at-speed performance of circuits was typically verified using functional tests. However, developing functional tests for todays multimillion gate designs to achieve satisfactory defect coverage may not be feasible due to the high cost of development of such tests. The scan-based delay testing approach is commonly used as a low-cost alternative to functional testing [1]. In this approach, performance failures are modeled as delay faults and test patterns are generated by an automatic test pattern generator (ATPG). The transition delay fault [2] and path delay fault [3] models are typically used to generate tests for delaycausing defects. The transition delay fault (TDF) model is commonly used in the industry due to its simplicity. Existing ATPG algorithms that generate tests for stuck-

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improve TDF coverage are closely related. Section 3 includes the description and operation of the proposed flip-flops, called dual and transition-launch flip-flops. In Section 4 a procedure is given to select flip-flops to be replaced by the proposed dual or transition-launch flip-flops. Section 5 includes experimental results. Section 6 concludes the paper.

2. Preliminaries
In this section we briefly discuss the broadside and skewed-load test methods and review earlier works related to the methods proposed here. Even though the methods proposed can be used to increase the coverage of path and gate delay faults, for the sake of simplicity of discussion we consider transition delay faults (TDF) in this work.

one can wait a desired amount of time after the SEN signal transitions to the inactive state before the launch and capture clocks are applied. Thus, SEN does not have to be fast and its relative speed can be arbitrarily fixed. From our experience, the design effort involved in designing a fast SEN signal and the resulting impact on turnaround time is considered unacceptable for many designs. We believe that this concern is shared by others in the design and test community. Thus, the main motivation behind the proposed techniques for improving delay fault coverage is to avoid the requirement of a fast control signal that switches between launch and capture cycles while improving the fault coverage.

2.2 Related previous works

In this section we review earlier methods that are similar to the two modifications to scan cells we propose in this work and highlight the differences between them and the proposed designs. The method proposed in [1] uses additional flipflops called dummy flip-flops to reduce/eliminate the correlation between the initialization and launch patterns of a two-pattern skewed-load test. As an example of this approach consider the circuit shown in Figure 2(a). The slow-to-fall fault at the output of the AND gate cannot be tested with the given order of the flip-flops because the initialization condition requires FF2 = 1 under the first pattern whereas fault propagation requires FF3 = 0 under the second pattern. This conflict can be removed by inserting a dummy flip-flop in the scan path between FF2 and FF3 as shown in Figure 2(b). The dummy flip-flop receives the zero value required by FF3 under the launch pattern when the initialization pattern is scanned in. Inserting dummy flip-flops can guarantee the elimination of all the shift dependencies in a circuit. Insertion of dummy flip-flops will increase the scan chain length and hence the length of the test patterns. A fast SEN signal is still needed since the test is done under the skewed load method. It should be noted that the dummy flip-flops used are single port devices and not two-port standard scan cells. As will be seen in the next section, one of the methods we propose also adds flip-flops to the scan chain to enhance the fault coverage using broadside tests. However, the flip-flops we add are two port flip-flops that allow the use of broadside tests. As a consequence, there is no need for a fast SEN signal with the proposed augmented flipflops. The method proposed in [12] to improve delay fault coverage is applicable under the broadside test approach. This method augments some flip-flops in the scan chain to receive inputs from sources other than the standard ones. In this method [12] an additional

2.1 Scan-based delay tests

A test for a TDF requires the application of a pair of patterns (V1, V2) to the circuit. V1 is called the initialization pattern and V2 is called the launch pattern. The test application can be divided into three phases (a) Initialization phase (IP), when V1 is scanned in and applied to initialize the circuit to a desired state. (b) Launch phase (LP) during which V2 is applied to the circuit to activate the target fault and propagate the fault effects. (c) Capture phase (CP). A system clock is applied to capture the circuit response to the test.
IP CLK SEN LP CP

(a) IP CLK SEN LP CP

(b)

Figure 1: Timing waveforms for delay tests (a) skewed-load (b) broadside Waveforms illustrating the relative timing between the scan enable (SEN) signal and the system clock in multiplexer based designs using skewed-load and broadside tests are given in Figures 1(a) and 1(b), respectively. Under a skewed-load test, the SEN signal has to change after the last scan shift cycle that applies the launch vector V2, and settle prior to the next clock pulse. Thus, SEN must change fast and accommodate the system clock period. Under a broadside test the launch vector is obtained when SEN is inactive. Hence,

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multiplexer is inserted in the functional input path of the selected scan cells. An example of this method is
scan output From comb. circuit

0 1

D
FF3

CLK

From comb. circuit

0 1

D
FF2

&

in the circuit or an externally controlled signal. The ability to select D3 or Sj for the launch vector allows the ATPG to select an appropriate value for launching the desired transitions. Since DFT_EN is held constant during the launch and capture phases it does not have to be a fast signal. However, since an additional multiplexer is added in the functional path, the performance of the circuit may be degraded unless the multiplexers are added only at the inputs of the flipflops with sufficient slacks. It is important to note that the responses to tests are captured in all the modified scan cells as well as in the unmodified scan cells.
D3 Sj 0 1 0 1

CLK

D
FF3

From comb. circuit

0 1

D
FF1

DFT_EN SEN scan input

CLK

SEN CLOCK
scan input

CLK

Figure 3: Example illustrating the method of [12] (a)

scan output

From comb. circuit

0 1

D
FF3

To comb. circuit

CLK

D
Dummy Flip-flop

The second method we propose uses what are called transition launch (TL) flip-flops. This can be seen to be an adaptation of the flip-flop enhancements proposed in [11] with two differences. The first difference is that an additional multiplexer is not placed in the functional path but instead it is placed in what is normally the scan path of a scan cell. The second difference is that TL flip-flops either do not capture test responses or their contents in test responses are masked.

CLK
From comb. circuit

3. Design and operation of the proposed flip-flops

Q
To comb. circuit

0 1

D
FF2

SEN
From FF1

CLK

(b) Figure 2: (a) Example circuit (b) Dummy flipflop given in Figure 3. Note that an additional multiplexer and an additional control signal DFT_EN is added to the standard scan cell. The functional input of the scan cell FF3 can receive its value either from D3 (the normal functional input carrying the next state value) or from Sj depending on the value of the additional control input DFT_EN. The DFT_EN input is set appropriately after the initialization phase and held constant during the launch and capture phases. Sj can be any signal line

In this section we describe two augmented scan cells that can be used to increase the TDF coverage under the broadside test method. The first augmentation, described in Section 3.1, adds a two-port flip-flop in series with a scan cell. Under the second augmentation, described in Section 3.2, a multiplexer is added to a scan cell. Both methods also connect an additional control signal to the augmented flip-flops. In Section 3.3 we discuss the impact on the performance of the circuit under test and how this can be addressed when the proposed flip-flops are used in the scan chains.

3.1 Dual flip-flops

As described in the previous section, dummy flipflops can be inserted in the scan chain to improve the fault coverage of skewed-load tests. This method cannot be applied to broadside tests due to the requirement for the SEN signal to remain high during the launch cycle in order to shift the dummy flip-flop

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contents into the functional flip-flops. We overcome this requirement by providing a separate control signal, called the enhanced scan mode (ESM) signal, to the functional flip-flops. The enhanced flip-flop, called a dual flip-flop, is shown in Figure 4. Its operational modes are listed in Table 1. FF2 in Figure 4 corresponds to the standard two-port scan flip-flop whose output Q drives the combinational logic of the circuit under test. The multiplexer select line of FF2 is controlled by ESM instead of SEN as is normally done. In a dual flip-flop SEN controls the select input of FF1. SEN also controls the select inputs of scan cells that are not augmented. Note that the functional data input D carrying the next state value to the dual flip-flop is connected to both FF1 and FF2. In a scan chain, the output of FF2 of a dual flip-flop is connected to the scan-in (SIN) input of the next flip-flop in the chain.
D

0 1 0

SIN SEN CLK

1 FF2

FF1

ESM

Figure 4: Dual flip-flop Table 1: Dual flip-flop operation SEN 0 0 1 1 ESM 0 1 1 0 Operation of Flip-flop Functional mode/Standard broadside test mode Enhanced broadside test mode Scan shift mode Not allowed

with SEN = 0 and ESM = 1 during the launch and capture cycles. In this mode, the non-augmented scan cells operate as in standard broadside tests since SEN is connected to them. The dual flip-flops operate as follows. During the launch cycle the content of FF1 is shifted into FF2 and during the capture cycle the test response is captured in FF1. This implies that the state latched in FF1 at the end of the initialization phase is used as the present-state of FF2 in the launch cycle. Thus, when dual flip-flops are used in a scan chain there are two modes of broadside testing. One uses SEN = ESM = 0 and the other uses SEN = 0 and ESM = 1. The broadside tests in the second mode are the ones that achieve additional delay fault coverage. It is important to note that both the broadside test modes use SEN = 0 and that both SEN and ESM are constant during the launch and capture cycles just as in standard broadside tests. Thus, neither SEN nor ESM needs to be designed to be fast. In practice one can mix the two modes of broadside tests using dual flip-flops to achieve higher fault coverage and to potentially reduce test pattern counts. It is important to note that if all the flip-flops in the scan chain are replaced with dual flipflops we can apply arbitrary pairs of tests just as in the earlier proposed enhanced scan designs [6-9]. The difference however is that by using two flip-flops in a dual scan cell we avoid the need for a fast control signal or an extra clock needed for the three latch enhanced scan designs. However a disadvantage is that the scan chain length will be doubled. The global ESM signal that is connected to all the dual flip-flops in the circuit can be derived either from a primary input or through a programmable register inserted in the JTAG controller.

3.2 Transition-launch flip-flops

In this section we propose a different method to augment some of the scan cells in order to achieve higher TDF coverage using broadside tests. A scan cell with the proposed augmentation called a TL (transition launch) flip-flop is shown in Figure 5. A TL flip-flop is obtained by adding a multiplexer with a new input TI and a control input called TEN (transition enable) to a standard scan cell. Input TI is connected to some signal existing in the circuit or to an externally controlled signal. The modes of operation of a TL flip-flop are shown in Table 2. The function of TEN is similar to that of the ESM signal of the dual flip-flop given in the last section. The TL flip-flops also have two broadside test modes. In the first mode with SEN = TEN = 0 all the flip-flops in the scan chain operate as in the standard broadside test. In the second broadside test mode, called the enhanced broadside test mode, SEN = 0 and TEN = 1 during the launch and capture cycles. In this mode the scan cells that are not augmented operate

When SEN = ESM = 0 both FF1 and FF2 of a dual flip-flop will latch the value on the D input and hence one can apply the broadside tests normally used for standard scan designs. In this case FF1 does not have any role in testing. When SEN = ESM = 1 all the flip-flops are in scan mode and hence the initialization vector of a twopattern test can be scanned in while the circuit response to the previous test is shifted out. Since the dual flipflops have two flip-flops in series the effective scan chain length is increased as is the case when dummy flip-flops are used in the skewed load test approach [1]. This allows us to scan in extra values that can be used to improve the fault coverage as discussed next. An additional mode of operation for broadside tests, called enhanced broadside test mode, is obtained

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in the usual broadside test mode whereas a TL flip-flop operates in the following manner. In the launch and capture cycles the values on input TI are latched. It can be seen that a TL flip-flop operation is similar to that of the flip-flops augmented as proposed in [12] and illustrated in Figure 3 with one important difference. The connection of the functional input D from the combinational logic of the circuit under test is not made to go through two multiplexers as in Figure 3. The behavior of a TL flip-flop depends on the signal driving the TI input. The source affects the second patterns obtained as part of the two pattern TDF tests applied to the circuit, hence the importance of considering different sources. In this work we experimented with three different sources for input TI. These are described below.
D TI SIN SEN TEN CLK

response captured by a TL flip-flop may falsely indicate the presence of a TDF. This limitation can be overcome by masking the test response captured by the TL flip-flops or by replacing only the flip-flops with sufficient slack with TL flip-flops. In our experiments we only considered masking the test responses.
D
SIN SEN TEN
0 1 0 1

D
SIN SEN TEN
0 1

0 1

(a) D
SIN SEN TEN
0 1 0 1

(b) D
SIN TEN

0 1

0 0 1 1

(c)

(d)

Figure 6: TL flip-flop with (a) TI = Q (b) TI = D (c) TI = SIN (d) independent scan enable TEN In the third configuration of the TL flip-flop, the TI input is connected to the scan chain input signal SIN as shown in Figure 6(c). When this TL flip-flop is operated in the enhanced broadside test mode, the launch and capture cycle values are obtained from the output of the previous flip-flop in the scan chain. It can be seen that the multiplexer connected to the SEN signal is redundant and can be removed. Thus in this case, the TL flip-flop becomes the same as a standard scan cell with independent scan enable TEN as shown in Figure 6(d). The enhanced broadside test mode behavior of this flip-flop is similar to skewed-load test operation during the launch cycle. During the capture cycle since TEN = 1, an unknown value present at the SIN input is captured as the scan path connections are not designed for operating at functional speed. For this reason the test response in these TL flip-flops should be masked. From the discussion above it is seen that test responses are either not captured by the TL flip-flops or they may capture unknown values due to unknown circuit delays affecting the captured values. In either case the contents of the TL flip-flops in the scanned out test responses should be masked which results in reduced observability. For this reason in order to achieve as high fault coverage as possible when a given number of scan cells are changed to TL flip-flops one can partition the TL flip-flops into two or more subsets and connect an independent TEN signal to each subset. This will allow us to activate the enhanced broadside test mode only on a subset of flip-flops with their TEN

Figure 5: Transition-launch flip-flop Table 2: Transition-launch flip-flop operation SEN 0 0 1 1 TEN 0 1 1 0 Operation of Flip-flop Functional mode/Standard broadside test mode Enhanced broadside test mode Scan shift mode Not allowed

In the first configuration the TI input of a TL flipflop is driven by the complement of the present state signal Q of the corresponding flip-flop as shown in Figure 6(a). When a TL flip-flop is configured in this manner, in the enhanced broadside test mode the TL flip-flop outputs are inverted during the launch and capture cycles. Also, the TL flip-flop does not capture any test response in the enhanced broadside test as the path connecting the functional input D is disabled. In the second configuration of a TL flip-flop, the TI input is connected to the complement of the functional input D as shown in Figure 6(b). In the enhanced broadside test mode, the value latched by the TL flip-flop is the complement of the value latched in conventional broadside test during the launch and capture cycles. Since the circuit response is captured through a path containing an additional inverter and multiplexer than the functional path, any faulty test

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signal activated while the remaining flip-flops operate in the standard broadside mode. This is illustrated by an example below using TL flip-flops whose TI inputs are driven by Q of the corresponding flip-flop. Example: Consider the part of a sequential circuit shown in Figure 7(a). Using this circuit we will show how TL flip-flops can be employed to test additional delay faults. FF1, FF2, FF4 and FF6 are standard scan flip-flops and FF3 and FF5 are TL flip-flops. The scan enable, scan path and clock connections are not shown for the sake of simplicity.
TEN
D SIN

AND2. However, if enhanced broadside test mode is used with TEN = 1, then FF5 = 0 can be satisfied during the launch cycle by setting it to 1 in the initialization phase. Thus, the fault becomes testable. Next consider the slow-to-fall fault at the output of AND1. In order to test for this fault, the fault effect needs to be propagated through OR2 and captured by FF5. However, the initialization condition FF1 = FF2 = 1 forces FF3 = 1 during the launch cycle, thus blocking the fault effect. If the enhanced broadside test mode is used with TEN = 1, then FF3 = 0 during the launch

OR1
0

1 SEN

+
FF1
Q3' 0 1 SEN

D SIN

OR2
0 1

+
FF3
Q5' 0 1 SEN

D SIN

0 1

CLK

CLK

FF5
CLK D SIN

D SIN

&
AND1 FF2
D SIN 0

1 SEN CLK

&
NAND1 FF4

&
AND2

1 SEN CLK

1 SEN

FF6
CLK

(a)
TEN1
D SIN

TEN2 OR2

OR1
0

1 SEN

+
Q3'

D 0 1 SEN SIN

0 1

+
Q5'

D 0 1 SEN SIN

0 1

FF1
CLK

FF3
CLK

FF5
CLK D SIN

D SIN

&
AND1 FF2
D SIN 0

1 SEN CLK

&
NAND1 FF4

&
AND2

1 SEN CLK

1 SEN

FF6
CLK

(b) Figure 7: Example circuit using TL flip-flops (a) single TEN signal (b) two TEN signals Assume that the scan chain order is as indicated by the indices of the flip-flops. Also assume that any desired next-state value can be obtained for FF1, FF2 and FF4 using normal functional operation. Using standard broadside test (TEN = 0), the slow-to-rise fault at the output of NAND1 is untestable. The reason is that the fault initialization condition, FF3 = FF4 = 1, implies that FF5 = 1 during the launch cycle and therefore the fault propagation path is blocked at cycle can be obtained by setting FF3 = 1 in the initialization phase. However, the observation point, FF5, is also a TL flip-flop and it cannot capture its D input when TEN = 1. If FF3 and FF5 are controlled by independent TEN signals as shown in Figure 7(b) then the fault can be tested by setting TEN1 = 1 and TEN2 = 0 during the enhanced broadside test. It should be noted that when two or more TEN signals are used one can have several broadside test

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modes. For example in the case of two TEN signals shown in Figure 7(b) we can have four such test modes obtained by setting the TEN lines to four different possible combinations of values during the launch and capture cycles. When both TEN1 = 0 and TEN2 = 0 we get the normal broadside test mode; the enhanced broadside test modes are obtained for other combinations of TEN signal values.

3.3 Discussion
In at-speed test for transition delay faults using the proposed flip-flops the following points are important to note. When a dual flip-flop replaces a standard scan cell the functional input D drives the inputs of two multiplexers instead of one. Thus, an additional capacitive load is placed on the gate generating the functional signal D. In order to eliminate the potential effect on system performance and the ability to test the circuit at-speed, one can restrict the candidate scan cells that can be replaced with dual flip-flops. Another possibility is to design dual flip-flops such that the data input D sees the same capacitive load as when driving a standard scan cell. Similarly when a standard scan cell is replaced with a TL flip-flop system performance may be effected depending on the signal driving the TI input. For the TL flip-flop shown in Figure 6(a) the functional output Q drives the extra multiplexer in addition to the functional logic to which it is connected. In Figure 6(b) the functional input D drives the input of an additional inverter. In both cases one can avoid the effect on system performance by restricting the scan cells that can be replaced by TL flip-flops or by designing the TL flip-flops appropriately.

We found from our experiments that most of the faults in FD are detected when only the flip-flops in the set S are replaced by the proposed dual flip-flops. The reason for some faults not being detected is that we do not include in S flip-flops that affect the fault propagation paths. In this work we did not implement methods to address detection of these faults. From S, we obtain a pruned and ordered list of flip-flops S S using a two-phase greedy procedure. We give a pseudo-code of the greedy procedure for selecting flip-flops to be enhanced in Figure 8. Let S be ordered randomly and si denote the ith flip-flop in the ordered set S. Let N be the number of flip-flops in S. Let A = FD.
Procedure Select_Flip-flops(S, FD) Phase I: 1. For i = 1 to N 2. If si affects some fault f A, delete from A every fault such that si affects f 3. Else delete si from S 4. Endfor /* At the end of Phase I we have reduced the size of S */ Phase II: 1. Let S = 2. For every s S, compute rank(s) 3. While S , do 4. Pick the flip-flop smax with the highest rank in S (in case of a tie pick one randomly) 5. Add smax to S 6. For every f FD if smax affects f then delete f from FD 7. Delete smax from S 8. Compute the ranks of the flip-flops in S using the reduced set FD 9. Remove any flip-flops from S of rank 0 10. Endwhile

4. Flip-flop selection procedure

We use a topology based heuristic procedure to select flip-flops that will be replaced with the dual or TL flip-flops. Let FD denote the set of transition delay faults that can be detected with enhanced scan, which allows arbitrary two-pattern tests. Let FDb denote the set of faults that are detected using standard broadside tests. Then FD = (FD FDb) represents the set of faults that should be targeted for detection by broadside tests using the augmented flip-flops proposed in this work. Definition 1: Let fi be a delay fault. Then a scan flipflop sk is said to affect the fault fi, if sk is in the input cone of the circuit line corresponding to fi. Definition 2: The rank of a flip-flop s, rank(s), is defined as the number of faults in FD that s affects. Let S be the set of scan flip-flops that are in the input cone of all faults in the set FD, i.e., S = {s | s affects f for some f FD}

Figure 8: Procedure for flip-flop selection The above procedure is illustrated using an example. Example: Let FD = {f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11} be the set of target faults. Let S = {s1, s2, s3, s4, s5, s6, s7} be the set of flip-flops that affect the faults in FD. Figure 9(a) shows the faults from FD that are affected by each flip-flop in S. Let the flip-flops in S be ordered in increasing order of their numerical indices. During Phase I of the proposed procedure, beginning with s1, each flip-flop is checked if it affects a fault in FD that is not already affected by previous flip-flops. It can be seen that the faults affected by s4: f1, f4, f8, are affected by flip-flops s1 and s3 which were considered earlier. Thus s4 is dropped from the set S. Similarly s7 is also dropped because fault f10 is affected by s5. Thus S = {s1, s2, s3, s5, s6} at the beginning of Phase II. Figure 9(b) shows the affected faults and the rank of each flip-flop at the start of Phase II. In the first iteration, s3 is selected,

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removed from S and added to S. The faults {f1, f2, f5, f7, f8, f9} are removed from the set FD. The ranks of
FF s1 s2 s3 s4 s5 s6 s7 affected faults FF f1, f4, f5, f6 f3, f6 f1, f2, f5, f7, f8, f9 f1, f4, f8 f2, f10 f3, f5, f6, f11 f10 s1 s2 s3 s5 s6 affected faults f1, f4, f5, f6 f3, f6 f1, f2, f5, f7 ,f8 ,f9 f2, f10 f3, f5, f6, f11 rank(s) 4 2 6 2 4

(b) (a)

FF s1 s2 s5 s6

affected faults f4, f6 f3, f6 f10 f3, f6, f11

rank(s) 2 2 1 3 FF s1 s5 affected faults f4 f10 rank(s) 1 1

(d)

(c) Figure 9: Example of flip-flop selection the remaining flip-flops in S is computed based on the new FD = {f3, f4, f6, f10, f11} as shown in Figure 9(c). s6 is selected in the next iteration and added to the set S. The new FD = {f4, f10} and S = {s1, s2, s5} are obtained by removing the faults affected by s6 from FD as well as removing s6 from S. Since s2 does not affect any faults in FD, it is removed from S. The new ranks of the remaining flip-flops s1 and s5 are shown in Figure 9(d). Since both have the same rank, one of them is selected. The remaining flip-flop is selected in the last iteration, resulting in S = {s3, s6, s1, s5}.

5. Experimental results
We applied the proposed enhancements to several industrial designs. In all the experiments, deterministic broadside ATPG is performed with a commercial ATPG under the constraints that primary inputs do not change during launch and capture cycles and the primary outputs are not observed. In Table 3 we give the experimental results on fault coverage improvement obtained when a selected subset of scan cells are replaced by dual flip-flop, described in Section 3.1. The name of the circuit and the number of scan cells in the circuit are given in columns 1 and 2, respectively. The fault coverage using the standard

broadside test mode is given in column 3. The fault coverage achieved when all the scan flip-flops are replaced with dual flip-flops is shown in the next column. This is the maximum achievable delay fault coverage for the circuit since all arbitrary pairs of state vectors can be applied. In the next columns we report improved fault coverages when only a subset of the scan cells are augmented using dual flip-flops. In the first set of columns under the heading S, all the flipflops in S defined earlier are augmented. The number of flip-flops augmented (i.e., the number of flip-flops in S) as a percentage of the number of scan cells, and the broadside TDF coverage obtained as a result of augmenting the flip-flops, are given in columns 5 and 6, respectively. Similar results are given in the next two columns under heading S when all the flip-flops in S are augmented. Next in columns with heading S15% and S10% we give the fault coverage when only 15% and 10% of the total number of scan cells are augmented. In these cases the flip-flops to be augmented are selected from the top of the list S considering it as ordered in the way the flip-flops are entered into S in Phase II of the flip-flop selection procedure given in Figure 8. In Tables 4, 5 and 6 we give the results for Ckt1, Ckt2 and Ckt3 respectively for the cases when the selected scan cells are replaced by TL flip-flops described in Section 3.2. Three sets of experiments are performed for each circuit corresponding to the three sources for the TI inputs of the TL flip-flops shown in Figure 6. In each of these three experiments, 10% of the scan cells selected from the top of the list S are replaced with TL flip-flops. The set of TL flip-flops is further partitioned so that each partition is driven by an independent TEN signal. The partitions are obtained randomly and are of essentially equal sizes. The number of partitions is given in the first column of the tables. In the second and the third columns we show the broadside TDF coverage and the improved TDF coverage when dual flip-flops are used instead of TL flip-flops. In the fourth column we show the TDF coverage when the TI input of TL flip-flops is connected to the complement of the functional output Q of the flip-flop. The fifth and the sixth columns show the TDF coverage when the TI inputs are connected to the complement of the functional input D and the scan chain input SIN, respectively. From these results it can be seen that most of the detectable transition delay faults are detected using broadside tests after replacing a small percentage of scan cells with the proposed flip-flops. For example, for Ckt1 using 100% enhanced scan improves the TDF coverage from 85.25% to 90.91%. This is the maximum achievable TDF coverage. Replacing only 10% of the scan cells by dual flip-flops leads to a TDF coverage of 89.50% using broadside tests. Instead, if 10% of the scan cells are replaced with TL flip-flops

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and the number of partitions is 16, the TDF fault coverage using broadside tests will be 89.15%.

6. Conclusions
The high cost of designing a fast signal to control flip-flops is an obstacle in practice for using the skewed-load test approach as well as enhanced scan methods proposed earlier. These methods provide higher delay fault coverage than the broadside test approach, which does not require fast signals. In this paper, we proposed two novel techniques for improving the delay fault coverage of broadside tests. Both techniques do not require control signals to operate atspeed during test. In the first method, a standard scan cell is augmented by adding a two-port flip-flop to allow an arbitrary pair of values to be applied to the combinational logic of the circuit during test. The second technique modifies the scan path by inserting an additional multiplexer to allow the launch pattern value to be obtained from one of two sources. The effectiveness of these techniques was demonstrated by experimental results on several industrial circuits.

[11] W. Mao and M. D. Ciletti, Reducing Correlation to Improve Coverage of Delay Faults in Scan-Path Design, IEEE TCAD, 1994, pp. 638-646 [12] I. Pomeranz and S. M. Reddy, "On Achieving Complete Coverage of Delay Faults in Full Scan Circuits using Locally Available Lines", Proc. ITC, 1999, pp. 923-931 [13] S. Wang, X. Liu, and S. T. Chakradhar, Hybrid Delay Scan: A Low Hardware Overhead Scanbased Delay Test Technique for High Fault Coverage and Compact Test Sets, Proc. DATE, 2004, pp. 1296-1301

References
[1] J. Savir and S. Patil, Scan-Based Transition Test, IEEE TCAD, 1993, pp. 1232-1241 [2] J. A. Waicukauski, E. Lindloom, B. K. Rosen and V. S. Iyengar, Transition Fault Simulation, IEEE Design and Test of Computers, 1987, pp. 32-38 [3] G. L. Smith, Model for Delay Faults Based Upon Paths, Proc. ITC, 1985, pp. 342-349 [4] J. Savir and S. Patil, Skewed-Load Transition Test: Part II, Coverage, Proc. ITC, 1992, pp. 714-722 [5] J. Savir and S. Patil, On Broad-Side Delay Test, Proc. VTS, 1994, pp. 284-290 [6] S. Dasgupta, R. G. Walthers, T. W. Williams and E. B. Eichelberger, An Enhancement to LSSD and Some Applications of LSSD in Reliability, Availability and Serviceability, Proc. 11th FaultTolerant Computing Symp., 1981, pp. 880-885 [7] K. T. Cheng, S. Devadas, and K. Keutzer, A Partial Enhanced-Scan Approach to Robust DelayFault Test Generation for Sequential Circuits, Proc. ITC, 1991, pp. 403-410 [8] B. I. Dervisoglu and G. E. Stong, Design for Testability: Using Scanpath Techniques for PathDelay Test and Measurement, Proc. ITC, 1991, pp. 365-374 [9] C. Thomas Glover and M. Ray Mercer, A Method of Delay Fault Test Generation, Proc. DAC, 1988, pp. 90-95 [10] J. P. Hurst and N. Kanopoulos, Flip-Flop Sharing in Standard Scan Path to Enhance Delay Fault Testing of Sequential Circuits, Proc. of 4th Asian Test Symposium, 1995, pp. 346-352

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Table 3: Results using dual flip-flops ckt. name Ckt1 Ckt2 Ckt3 # of scan FFs 27.5k 73k 210k Broadside TDF cov. 85.25 86.49 88.35 Enhanced scan TDF cov. 90.91 90.73 91.94 S % of TDF dual FFs cov. 35.90 90.73 37.40 90.38 46.50 91.75 S % of dual FFs 26.90 18.05 23.50 TDF cov. 90.55 89.79 91.57 S15% 89.95 89.61 90.37 S10% 89.50 89.12 90.37

Table 4: Results using TL flip-flops for Ckt1 No. of partitions 2 4 8 16 Broadside TDF cov. 85.25 85.25 85.25 85.25 TDF cov. with 10% dual FFs 89.50 89.50 89.50 89.50 TDF cov. with 10% TL FFs TI = Q TI = D TI = SIN 88.49 88.75 88.33 88.71 88.92 88.61 88.90 89.10 88.72 89.07 89.15 88.78

Table 5: Results using TL flip-flops for Ckt2 No. of partitions 2 4 8 16 Broadside TDF cov. 86.49 86.49 86.49 86.49 TDF cov. with 10% dual FFs 89.12 89.12 89.12 89.12 TDF cov. with 10% TL FFs TI = Q TI = D TI = SIN 88.35 88.31 88.54 88.51 88.45 88.70 88.66 88.58 88.82 88.72 88.61 88.85

Table 6: Results using TL flip-flops for Ckt3 No. of partitions 2 4 8 16 Broadside TDF cov. 88.35 88.35 88.35 88.35 TDF cov. with 10% dual FFs 90.87 90.87 90.87 90.87 TDF cov. with 10% TL FFs TI = Q TI = D TI = SIN 90.12 90.07 89.93 90.29 90.35 90.08 90.45 90.52 90.16 90.53 90.55 90.22

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