Circuit design with FinFET processes

Andrew Marshall July 2006

Acknowledgements
Mark Campise (3), C. Rinn Cleavelin (1), Harald Gossner (2), Mak Kulkarni (1), Michael Gostkowski (3), Juergen Holz (2), Gerhard Knoblinger (2), Christian Pacha (2), Christian Russ (2), Klaus Schruefer (2), Thomas Schulz (2,3), Klaus VonArnim (2), Bruce Wilks (3), Wade Xiong (1,3), Paul Patruno (4) (1) Texas Instruments Inc., Dallas, TX, USA (2) Infineon Technologies AG, Balanstrasse 73, D-81541 Munich, Germany (3) ATDF Advanced Technology Development Facility,International Sematech,Austin,TX,USA (4) SOITEC S.A., Parc Technologique des Fontaines 38190 Bernin, France

Presentation Overview
Introduction Bulk vs FinFET Active components Passive components

Circuit Techniques Digital Circuits Stacked Gates Ring Oscillators

DRAIN DRAIN

N+
500nm

Analog design using FinFET Current Mirror Operational Amplifier

Wgeo

Wgeo

POLY
500nm pitch 200 nm

Lg Lg

POLY
GATE
MDR Wfin 50nm SCGS

LgLg

N+
SOURCE

SOURCE

GATE

FinFET Gate Width

Sidewalls become active channel width/length vs. planar surface for bulk. State of the art fin W is 20-60nm, fin/gate height 50-100nm, gate length ~30nm larger gate width / unit area With Fin height of 50nm, Fin width 20nm, pitch 80nm, 300nm of gate width can be squeezed into 200nm silicon width [1] Gate lengths of <20nm have been generated. Issues S/D resistance / channel modulation Multiple fins permit larger widths, but gate width is quantized by fins gate width
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Passive Components - Major passives: Rs Cs, diodes and Ls

Resistors in SOI/FinFET - two forms Polysilicon - constructed same way on bulk and FinFET but lower substrate cap SOI Well resistors are different to their bulk counterparts.
In bulk n-type doping into p-type substrate, creates V dependent R/C SOI mesa resistor has no parasitic diode to ground, low capacitance to ground, and R/C variation with respect to voltage is low

Capacitors Well caps not available in FinFET Gate caps usually have higher series resistance in SOI due to thinner silicon Inferior resistance but lower parasitic
capacitance to ground Minimized with multiple-finger layout

The metal capacitor is commonly used, formed with multiple interdigitated layers Interdigitated for maximum
capacitance Alike in bulk and SOI, but reduced parasitics in SOI
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Inductors Often constructed in the top level of metal Since SOI is used for RF circuitry influence of finFET on integrated inductors is important The Q-factor of inductors improved on finFET (esp. high res substrates) Inductors and transformers are constructed as a spiral using one or more levels of metal

Diodes Conventional bulk well diodes are not readily available in FinFET The Lubistor is a diode based on a MOS device [3]

Monolithic inductor layout: Red trace represents one or more metal levels, center tap tunnels under the inductor [2]
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Ring Oscillator Performance [4]

Ring oscillators have long been used as a guide to process performance Fastest ring oscillator is a minimally loaded fan-out of 1 inverter (even these need to take account of minimum interconnect R/C) More realistic circuit operation indicator are larger fan-out NAND ROs Interconnect loaded ROs good for monitoring capacitive & resistive effects

FinFET Ring Oscillator Circuits Performance

Approx 30 ROs on test chip with: gate lengths 90-120nm fin widths from 50 to 80nm fin height ~ 80nm fin numbers: 2-12 (NMOS) 2-18 (PMOS) Invertor, Nand, Nor
SOI ring oscillators
2.5E+06 FIN INV FO1 2.0E+06

INV1

NAND2

frequency

1.5E+06

FIN INV FO3

Inv/Nand freq vs supply

-Operate from <0.6v to >1.6v

1.0E+06 FIN NA FO1 5.0E+05

0.0E+00

FIN NA FO3

0.4

0.6

0.8

1.2

1.4

1.6

1.8

voltage

Gate energy 1.0E-12

Energy/transition

IV FO1 IN FO3 1.0E-13 NA FO1 NA FO3 1.0E-14 0.6 0.8 1 1.2 1.4 1.6 voltage

Energy per transition includes switching and shoot-through

FO1 ~ 100fJ, FO3 ~ 150fJ FO1 Nand / FO3 INV similar

R O p e r f o r ma n c e

RO Performance over Temperature Performance gradually reduces with temperature due to mobility, except low temps, where Vt reduction offsets degradation Operation to 300C

750 650 1.6 550 450 350 250 -50 50 150 temp (de g C ) 250 1.4 1.2 1

Analog Circuit Design - Overview

Analog design requires consideration of: Threshold voltage mismatch due to different topography Thermal management - due to Oxide thermal isolation Power consumption Slow development of analog CAD tools for SOI applications has contributed to the slow acceptance of SOI for analog circuitry Advantages of FinFET for Analog Improved frequency performance Reduced capacitance Higher drive current Reduction in interconnect length / reduced interconnect capacitance Noise and latchup are minimized through reduced substrate coupling Silicon resistors have improved linearity with respect to absolute voltage No reverse biased diodes to substrate Inductor Q enhanced through use of very high resistivity substrates Drawbacks to FinFET for Analog Poor thermal response due to buried oxide and trench isolation. 9 Quantized widths

Current Mirrors NMOS and PMOS mirrors, Input and 5 adjacent outputs Lengths 1um, 5um Matching and leakage, in sat, lin and intermediate states Poly and Metal gates Analysis over temperature Good matching (better than 2.5%) for most of current range Matching retained over supply voltages, except for higher currents Similar performance from NMOS and PMOS, though PMOS leakier
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MUGFET leakage
1.00E-08 Leakage (per fin) 1.00E-09 1.00E-10 1.00E-11 1.00E-12 1.00E-13 1.00E-14 -50 0 50 100 150 200 250 300 Temperature (C) PMOS NMOS

NMOS & PMOS fin and planar leakage as a function of temperature Fin
- leakage increase ~ 10x/100deg - leakage/fin NMOS 1nA/fin @ 300 degC PMOS 80pA/fin @ 300 deg - Ion/Ioff ratio better than 6000

Planar Leakage
Leakage per fin equivalent. 1.0E-07 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 0 50 100 150 200 250 300 Temperature NMOS PMOS

Bulk Planar
- leakage increase ~ 10x/100deg - leakage/fin equivalent NMOS 30nA/fin @ 300 degC PMOS 4nA/fin @ 300 deg - Ion/Ioff ratio about 220

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NMOS - normalized matching

1.60E+00 1.50E+00 1.40E+00 1.30E+00 1.20E+00 1.10E+00 1.00E+00 9.00E-01 8.00E-01 -100

Mirror-Matching
.1u 1u 10u 100u

Matching is better than 3% over all conditions of bias and temperatures, except for the following conditions: At very low currents NMOS and to a lesser extent PMOS mirroring is affected by leakage at high temperatures. Easily fixed with scaling or low leakage transistor options PMOS shows similar trends, but with less mismatch, due to lower baseline PMOS leakage in this FinFET material

matching

100

200

300

400

Temperature

PMOS - normalized matching

1.04E+00 1.03E+00 Matching 1.02E+00 1.01E+00 1.00E+00 9.90E-01 9.80E-01 9.70E-01 9.60E-01 -100 .1u 1u 10u

100

200

300

400

Temperature

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Opamps [5]
-NMOS and PMOS -operation -50 to 300 C -input offset better than 2mV -open loop gain > 3000 -hysteresis < 0.5mV (except 300 degrees = 0.5mV) -output switching 0-100% -I/P current 1uA-30uA
NMOS I/P Opamp - 1uA 2 output voltage

PMOS I/P Opamp - 10uA 0.5 output voltage

-50deg 50deg 150deg 200deg 300deg

1.5 1 0.5 0 -0.5 -0.003 -0.002 -0.001

0 -0.5 -1 -1.5 -2 -0.004

0deg 100deg 200deg 300deg

0.001

0.002

0.003

-0.002

0 input delta

0.002

0.004

input delta

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Advantages of FinFET over Bulk

Reduced D/S cap (oxide isolation vs junction isolation) Lower power No MOS reverse body effect" in stacked transistor devices Improved latchup, noise and current immunity through the substrate Simpler high V component design Improved high temp performance (lower device and parasitic leakage) Improved passive components Inductor Q, parasitic capacitance Reduced capacitance from substrate to metal interconnect (reduced power) Fewer process steps (Pwell / NBL) SOC, High Perf, RF, High Freq, Low Leakage, Low Power, High Temp, Smaller area Adds extra dimension (height) for additional gate width

Disadvantages of finFET v Bulk

Self heating, dissipation problems Reduced Vdd-GND capacitance for noise reduction on supply rail Start-up cost,
Engineering & Management Pushback, Extra Design time limited knowledgebase

Quantization of width Substrate cost

Why consider FinFET?

Scaling trends
Bulk requires increase in doping level with scaling, adversely affecting carrier mobility and junction capacitance. May limit scaling to 25-35nm gate lengths FinFET Scaling limits at least a generation beyond bulk
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Summary
Ring Oscillators: Demonstrated Inverter and NAND FinFET ring oscillators of various fan-outs: Gate delay of 25ps for Inv F01 at Vdd=1.2V Performance from -50 to 300 C Current Mirrors: Demonstration of current mirrors of 1-5um Systematic matching approx 2.5% or better for 1um ring Poly and Metal gate structures have similar performance Performance from -50 to 300 C Op Amps: Demonstration of NMOS/PMOS op amps DC large signal performance from -50 to 300 degrees C In line with or better than equivalent bulk op amps
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References (1) X. Huang, et-al, Sub-50nm FinFET:PMOS, IEDM Tech Digest, Dec 1999 (2) A. Marshall & S. Natarajan, SOI Design: Analog, Memory and Digital Techniques, Springer, ISBN 0-7923-7640-4 (3) M-D Ker etal, Novel Diode Structures and ESD Protection Circuits in a 1.8v 0.15um Partially Depleted SOI Salicided CMOS Process, Proc. 8th IPFA 2001, Singapore, pp91-96 (4) N. Collaert et-al, A Functional 41-Stage Ring Oscillator Using Scaled FinFET Devuces WIth 25-nm Gate Lengths and 10-nm Fin Widths Applicable for the 45-nm CMOS Node, IEEE Electron Device Letters, Vol 25, No 8, August 2004, p568-570 (5) G. Knoblinger et.al., Design and Evaluation of Basic Analog Circuit in an Emerging MuGFET Technology, IEEE SOI Conference, Oct 4-6, 2005

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