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Reel/Frame: 027991/0473

Pages: 19
Recorded: 04/04/2012

Attorney Dkt #: 079894.0557

Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 51
1

Patent #: 7346632
Publication #: US20020161815

Issue Dt: 03/18/2008

Application #: 10055208

Filing Dt: 01/23/2002

Pub Dt: 10/31/2002

Title: MECHANISM FOR EXECUTING NESTED TRANSACTIONS IN AN EXECUTION ENVIRONMENT SUPPORTING FLAT
TRANSACTIONS ONLY

Patent #: 7353398
Publication #: US20030226028

Issue Dt: 04/01/2008

Application #: 10156929

Filing Dt: 05/29/2002

Pub Dt: 12/04/2003

Title: ARTICLE, METHOD, SYSTEM AND APPARATUS FOR DECENTRALIZED CREATION, DISTRIBUTION,
VERIFICATION AND TRANSFER OF VALUABLE DOCUMENTS

Patent #: 7398237
Publication #: US20030084428

Issue Dt: 07/08/2008

Application #: 10178439

Filing Dt: 06/24/2002

Pub Dt: 05/01/2003

Title: RULE BASED ENGINE FOR VALIDATING FINANCIAL TRANSACTIONS

4

Patent #: 7340733
Publication #: US20030115579

Issue Dt: 03/04/2008

Application #: 10314094

Filing Dt: 12/05/2002

Pub Dt: 06/19/2003

Title: OPTIMIZING SOURCE CODE FOR ITERATIVE EXECUTION

5

Patent #: 7337319
Publication #: US20040111617

Issue Dt: 02/26/2008

Application #: 10621731

Filing Dt: 07/17/2003

Pub Dt: 06/10/2004

Title: METHOD OF COMPARING DOCUMENTS POSSESSED BY TWO PARTIES

6

Patent #: 7401055
Publication #: US20050086181

Issue Dt: 07/15/2008

Application #: 10686750

Filing Dt: 10/16/2003

Pub Dt: 04/21/2005

Title: SYSTEM AND METHOD FOR SETTING SPECIAL WHOLESALE PRICING FOR RESELLERS
7

Patent #: 7401281
Publication #: US20050172194

Issue Dt: 07/15/2008

Application #: 10707971

Filing Dt: 01/29/2004

Pub Dt: 08/04/2005

Title: REMOTE BIST HIGH SPEED TEST AND REDUNDANCY CALCULATION

8

Patent #: 7328396
Publication #: US20050268209

Issue Dt: 02/05/2008

Application #: 10709794

Filing Dt: 05/28/2004

Pub Dt: 12/01/2005

Title: CYCLIC REDUNDANCY CHECK GENERATION CIRCUIT

9

Patent #: 7336102
Publication #: US20060026457

Issue Dt: 02/26/2008

Application #: 10710641

Filing Dt: 07/27/2004

Application #: 10746961

Filing Dt: 12/24/2003

Pub Dt: 02/02/2006

Title: ERROR CORRECTING LOGIC SYSTEM

10

Patent #: 7376638
Publication #: US20050165741

Issue Dt: 05/20/2008

Pub Dt: 07/28/2005

Title: SYSTEM AND METHOD FOR ADDRESSING INEFFICIENT QUERY PROCESSING

11

Patent #: 7355680
Publication #: US20060146313

Issue Dt: 04/08/2008

Application #: 10905453

Filing Dt: 01/05/2005

Pub Dt: 07/06/2006

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Page 2 of 4

Title: METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS
12

Patent #: 7348610

Issue Dt: 03/25/2008

Publication #: US20060186416

Application #: 10906557

Filing Dt: 02/24/2005

Pub Dt: 08/24/2006

Title: MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE

13

Patent #: 7392516

Issue Dt: 06/24/2008

Publication #: US20060031823

Application #: 10912482

Filing Dt: 08/05/2004

Pub Dt: 02/09/2006

Title: METHOD AND SYSTEM FOR CONFIGURING A DEPENDENCY GRAPH FOR DYNAMIC BY-PASS INSTRUCTION
SCHEDULING

14

Patent #: 7353235

Issue Dt: 04/01/2008

Publication #: US20050097121

Application #: 10921444

Filing Dt: 08/19/2004

Pub Dt: 05/05/2005

Title: CONTENT FILTERING, ORDERING BY RELEVANCE, AND CACHING

15

Patent #: 7359923

Issue Dt: 04/15/2008

Publication #: US20060041569

Application #: 10923547

Filing Dt: 08/20/2004

Pub Dt: 02/23/2006

Title: ONLINE INCREMENTAL DEFERRED INTEGRITY PROCESSING AND MAINTENANCE OF ROLLED IN AND ROLLED
OUT DATA

16

Patent #: 7395530

Issue Dt: 07/01/2008

Publication #: US20060048116

Application #: 10930032

Filing Dt: 08/30/2004

Pub Dt: 03/02/2006

Title: METHOD FOR IMPLEMENTING SINGLE THREADED OPTIMIZATIONS IN A POTENTIALLY MULTI-THREADED

ENVIRONMENT

17

Patent #: 7389296

Issue Dt: 06/17/2008

Publication #: US20060047688

Application #: 10932676

Filing Dt: 09/02/2004

Pub Dt: 03/02/2006

Title: METHOD, SYSTEM AND PROGRAM PRODUCT FOR DISPLAYING A LOGICAL STRUCTURE
18

Patent #: 7367019

Issue Dt: 04/29/2008

Publication #: US20060059472

Application #: 10942428

Filing Dt: 09/16/2004

Pub Dt: 03/16/2006

Title: PARAMETER MANAGEMENT USING COMPILER DIRECTIVES

19

Patent #: 7331021

Issue Dt: 02/12/2008

Publication #: US20070101304

Application #: 11163750

Filing Dt: 10/28/2005

Application #: 11163882

Filing Dt: 11/02/2005

Pub Dt: 05/03/2007

Title: FAST/SLOW STATE MACHINE LATCH

20

Patent #: 7329940

Issue Dt: 02/12/2008

Publication #: US20070096257

Pub Dt: 05/03/2007

Title: SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE

21

Patent #: 7353472

Issue Dt: 04/01/2008

Publication #: US20070038970

Application #: 11202591

Filing Dt: 08/12/2005

Pub Dt: 02/15/2007

Title: SYSTEM AND METHOD FOR TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN
22

Patent #: 7333379

Issue Dt: 02/19/2008

Publication #: US20070159899

Application #: 11275539

Filing Dt: 01/12/2006

Pub Dt: 07/12/2007

Title: BALANCED SENSE AMPLIFIER CIRCUITS WITH ADJUSTABLE TRANSISTOR BODY BIAS
23

Patent #: 7362184

Issue Dt: 04/22/2008

Publication #: US20070200634

Application #: 11276410

Filing Dt: 02/28/2006

Pub Dt: 08/30/2007

Title: FREQUENCY DIVIDER MONITOR OF PHASE LOCK LOOP

24

Patent #: 7385781

Issue Dt: 06/10/2008

Publication #: US20080123213

Application #: 11278283

Filing Dt: 03/31/2006

Pub Dt: 05/29/2008

Title: MULTI-ARM DISK DRIVE SYSTEM HAVING INTERLEAVED READ/WRITE OPERATIONS AND METHOD OF
CONTROLLING SAME

25

Patent #: 7393703
Publication #: US20070264729

Issue Dt: 07/01/2008

Application #: 11382489

Filing Dt: 05/10/2006

Pub Dt: 11/15/2007

Title: METHOD FOR REDUCING WITHIN CHIP DEVICE PARAMETER VARIATIONS

26

Patent #: 7339364
Publication #: US20080012549

Issue Dt: 03/04/2008

Application #: 11424881

Filing Dt: 06/19/2006

Pub Dt: 01/17/2008

Title: CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT

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27

Patent #: 7345503

Page 3 of 4

Issue Dt: 03/18/2008

Publication #: US20080001620

Application #: 11427798

Filing Dt: 06/30/2006

Pub Dt: 01/03/2008

Title: METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM
NITRIDE RESISTOR DEVICES

28

Patent #: 7348634

Issue Dt: 03/25/2008

Publication #: US20060220148

Application #: 11445786

Filing Dt: 06/02/2006

Application #: 11456684

Filing Dt: 07/11/2006

Pub Dt: 10/05/2006

Title: SHALLOW TRENCH ISOLATION FORMATION

29

Patent #: 7352252

Issue Dt: 04/01/2008

Publication #: US20080024232

Pub Dt: 01/31/2008

Title: CIRCUIT AND METHOD TO MEASURE THRESHOLD VOLTAGE DISTRIBUTIONS IN SRAM DEVICES
30

Patent #: 7627835

Issue Dt: 12/01/2009

Publication #: US20070245271

Application #: 11765475

Filing Dt: 06/20/2007

Pub Dt: 10/18/2007

Title: FREQUENCY DIVIDER MONITOR OF PHASE LOCK LOOP

31

Patent #: 7642813
Publication #: US20090002015

Issue Dt: 01/05/2010

Application #: 11850857

Filing Dt: 09/06/2007

Application #: 11866471

Filing Dt: 10/03/2007

Application #: 11869988

Filing Dt: 10/10/2007

Pub Dt: 01/01/2009

Title: ERROR CORRECTING LOGIC SYSTEM

32

Patent #: 7652334

Issue Dt: 01/26/2010

Publication #: US20080017932

Pub Dt: 01/24/2008

Title: SHALLOW TRENCH ISOLATION FORMATION

33

Patent #: 7459936

Issue Dt: 12/02/2008

Publication #: US20080024166

Pub Dt: 01/31/2008

Title: FAST/SLOW STATE MACHINE LATCH

34

Patent #: 7323913

Issue Dt: 01/29/2008

Application #: 11871578

Filing Dt: 10/12/2007

Title: MULTIPHASE DIVIDER FOR P-PLL BASED SERIAL LINK RECEIVERS

35

Patent #: 8022496

Issue Dt: 09/20/2011

Publication #: US20080099787

Application #: 11873696

Filing Dt: 10/17/2007

Pub Dt: 05/01/2008

Title: SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE

36

Patent #: 8126041

Issue Dt: 02/28/2012

Publication #: US20090102452

Application #: 11874960

Filing Dt: 10/19/2007

Pub Dt: 04/23/2009

Title: CIRCUIT AND METHOD FOR ON-CHIP JITTER MEASUREMENT

37

Patent #: 8090697

Issue Dt: 01/03/2012

Publication #: US20080059965

Application #: 11925951

Filing Dt: 10/27/2007

Pub Dt: 03/06/2008

Title: MECHANISM FOR EXECUTING NESTED TRANSACTIONS IN AN EXECUTION ENVIRONMENT SUPPORTING FLAT
TRANSACTIONS ONLY

38

Patent #: 7471115
Publication #: US20080048711

Issue Dt: 12/30/2008

Application #: 11926386

Filing Dt: 10/29/2007

Application #: 11942396

Filing Dt: 11/19/2007

Pub Dt: 02/28/2008

Title: ERROR CORRECTING LOGIC SYSTEM

39

Patent #: 7378866

Issue Dt: 05/27/2008

Publication #: US20080061902

Pub Dt: 03/13/2008

Title: METHOD AND APPARATUS FOR IMPEDANCE MATCHING IN TRANSMISSION CIRCUITS USING TANTALUM
NITRIDE RESISTOR DEVICES

40

Patent #: 7685544

Issue Dt: 03/23/2010

Publication #: US20080104555

Application #: 11947254

Filing Dt: 11/29/2007

Pub Dt: 05/01/2008

Title: TESTING PATTERN SENSITIVE ALGORITHMS FOR SEMICONDUCTOR DESIGN

41

Patent #: 7378885

Issue Dt: 05/27/2008

Application #: 11959069

Filing Dt: 12/18/2007

Title: MULTIPHASE DIVIDER FOR P-PLL BASED SERIAL LINK RECEIVERS

42

Patent #: 7521735
Publication #: US20080099844

Issue Dt: 04/21/2009

Application #: 11969320

Filing Dt: 01/04/2008

Pub Dt: 05/01/2008

Title: MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE

43

Patent #: 8032747

Issue Dt: 10/04/2011

Application #: 12015536

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Filing Dt: 01/17/2008

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Publication #: US20080141030

Pub Dt: 06/12/2008

Title: COMPARISON OF DOCUMENTS POSSESSED BY TWO PARTIES

44

Patent #: 7818812

Issue Dt: 10/19/2010

Publication #: US20080184337

Application #: 12018176

Filing Dt: 01/22/2008

Pub Dt: 07/31/2008

Title: ARTICLE AND SYSTEM FOR DECENTRALIZED CREATION, DISTRIBUTION, VERIFICATION AND TRANSFER OF
VALUABLE DOCUMENTS

45

Patent #: 7826038

Issue Dt: 11/02/2010

Publication #: US20080131795

Application #: 12029506

Filing Dt: 02/12/2008

Pub Dt: 06/05/2008

Title: METHOD FOR ADJUSTING LITHOGRAPHIC MASK FLATNESS USING THERMALLY INDUCED PELLICLE STRESS
46

Patent #: 7631236

Issue Dt: 12/08/2009

Publication #: US20080178053

Application #: 12057405

Filing Dt: 03/28/2008

Pub Dt: 07/24/2008

Title: HYBRID BUILT-IN SELF TEST (BIST) ARCHITECTURE FOR EMBEDDED MEMORY ARRAYS AND AN
ASSOCIATED METHOD

47

Patent #: 7472325
Publication #: US20080215937

Issue Dt: 12/30/2008

Application #: 12062599

Filing Dt: 04/04/2008

Pub Dt: 09/04/2008

Title: A METHOD FOR SEGMENTING BIST FUNCTIONALITY IN AN EMBEDDED MEMORY ARRAY INTO REMOTE

LOWER-SPEED EXECUTABLE INSTRUCTIONS AND LOCAL HIGHER-SPEED EXECUTABLE INSTRUCTIONS

48

Patent #: 7541613

Issue Dt: 06/02/2009

Publication #: US20080246097

Application #: 12117014

Filing Dt: 05/08/2008

Pub Dt: 10/09/2008

Title: METHODS FOR REDUCING WITHIN CHIP DEVICE PARAMETER VARIATIONS

49

Patent #: 7877416

Issue Dt: 01/25/2011

Publication #: US20080288514

Application #: 12118155

Filing Dt: 05/09/2008

Pub Dt: 11/20/2008

Title: SYSTEM AND PROGRAM PRODUCT FOR DISPLAYING A LOGICAL STRUCTURE

50

Patent #: 8001525

Issue Dt: 08/16/2011

Publication #: US20080250411

Application #: 12118799

Filing Dt: 05/12/2008

Pub Dt: 10/09/2008

Title: RULE BASED ENGINE FOR VALIDATING FINANCIAL TRANSACTIONS

51

Patent #: 7710683

Issue Dt: 05/04/2010

Publication #: US20080225431

Application #: 12127108

Filing Dt: 05/27/2008

Pub Dt: 09/18/2008

Title: MULTI-ARM DISK DRIVE SYSTEM HAVING INTERLEAVED READ/WRITE OPERATIONS AND METHOD OF
CONTROLLING SAME

Assignor
1

INTERNATIONAL BUSINESS MACHINES CORPORATION

Exec Dt: 03/27/2012

Assignee
1

FACEBOOK, INC.
1601 WILLOW ROAD
MENLO PARK, CALIFORNIA 94025

Correspondence name and address

BAKER BOTTS, L.L.P.
2001 ROSS AVENUE
SUITE 600
DALLAS, TX 75201
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