DESIGN OF ENERGY EFFICIENT ARRAY MULTIPLIER USING ADIABATIC LOGIC

A PHASE-II PROJECT REPORT Submitted by

SHANKAR.R (104VD114)
In partial fulfillment for the award of the degree of

MASTER OF ENGINEERING
in VLSI DESIGN

May 2012
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

BANNARI AMMAN INSTITUTE OF TECHNOLOGY

(An Autonomous Institution Affiliated to Anna University of Technology, Coimbatore)

SATHYAMANGALAM-638 401

BANNARI AMMAN INSTITUTE OF TECHNOLOGY (An Autonomous Institution) SATHYAMANGALAM-638 401

DESIGN OF ENERGY EFFICIENT ARRAY MULTIPLIER USING ADIABATIC LOGIC

Bonafide record of the work done by

SHANKAR.R (104VD114)
Project report submitted in partial fulfillment for the award of the degree of

MASTER OF ENGINEERING
in VLSI DESIGN Anna University of Technology, Coimbatore

May 2012

E.Dinesh, M.E., Assistant Professor (SUPERVISOR)

Dr.S.Valarmathy, M.E., Ph.D Professor (HEAD OF THE DEPARTMENT)

Certified that the candidate was examined in the viva-voce examination held on 03.05.2012

(Internal Examiner)

........ (External Examiner)

DECLARATION BY THE CANDIDATE

I hereby declare that the project report entitled Design of Energy Efficient Array Multiplier Using Adiabatic Logic submitted in partial fulfillment of the requirements for the award of degree of Master of Engineering in VLSI Design is a record of original research work done by me under the supervision and guidance of Mr.E.Dinesh, Assistant Professor, Department of Electronics and Communication Engineering. This research work has not formed the basis for the award of any degree/diploma/Associate ship/fellowship or other similar title to any candidate of any college.

Signature of the Candidate (SHANKAR.R)