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Culture Documents
4/scripts/GUI
create design.pl
#!/usr/bin/perl -w
################################################################################
#
#
#
# Copyright (C) 2002,2003 Wim Vanderbauwhede. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
#
# under the same terms as Perl itself.
#
#
#
################################################################################
#
use strict;
#This script is called for new designs.
#It creates the directory structure and the design library
my $design=(@ARGV)?$ARGV[0]:'';
if(! -d "DeviceLibs") {
mkdir "DeviceLibs",0755;
mkdir "DeviceLibs/Objects",0755;
mkdir "DeviceLibs/Objects/DeviceLibs",0755;
mkdir "TestObj",0755;
mkdir "Schematics",0755;
mkdir "Diagrams",0755;
}
if($design && !(-d "DeviceLibs/Objects/$design")) {
print "Creating $design design\n";
mkdir "DeviceLibs/Objects/$design",0755;
mkdir "DeviceLibs/Objects/$design/DeviceLibs",0755;
mkdir "TestObj/$design",0755;
mkdir "Schematics/$design",0755;
mkdir "Diagrams/$design",0755;
use Verilog::CodeGen;
chdir "DeviceLibs/Objects/$design";
if(!$design){$design='Verilog'};
&make_module('Empty',$design);
}
#create .vcgrc file which contains current design
if (!$design) {$design = 'Verilog'}
open(VCG,'>.vcgrc');
print VCG "$design\n";
close VCG;
debug.pl
#!/usr/bin/perl -w
################################################################################
#
#
#
# Copyright (C) 2002,2003 Wim Vanderbauwhede. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
#
# under the same terms as Perl itself.
#
#
#
################################################################################
#
use strict;
#-creates Perl object code if none exists
#-otherwise parses code
use Verilog::CodeGen;
my $current='';
my $s=0;
my $d=0;
if(@ARGV){
$current=$ARGV[0];
}
if($current eq '-s') {
$current=$ARGV[1]||'';
$s=1;
$d=0;
}
if($current eq '-sd') {
$current=$ARGV[1]||'';
$s=0;
$d=1;
}
my $design=$ARGV[@ARGV-1];
if($design=~/^\-/){$design=''}
#my $up=($design)?'../':'';
#if($design eq $current){$current=''};
if($design eq $current){$design=''};
my $up=($design)?'../':'';
chdir "DeviceLibs/Objects/$design";
my @objs=();
if($current=~/\w_*.*\.pl/){
push @objs,$current;
} else {
@objs=`ls -1 -t *$current*.pl`;
}
if(@objs>0) {
if($current ne '' ) {
print "Found ",scalar(@objs)," files matching $current:\n";
inspect code.pl
#!/usr/bin/perl -w
################################################################################
#
#
#
# Copyright (C) 2002,2003 Wim Vanderbauwhede. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
#
# under the same terms as Perl itself.
#
#
#
################################################################################
#
use strict;
################################################################################
#
#
#
# Copyright (C) 2002,2003 Wim Vanderbauwhede. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
#
# under the same terms as Perl itself.
#
#
#
################################################################################
#
#This script very simply sends everything it receives on STDIN to TCP port $port
on the localhost.
use strict;
use IO::Socket;
my $port=2507;
my $new_sock;
my $buff;
my $sock = new IO::Socket::INET (
PeerAddr => 'localhost',
PeerPort => $port,
Proto => 'tcp',
);
die "Socket could not be created: $!" unless $sock;
while (<STDIN>) {
my $line=$_;
print $sock $line;
#print "SENT:$line\n";
$sock->flush();
}
close ($sock);
test.pl
#!/usr/bin/perl -w
################################################################################
#
#
#
# Copyright (C) 2002,2003 Wim Vanderbauwhede. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
#
# under the same terms as Perl itself.
#
#
#
################################################################################
#
use strict;
use Cwd;
### -Creates a testbench if none exists
### -Otherwise runs the testbench
my $current='';
# by default, just open the tb for editing or create from template
my $force=0;
my $show=0;
my $run=0;
my $plot=0;
my $parse=0;
if(@ARGV){
$current=$ARGV[0];
}
if($current eq '-f') {
$current=$ARGV[1]||'';
$force=1;
}
if($current eq '-yes') {
$current=$ARGV[3]||'';
$parse=1;
$show=1;
if($ARGV[1] eq '-on'){$plot=1}
if($ARGV[2] eq '-on'){$run=1}
}
if($current eq '-no') {
$current=$ARGV[3]||'';
$parse=1;
$show=0;
if($ARGV[1] eq '-on'){$plot=1}
if($ARGV[2] eq '-on'){$run=1}
}
my $design=$ARGV[@ARGV-1]||'';
if($design=~/^\-/){$design=''};
#if($design eq $current){$current=''};
if($design eq $current){$design=''};
my $up=($design ne '' )?'../':'';
#===============================================================================
#
# Get the perl object file
#
chdir "DeviceLibs/Objects/$design";
my @objs=();
if($current=~/test_.*\.pl/){
push @objs,$current;
} else {
$current=~s/test_//;
@objs=`ls -1 -t *$current*.pl`;
}
if(@objs>0) {
if($current ne '') {
$regs.="$in\n";
my $inps=$in;
$inps=~s/reg\ //;
$inps=~s/\s*;.*//;
my @regs=split(',',$inps);
foreach my $reg (@regs) {
$reg=~s/\[.*\]//;
my $inp=uc($reg);
$assigns.="assign $inp=$reg;\n";
}
} # if input
s/input|output|inout/wire/;
} # foreach pin
my $pinlist=join('',@pins);
my $b='';
$outputs=~s/^\,//;
my @outputs=split(/\,/,$outputs);
$outputs='';
my $title='';
foreach my $out (@outputs) {
# build the $display line
$b.=' \%b';
$outputs.=',$x.'.$out;
$title.=" $out";
}
my $defaultdesign='Verilog';
if($design){$defaultdesign=$design};
#if(!$design){$design='Verilog'}
$tb_template='#!/usr/bin/perl -w
use strict;
use lib "'.$up.'..";
use DeviceLibs::'.$defaultdesign.';
################################################################################
my $device=new("'.$current.'",'.$paramlist.');
open (VER,">test_'.$current.'.v");
output(*VER);
modules();
print VER "
module test_'.$current.';
'.$pinlist.'
'.$regs.'
'.$assigns.'
reg _ck;
";
$device->instance();
my $x=$device->{""};
print VER "
// clock generator
always begin: clock_wave
#10 _ck = 0;
#10 _ck = 1;
end
always @(posedge _ck)
begin
\$display(\" \%0d '.$b.' \",\$time'.$outputs.');
end
initial
begin
\$display(\"Time '.$title.'\");
//
//
\$dumpfile(\"test_'.$current.'.vcd\");
\$dumpvars(2,test_'.$current.');
#25;
\$finish;
end
endmodule
";
close VER;
run("test_'.$current.'.v");
#plot("test_'.$current.'.v");
';
} # created testbench
chdir "$up../.."; #to root
chdir "TestObj/$design" or die "$!: TestObj/$design";
#Create testbench code
if ($force or (not -e "test_$current.pl")) { # force overwrite or file did not e
xits
open(TB,">test_$current.pl");
print TB $tb_template;
close TB;
}
if($parse) {
print "\n",'-' x 60,"\n","\tParsing test_$current.pl testbench ...\n",'-' x 60
,"\n";
if($run) {#run
if ($plot) {# plot
system("perl -p -i -e 'if(/dump/){s/^\\/+//};s/^\\#plot/plot/;s/^\\#run/ru
n/;' test_$current.pl");
} else {# no plot
system("perl -p -i -e 'if(/dump/){s/^/\\/\\//};s/^plot/\\#plot/;s/^\\#run/
run/;' test_$current.pl");
}
} else {#don't run
system("perl -p -i -e 'if(/dump/){s/^/\\/\\//};s/^plot/\\#plot/;s/^run/\\#ru
n/;' test_$current.pl");
}
system("perl test_$current.pl");
if($show) {
system("gnuclient test_$current.v &");
} elsif(!$run) {
update.pl
#!/usr/bin/perl -w
################################################################################
#
#
#
# Copyright (C) 2002,2003 Wim Vanderbauwhede. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
#
# under the same terms as Perl itself.
#
#
#
################################################################################
#
use strict;
#-adds new objects to the design library
my $show=0;
if(@ARGV){
$show=$ARGV[0];
}
if($show eq '-s') {
$show=1;
} else {
$show=0;
}
my $design=$ARGV[@ARGV-1]||'';
if($design=~/^\-/){$design=''}
my $up=($design ne '')?'../':'';
chdir "DeviceLibs/Objects/$design";
print '-' x 60,"\n","\tUpdating Verilog.pm ...\n",'-' x 60,"\n";
use Verilog::CodeGen;
#system("perl make_module.pl &");
if(!$design){$design='Verilog'}
&make_module('',$design);
if($show==1){
chdir "$up..";
exec("gnuclient $design.pm &");
}