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Table Of Contents

2.2 Timing using multiclock propagation
2.3 Clock groups
2.4 The promiscuous clock problem
2.5 A new solution to this old problem – the –combinational switch
2.6 Avoiding the generated clock entirely: the –reference switch
3 Using multiclock propagation to time a shared set of input pins
3.1 The circuit
3.2 Timing using multiclock propagation
3.3 Clocks everywhere!
3.4 The new clock killer command
4 A more complex example – a multi-mode output circuit
4.1 The circuit
4.2 The strategy
4.3 Creating the PLL tap clocks
4.4 High-speed Modes
4.4.1 Mode H1
4.4.2 The HS output clock
4.4.3 Mode H2
4.5 Low-speed Modes
4.5.1 Mode L1
4.5.2 Creating the clocks
4.5.3 Handling the output clock
4.5.4 Mode L2
4.6 Other considerations
4.6.1 H* mode divide-by 2 clocks
4.6.2 lssel_setting
4.6.3 Control logic
5 Conclusion
6 Acknowledgements
7 References
8 Appendix
8.1 Complex Circuit at Full Page Size
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Multiclk Final 032807

Multiclk Final 032807

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Published by Reena Mathew

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Published by: Reena Mathew on May 04, 2012
Copyright:Attribution Non-commercial

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