VLSI DESIGN|Question Bank
K.P.SAI PRADEEP|ASSISTANT PROFESSOR|ECE|Dr.N.G.P.IT
Define threshold voltage.
The Threshold voltage, V
for a MOS transistor can be defined as the voltageapplied between the gate and the source of the MOS transistor below which the drain tosource current, I
effectively drops to zero. Threshold voltage is the voltage at whichthe device turns on or starts conducting.
What is self aligned technique?
In the MOSFET fabrication process, gate and n+ or p+ regions automaticallyaligned to each other which is known as self aligned technique.
What is CMP?
Planarization is mandatory in chips that use more than two or three metallayers. The most common technique is Chemical-Mechanical Polishing (CMP) which iscapable of producing very flat surfaces.
What is meant by doping? List some of dopants.
The process of adding impurity atoms is called doping. Impurities themselvesare called dopants, e.g. - arsenic and silicon.
What is LDD?
LDD is Lightly Doped Drain structure. This structure is used to reduce somesmall device effect due to very energetic partials called hot electrons and hot holes.
What are generations of Integration Circuits?
SSI (Small Scale Integration), MSI (Medium Scale Integration) , LSI (Large ScaleIntegration) , VLSI (Very Large Scale Integration) , ULSI (Ultra Large Scale Integration ,GSI(Giga Scale Integration).
Give the basic process for IC fabrication.
Silicon wafer Preparation, Epitaxial Growth, Oxidation, Photolithography, Diffusion, IonImplantation, Isolation technique, Metallization, Assembly processing & Packaging.
What are the different layers in MOS transistors? -
Drain, Source & Gate
Give the different types of CMOS process?
P-well process, N-well process, Silicon-On-Insulator Process, Twin- tub Process.
What are the steps involved in twin-tub process?
Tub Formation, Thin-oxide Construction, Source & Drain Implantation, Contactcut definition, Metallization.
What are the advantages of CMOS process?
Low power Dissipation, High Packing density, Bi directional capability, LowInput Impedance, Low delay Sensitivity to load.
What is pull down device?
A device connected so as to pull the output voltage to the lower supply voltageusually 0V is called pull down device. nMOS is good for logic ‘0’ so it is known as pulldown device.
What is pull up device?
A device connected so as to pull the output voltage to the upper supply voltage usuallyV
is called pull up device. pMOS is good for logic ‘1’ so it is known as pull up device.