Fat-Pyramid-NOC and Fat-Stack-NOC:
New Frameworks Network-On-Chip Architectures
Reza KourdyDepartment of Computer EngineeringIslamic Azad University,Khorramabad Branch, IranMohammad Reza Nouri radDepartment of Computer EngineeringIslamic Azad University,Khorramabad Branch, Iran
— Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communicationarchitecture for Systems on Chips (SoCs). This paper proposes a general framework for the design and simulation of network-on-chip-based pyramid architectures such as Fat-Pyramid-NOC and Fat-Stack-NOC. Several parameters in the design spaceare investigated, namely, network topology, parallelism degree, and the Scalability. Emulation is necessary to evaluate andvalidate the performance of the NoC system.
— Network-on-Chip (NoC), Systems on Chip (SoC), Field-Programmable Gate Array (FPGA), processing element(PE).
atest applications ported to embedded systems(e.g., scalable video rendering, communication proto-cols) demand a large computation power, while mustrespect other critical embedded design constraints, suchas, short time-to-market, low energy consumption or re-duced implementation size.Thus, embedded systems are complex Systems-on-Chip (SoCs) that consist of a large number of components,such as, processing elements, storage devices and evenreconfigurable devices, such as Field-Programmable GateArrays (FPGAs), to enhance the flexibility of final SoCs tobe used in different environments , .Nevertheless, one of the most critical areas of MPSoCdesign is the definition of the suitable interconnect sub-system for all these SoC components, due to architecturaland physical scalability concerns . In fact, traditionalshared bus interconnects are relatively easy to design, butdo not scale well for latest and forthcoming SoC consum-er platforms.In order to cope with the large communication de-mands of such SoCs, the use of modular and scalableNetworks-on-Chips (NoCs) has been proposed . Then,designing custom-tailored NoC interconnects that satisfythe performance and design constraints of the SoC for allthe different combinations of possible executed applica-tions is a key goal to achieve optimal commercial prod-ucts ,.However, as general-purpose processor cores are usedto run software tasks of different applications in SoCs, thecommunication between the cores cannot be precharacte-rized and fully optimized, since the application processescan be mapped differently to the cores, typically with thesupport of the compiler. Thus, to provide predictable per-formance of the NoC, the bandwidth capacity of the dif-ferent links must be sufficient to support the peak rate oftraffic on the links of the possible different mappings ofthe tasks onto the final SoC. Otherwise, the networkmight experience traffic congestion and the latency for thetraffic streams and, hence, the interconnect performancewill become unacceptable, which needs to be avoided toprovide appropriate consumer devices.As a result, NoCs designs that guarantee worst-casebandwidth conditions of SoC operation with multipleconcurrent application often leads to over-sized topolo-gies and links on regular operation of the SoC. In this con-text, the development of new methods and frameworksthat increase the runtime versatility of initial static NoCdesigns to adapt to different working conditions, origi-nated by the diversity of sets of applications at each mo-ment, is an important research area in the NoC domain.Networks on Chips (NoCs) have been proposed as apromising solution to complex on-chip communicationproblems. However, many challenging research problemsremain unsolved at all levels of design abstraction, suchas design exploration of NoC architecture for applica-tions;scheduling and mapping algorithms; evaluation ofswitching, topology or routing algorithms for efficientexecution of applications; and optimizing communicationcosts, area, energy, and so forth. A solution to solving theabove problems calls for the development of a synthesiz-able, parameterizable NoC framework that would eva-luate and implement these problems and algorithms withminimum ease and flexibility.
The proposed NoC framework consists of five main
JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617https://sites.google.com/site/journalofcomputingWWW.JOURNALOFCOMPUTING.ORG1