JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.

ORG

150

A New Power Efficient SEU-Tolerant Latch Design for Walking Robots

Department of Computer Engineering

Erfan AghaKArim Alamdar Islamic Azad University, Khorramabad Branch, Iran

Department of Computer Engineering

Reza Kourdy

Islamic Azad University, Khorramabad Branch, Iran

Department of Computer Engineering

Mohammad Reza Nouri rad Islamic Azad University, Khorramabad Branch, Iran .

Abstract The novel lath is convenient for those walking robots in which the power consumption is critical .The continuous decrease in CMOS technology feature size increases the susceptibility of such circuits to single event upsets (SEU) caused by the impact of particle strikes on system flip flops. This paper presents a novel SEU-tolerant latch in which redundant feedback lines are used to mask the effects of SEUs. The power dissipating, area, reliability, and propagation delay of the proposed SEU-tolerant latch are analyzed by SPICE simulator. The simulation results show that this latch consumes about 25% less power and occupy 29% less area than a TMR -latch. However, the reliability and the propagation delay of the proposed latch are still the same as the TMR-latch .The paper also compares the reliability of the new latch with that of the three documented SEU latches. Key words: SEU, Reliability, Fault tolerance, Latency. 1. Introduction When a high energy neutron or an alpha particle strikes a sensitive region in a semiconductor device, a single event upset (SEU) occurs that can alter the state of the system resulting in a soft error. Traditionally, single event upsets were only the main concern for space applications [17]. Currently, smaller feature size, lower voltage levels and higher frequencies of deep sub-micron integrated circuits, make the circuits susceptible to the SEUs even at the ground level [2-4]. Since the chip and the packaging materials emit alpha particles, packaging cannot be effectively used to shield circuits against SEUs [14]. In addition, SEUs can also be caused by neutrons which can easily penetrate through packages [13]. These two facts address the importance of incorporating SEU-tolerance techniques to digital circuits to increase their reliability requirements. SEU-tolerant techniques can be applied to three levels of digital systems: Device level, System level and Circuit level [14,15]. An example of device level techniques is the extra doping layer

[5] which can be applied in fabrication process to suppress the effects of particle strikes and to reduce the probability of SEUs. At System level some techniques such as error detection and correction codes [12], control flow checking [7] and using information, hardware or time redundancy are used to reduce the SEU effects. At Circuit level robust circuit design techniques are employed to mitigate or eliminate the sensitivity of the circuit to SEUs [8-11] [15] [16]. One effective way to overcome the SEU effects at circuit level is to triplicate each system latch i.e. TMR-latch. Although the TMR-latch is highly reliable and widely used latch, it suffers from high area overhead and power dissipation which are not acceptable for applications in which cost and power consumption are of primary concerns. To reduce the cost and the power consumption, some techniques have employed redundant components inside the latch [9] [15] [16]. Unlike the TMR-latch, these latches cannot tolerate all the SEUs and they can only mitigate the effects of relatively low energy particles. The contributions of this paper are twofold: i. A new circuit level technique for protecting latches against SEUs is proposed. This latch provides the same reliability as a TMR-latch and occupies 29% less area and consumes about 25% less power than the TMR latch. In the proposed technique, a redundant feedback line is added to the latch and also a filtering circuit is utilized to combine the redundant and original feedback lines in a way that the occurrence of an SEU in a line has no effect on the other line. In fact, the filtering circuit prevents the propagation of SEU effects through the latch output regardless of the amount of the particle energy. ii. Detailed SPICE-based fault injection experiments have been performed for analyzing the SEU-tolerant as well as SEUhardened latches presented in [9] [15] [16]. This analysis shows that: a. In most of the previous SEU-tolerant latches, except for the TMR-latch, there are still some parts in a latch which are not protected and are very vulnerable to SEUs. Most of the previous SEU-tolerant latches, except for the TMR-latch, cannot tolerate the SEUs caused by relatively high energy particles. The analysis shows that the proposed SEU-tolerant latch has no one of the two above limitations. The organization of this paper is as follows: In section 2 the novel fault tolerant latch is introduced. Section 3 provides a reliability comparison of the novel and one

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

151

of the widely used latches. In section 4 power and performance characteristics of the novel latch are investigated. Section 5 gives some results of this work.

2. The Proposed SEU-Tolerant Latch

A conventional latch (Figure 1.b) employs a feedback path which to hold the data during the keeping phase. Suppose that a transient voltage pulse (due to a SEU ) occurs in the feedback path during the keeping phase. This may change the output of the latch depending on the amount of deposited charge. In this paper, a redundant feedback along with a filtering circuit is used to prevent the SEU effect propagation through the output. The filtering circuit, called C-element is a modified inverter, is shown in Figure 1.a [19]. The C-element is a state holder element which inverts its inputs only if both of its inputs have identical logic values. If the two inputs of this circuit have different values, the previous output value will be retained. Figure 1.c shows the output of the C-element for some sample input values. During the time interval (t0, t1) since the inputs A and B have the same values equal to "1", the output value becomes "0" i.e., the C-element acts as an inverter. When the inputs A and B have different values in the time interval (t1, t2), the C-element retains its output and enters to its filtering mode.

or N4 through the feedback line. The C-element 3 is responsible for preventing the propagation of the transient occurred in the node N3 or N4. Again suppose that the initial values of nodes N1 and N2 are "1". If a transient occurs in the node N3 or N4, the two inputs of the C-element 3 will take different values. This deference enters the C-element 3 to its filtering mode, so that the transient is not propagated to output. Since a value change of node N3 or N4 appears in node N1 or N2, the Celements 1 and 2 act as a filtering circuit. Consequently, all of the elements are in the filtering mode (keeping their previous values) until the next level of the clock signal in which the new data must be written.
__________

CLK

__________

CLK

__________

CLK

__________

CLK

__________

CLK

Figure 2. The proposed SEU-Tolerant latch.

Figure 1. The C-element (a), Traditional latch (b), Sample input/output of the C-element (c).

Figure 2 shows the block diagram of the proposed SEUtolerant latch. Three C-elements are used to construct the redundant feedback. The C-elements 1 and 2 are used to prevent the propagation of a transient occurred in node N1 or N2 to the output and the C-element 3 protects the output from the transient occurred in nodes N3 or N4. Suppose that the initial value of nodes N1 and N2 are "1", thus nodes N3 and N4 will be at state "0". In this case, if a transient occurs in the node N1, the value of this node will be changed to "0" .It will be then propagated to both C-elements 1 and 2. Since the node N2 is not affected by the transient, the C-elements 1 and 2 fall into their filtering mode and retain their previous values, "0" i.e., the values of nodes N3 and N4 are not affected by the transient. Therefore the output will not be erroneous. As the values of nodes N3 and N4 are not affected by the transient, the value of node N1 or N2 will be corrected by the node N3

As it seen in figure 2, two subsequent red NOTs and a red transmission gate have been used in the output of proposed latch .For the adequate speed of the proposed latch, it is necessary to switch at a high rate at the time of usual action and there for, it is needed that the new changed data to be written at the output with out any interfere. So the red transmission gate receive the clock with delay, so red NOTs acting as an open circuit at switching time, and confirm the output with a little delay in normal mode, but if a fault occurs, the red transmission gate receive the clock with a delay and cause the output data remain in the previous voltage until the effects of SEU disappeared or next clock occurred. In this way, when a fault was happened the output voltage level is preserved at the previous level and the parasitic capacitors can not discharge the output voltage. Also these NOTs prevent from the open circuit the output which results in various faults. Hence they play an important role in fault tolerance of the proposed latch.

3. Comparative Analysis
As the main focus of this paper is the design of a circuit level SEU-tolerant latch, the TMR-latch along with a SEU-tolerant latch proposed in [21] are selected, and their reliability are compared with that of our novel latch .

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

152

Figure 4. Gate level schematic of a TMR-latch. Figure 3. A particle strike.

3.1. SEU-Injection Method

To investigate the SEU-tolerance capability of the proposed latch, the SPICE based SEU-injection experiments were used. The simulations were carried out for both latches using CMOS predictive transistor models presented in [8]. SEUs were injected using the current source, which can accurately represent the electrical impact of a particle strike. Similar approaches have been used in [13] [17] [20]. Figure 3 shows the injected current caused by a particle strike using the following model [13]:

I inj (t ) =

2 T

t T e T

3.2. Reliability Analysis of the Previous Work

As shown in Figure 4, a TMR-latch includes three identical latches with a voting circuit. Due to a large amount of redundancy used in TMR-latch, its area overhead and power dissipation are rather high. In contrast, since the SEU can affect only one of the latches at a time, the TMR-latch can tolerate the soft error caused by the SEU. Therefore this technique is extremely robust against soft errors. For example in [15], a SEU-tolerant latch is proposed (Figure 5). This latch includes two identical parts, one is the original part and the other is the redundant part. Each part contains two cascaded inverters similar to the conventional latch discussed in the previous section.

The first inverter is a CMOS inverter and the second one is a C2MOS inverter which plays the role of the inverter and the transmission gate of the conventional latch. Separating the input of n-type and p-type transistors of the all inverters is the key idea of this design. As it can been seen from Figure 5, the gate of the p-type transistor T1 in the first inverter (CMOS inverter) is connected to node N1, and the gate of its n-type transistor T2 is connected to node N3 (from the redundant part). The separation has also been applied to the second inverter (C2MOS inverter) as well as inverters in the redundant part. Since the original and the redundant parts are identical, the nodes N1, N3 and also the nodes N2, N4 have the same values in normal operation mode (without any SEUs). As mentioned before, the SEU cannot alter two different parts of the circuit simultaneously. Based on this fact, by the use of separation technique, i.e. providing the input of p- and type transistor in the inverters from different parts of the circuit, the propagation of the SEU effects toward the output will be canceled. The main drawback of this technique is that it is only efficient in the case of low energy particle strikes and if a relatively high energy particle strikes a sensitive region of the circuit, the output will be affected. The reason is that the CMOS and C2MOS inverters (in which the inputs of t p-type and n-type transistors are separated) cannot act as a filter when a high voltage is applied to one of their inputs. Figures 6, 7 and 8 demonstrate the circuit level schematic and behavior of a separated CMOS inverter (a CMOS inverter with two separated inputs for p- and n-type transistors) when a high and a low energy particles strike one of its inputs. Suppose that the input A and B of the inverter (shown in Figure 6) are "0" and a transient pulse occurs in the input A at time 4 ns and continues for about 1 ns. Figure 7.a shows that there is a low voltage drop, while a low energy SEU is injected to input A of the inverter. In this case, the output is still interpreted as "1".

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

153

Figure 5.The proposed latch in [15].

Figure 9. SEU-injection to the proposed latch in [15].

Figure 6. A separated CMOS inverter.

Figure 7. A transient pulse caused by a low energy particle.

In contrast, as represented in Figure 7.b the output of the inverter has significantly changed due to a high energy particle strike. The main reason of this phenomenon is that the produced current between drain and source of the transistor increases quadratically by rising the gate voltage of the transistor. Therefore most of the collected charge in the output capacitance is discharged through the n-type transistor. Based on the above discussion, a transient pulse on susceptible nodes of this latch such as nodes N1, N2, N3 and N4 causes a transient pulse in the output of the corresponding inverters, and this transient is latched through the constructed loop in the keeping phase of the latch. Figure 9 represents the simulation results of SEU injection into susceptible nodes of this latch (nodes N1 to N4 of Figure 5). As it can be seen, after SEU-injection the output is different from the error-free output. The SEU-injection results imply that the used inverters in this latch do not filter the effect of SEU occurred in one of their inputs in the case of a high energetic particle strike. Other latches that presented in [9][16] include sensitive node that not covered against soft errors. 3.3 Reliability Analysis of the Proposed Latch Based on the simulation results, all of the previously proposed SEU-tolerant latches have at least one susceptible node in which the SEU effect can be propagated to the output, resulting in a soft error in the latch. To address this issue, in the proposed latch a feedback path along with a C-element are used to form a fully isolated feedback line. The simulation results (Figure 10) show that the proposed latch masks the effect of SEUs at all of the fault injection points (see Figure 2). It should be considered that two feedbacks in the proposed design are identical. Thus only the fault injection results of nodes N1 and N3 are reported. The SEU-injections are preformed both for SEUs that cause a

Figure 8. A transient pulse caused by a high energy particle.

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

154

voltage drop and for those causes a voltage rise in susceptible nodes, but for the sake of simplicity only some of the SEUinjection results are reported here. Figure 10.a shows that a voltage drop in node 1, due to the SEU injection, is filtered by the C-element 1 (see Figure 2) and the transient cannot be propagated to the node N3. Node N1 is also recovered by the correct value in node N3 through the feedback line. The SEUinjection to node N3 is also represented in Figure 10.b. The SEU causes a voltage rise in node N3 and this transient propagates to the node N1 which is connected to C-elements 1 and 2.When the inputs of the C-elements are considered, these two C-elements filter the effect of the injected SEU so that both feedback lines will be disjointed. On the other hand, the value of node N3 differs from that of N4, and this moves the C-element 3 toward its filtering mode. Thus, the injected SEU effect cannot pass through the output. The SEU-injection results in Figure 10.b show that although the value of node N3 is not recovered but the output of the latch is still correct.

4. Performance and Power Analysis

Since fault-tolerant techniques use redundancy, some power, area and performance overheads may be imposed to the systems i.e., the more fault tolerance is achieved, the more overheads is imposed to the system. Therefore, the evaluation of such overheads is essential to demonstrate the effectiveness of a technique. The area overhead is directly proportional to the number of transistors used. In the proposed technique, 30 transistors are used while the number of required transistors in the TMR latch is 42. Thus the proposed latch occupies approximately 29% less area than the TMR-latch the power

consumption of a VLSI system can be subdivided into two main components: dynamic power and leakage power. Until recently dynamic power has been the main source of the power consumption. However, in deep-submicron CMOS, the technology shrinkage causes transistor sub-threshold leakage current to increase exponentially which results in a corresponding increase in leakage power, so that the leakage power becomes comparable to the dynamic power [17] [20]. The switching power is the dominant part of the dynamic power in a CMOS circuit. The switching power is proportional to the total capacitance, supply voltage, clock frequency and the expected number of transitions per clock cycle [20]. Since switching power dissipation is in direct proportion to switching activity of the circuit nodes, it can be minimized by performing circuit optimization. Since in the TMR-latch two extra latches along with some other circuits is exploited only for reliability enhancement, the switching activity increases significantly in comparison with a simple latch. In fact the redundancy for reliability objectives always increases the switching activity resulting in extra switching power dissipation. Although in the proposed latch, the number of transistors is reduced by about 29% in comparison with the TMR-latch, the switching activity decreases by the same amount i.e., it consumes about 25% less switching power than the TMR-latch. On the other hand, the leakage current which is caused by the off-state transistors in the circuit is the main source of leakage power dissipation. Therefore if the average number of off-state transistors per clock cycle is reduced in a design, the amount of leakage power dissipation will be also decreased. Since the number of transistors in

Figure 10. Behavior of the proposed latch with injection at (a) node 1 (b) node 3 (c) without injection.

JOURNAL OF COMPUTING, VOLUME 4, ISSUE 4, APRIL 2012, ISSN 2151-9617 https://sites.google.com/site/journalofcomputing WWW.JOURNALOFCOMPUTING.ORG

155

the proposed latch is about half of the TMR-latch, the average number of off-state transistor per clock cycle is definitely diminished. Simulation results in 250nm technology by using HSPICE show average power consumption in new latch is 29% smaller than TMR latch (see figure 11) .In short, the simulation results reveal that the proposed latch has approximately 25% reduction both in dynamic and leakage powers. Therefore it makes the proposed SEU-tolerant latch suitable for use in deep sum-micron technologies. In order to investigate the power efficiency of a method it is mandatory to consider the amount of imposed performance overhead too. Power delay product which is interpreted as energy per result is the most widely used metric to compare low power design techniques [20].

6. References
[1] G.C. Messenger, Collection of Charge on Junction Nodes from Ion Tracks, IEEE Trans. Nuclear Science, 1982, pp. 2024-2031. [2] N. Cohen, T.S. Sriram, N. Leland, D. Moyer, S. Butler, R. Flatley,Soft error considerations for deep-submicron CMOS circuit applications, International Electron Devices Meeting, Washington, DC, 1999, pp. 315 318. [3] R.W. Keyes, Fundamental limits of silicon technology, Proc. IEEE, vol. 89, no. 3, Mar. 2001, pp. 227339. [4] S. Mitra, T. Karnik, N. Seifert, M. Zhang, "Logic soft errors in sub-65nm technologies design and CAD challenges ", Design Automation Conference (DAC), Anaheim, CA, June 2005, pp. 2 4. [5] S.W. Fu, A.M. Mohsen, T.C. May, Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-well protection barrier on VLSI memories, IEEE Trans. Electron Devices, vol. ED-32, no. 1, Jan. 1985. pp. 4954. [6] M. Takai, T. Kishimoto, Y. Ohno, H. Sayama, K. Sonoda, S. Satoh, T. Nishimura, H. Miyoshi, A. Kinomura, Y. Horino, K. Fujii,Soft error susceptibility and immune structures in dynamic random access memories (DRAMs) investigated by nuclear microprobes, IEEE Trans. Nucl. Sci., vol. 43, no. 2, Feb. 1996, pp. 696704. [7] A. Mahmood, E.J. McCluskey, Concurrent Error Detection Using Watchdog Processors A Survey, IEEE Trans. on Computers, Feb. 1988, pp. 160 -174. [8] A.J. Drake, A. KleinOsowski, A.K. Martin, "A Self- Correcting Soft Error Tolerant Flop-Flop", 12th NASA Symposium on VLSI Design, Coeur dAlene, Idaho, USA, Oct. 4-5, 2005. [9] R. Naseer, J. Draper, "The DF-DICE Storage Element for Immunity to Soft Errors", Proceedings of the 48th IEEE International Midwest Symposium on Circuits and Systems, August 2005. [10] D.R. Blum, M.J. Myjak, J.G. Delgado-Frias, Enhanced Fault- Tolerant Data Latches for Deep Submicron CMOS, The 2005 International Conference on Computer Design (ICCD), pp. 28-34, Las Vegas, June 2005. [11] K.J. Hass, J.W. Gambles, B. Walker, M. Zampaglione, Mitigating single event upsets from combinational logic, 7th NASA Symposium on VLSI design, 1998. [12] C.L. Chen, M.Y. Hsiao, Error correcting codes for semiconductor memory applications: A state-of-the-art review, IBM J. Res. Develop., vol. 28, no. 2, pp. 124134, Mar. 1984. [13] P. Hazucha, C. Svensson: "Impact of CMOS technology scaling on the atmospheric neutron soft error rate", IEEE Trans. On Nuclear Sc. Vol. 47, n. 6, Dec. 2000, pp. 2586-2594. [14] Q. Zhou, K. Mohanram, "Gate sizing to radiation harden combinational logic", IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems (TCAD), vol.25, Jan. 2006, pp. 155-166. [15] T. Calin, N. Nicolaidis, R. Velazo, "Upset Hardened Memory Design for Submicron CMOS Technology", IEEE Trans. On Nuclear Sc. Vol. 43, n. 6, Dec. 1996, pp. 2874-2878. [16] M.P. Baze, S.P. Buchner, D. McMorrow, "A Digital CMOS Design Technique for SEU Hardening", IEEE Trans. On Nuclear Sc. Vol. 47, n. 6, Dec. 2000, pp. 2603-2608. [17] A. Ejlali, B.M. Al-Hashimi, M.T. Schmitz, P. Rosinger, S.G. Miremadi, "Combined time and information redundancy for SEUtolerancein energyefficient real-time systems", IEEE Trans. on Very Large Scale Integration Systems, Vol. 14, April 2006, Issue: 4, pp. 323-335. [18] W. Zhao, Y. Cao, "New generation of Predictive Technology Model for sub-45nm design exploration," ISQED, San Jose, CA, March 2006, pp. 585590. [19] S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K.S. Kim, "Robust system design with built-in soft-error resilience," Computer, vol. 38, no. 2, pp. 4352, 2005. [20] M. Pedram, J. Rabaey, "Power Aware Design Methodologies", Norwell, MA: Klouwer, 2002. 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07) 0-7695-2855-4/07 $20.00 2007 [21] M. Fazeli, A. Patooghy, S.G. Miremadi, A. Ejlali," Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies", 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07)

2.50E-04 2.00E-04 1.50E-04 1.00E-04 5.00E-05 0.00E+00 New latch TMR Series1

Figure 11.Power comparison with new proposed latch and TMR latch.

5. Conclusions
In this paper a novel SEU-tolerant latch was designed and evaluated. In the proposed latch, redundant feedback lines were used to mask the effects of SEUs.To investigate the efficiency of the proposed design, some important SEUtolerant latches and our proposed latch were analyzed and SEU injection experiments were carried out by the means of HSPICE tool. Experimental results showed that the proposed latch can tolerate the effects of SEU in all of the critical nodes. Also it was shown that there are some critical nodes in the previous proposed latches that were still vulnerable to SEUs. To demonstrate the power dissipation, performance and area overheads of the proposed design, simulations for 250nm, technologies was performed and compared with TMR which is the effective method to completely tolerate the SEU effects. According to the results, the proposed latch consumes 25% less power and occupies 29% less area as compared with the TMR-latch regardless the technology size, while its reliability is almost the same as TMR-latch.

Also simulation results show proposed latch dose not include any speed degradation respect to latch presented in [21] and in occurrence on any faults the new latch maintained output node in previous data and tolerates against faults whereas the latch presented in [21] is sensitive to faults.