dedicated to designers
accumulative antenna effect.Another way of preventing is adding reverse Diodes at the gates
4. We have multiple instances in RTL(Register Transfer Language), do you doanything special during synthesis stage?
While writing RTL(Register Transfer language),say in verilog or in VHDL language, wedont write the same module functionality again and again, we use a concept called asinstantiation, where in as per the language, the instanciation of a module will behave likethe parent module in terms of functionality, where during synthesis stage we need the fullcode so that the synthesis tool can study the logic , structure and map it to the library cells,so we use a command in synthesis , called as "UNIQUIFY" which will replace theinstantiations with the real logic, because once we are in a synthesis stages we have tovisualize as real cells and no more modelling just for functionality alone, we need tovisualize in-terms of physical world as well.
5. what is tie-high and tie-low cells and where it is used
Tie-high and Tie-Low cells are used to connect the gate of the transistor to either poweror ground. In deep sub micron processes, if the gate is connected to power/ground thetransistor might be turned on/off due to power or ground bounce. The suggestion fromfoundry is to use tie cells for this purpose. These cells are part of standard-cell library.The cells which require Vdd, comes and connect to Tie high...(so tie high is a powersupply cell)...while the cells which wants Vss connects itself to Tie-low.
6. what is the difference between latches and flip-flops based designs
Latches are level-sensitive and flip-flops are edge sensitive. latch based design and flopbased design is that latch allowes time borrowing which a tradition flop does not. Thatmakes latch based design more efficient. But at the same time, latch based design is morecomplicated and has moreissues in min timing (races). Its STA with time borrowing in deep pipelining can be quitecomplex.
7. What is High-Vt and Low-Vt cells.
Hvt cells are MOS devices with less leakage due to high Vt but they have higher delaythan low VT, where as the low Vt cells are devices which have less delay but leakage ishigh. The thereshold(t) vloltage dictates the transistor switching speed , it matters howmuch minimum threshold voltage applied can make the transistor switching to activestate which results to how fast we can switch the trasistor. disadvantage is it needs to