MicroBlaze Instruction Set Overview

ECE 3534 Part 1

The Facts
MicroBlaze
Soft-core Processor Highly Congurable 32-bit Architecture Master Component for Creating a MicroController
Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline

Overview

The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx eld programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core.
Instruction-side bus interface Data-side bus interface
DOPB

Organization
ALU
D-Cache

IOPB

I-Cache

Program Counter

IXCL_M IXCL_S

Special Purpose Registers

Shift Barrel Shift Multiplier Divider

DXCL_M DXCL_S

Bus IF
ILMB

FPU Instruction Buffer Instruction Decode Register File 32 X 32b

Bus IF

DLMB

MFSL 0..7 SFSL 0..7

Optional MicroBlaze feature

Figure 1-1: MicroBlaze Core Block Diagram

Features
The MicroBlaze embedded soft core is highly congurable, allowing users to select a specic set of features required by their design. The processors xed feature set includes

Major Components
Harvard Architecture Bus Interfaces Registers General Purpose Special Function ALU Instruction Processing
Optional MicroBlaze feature
IOPB
R

Chapter 2: MicroBlaze Signal Interface Description

Instruction-side bus interface

Data-side bus interface

DOPB

ALU

D-Cache

I-Cache

Program Counter

IXCL_M IXCL_S

Special Purpose Registers

Shift Barrel Shift Multiplier Divider

DXCL_M DXCL_S

Bus IF
ILMB

FPU Instruction Buffer Instruction Decode Register File 32 X 32b

Bus IF

DLMB

MFSL 0..7 SFSL 0..7

Figure 2-1: MicroBlaze Core Block Diagram

Table 2-1:

Summary of MicroBlaze Core I/O Interface DOPB DOPB DOPB DOPB DOPB DOPB I/O O O O O O O Description Data interface OPB address bus Data interface OPB byte enables Data interface OPB bus lock Data interface OPB write data bus Data interface OPB bus request Data interface OPB read, not write

Signal DM_ABus[0:31] DM_BE[0:3] DM_busLock DM_DBus[0:31] DM_request DM_RNW

Harvard Architecture

See Harvard Architecture

Princeton Architecture

Microcontroller Attributes (1/3)

Attribute Instruction / data ports Data memory read/ write operations External input/ output Option 1 Option 2

Separate (Harvard) Unied (Princeton) Only by load/store instructions (RISC) Use load/store instructions (memory-mapped) Any instruction can read/write memory (CISC) Special I/O instructions

See Harvard Architecture See RISC and CISC See Memory Mapped I/O

Microcontroller Attributes (2/3)

Attribute Option 1 Classic 3-stage (fetch/ decode/execute) Option 2 Classic 5-stage (fetch/ decode/execute/ access/writeback) 32-bit Word-addressable

Pipeline depth Word size (instructions, integers, addresses) Memory organization

16-bit Byte-addressable

See Pipeline See Word Size See Byte Addressable

Microcontroller Attributes (3/3)

Attribute Byte order within words # of instruction operands Addressing modes
See Endianness See Addressing Modes
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Option 1 Big-endian Two operand (rD rD op rS) Few (RISC)

Option 2 Little-endian Three operand (rD rA op rB) Many (CISC)

Overview

Simplied MicroBlaze Architecture

Instruction-side bus interface Data-side bus interface
DOPB IOPB

The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx eld programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core.

ALU
D-Cache I-Cache

Program Counter

IXCL_M IXCL_S

Special Purpose Registers

Shift Barrel Shift Multiplier Divider

DXCL_M DXCL_S

Bus IF
ILMB

FPU Instruction Buffer Instruction Decode Register File 32 X 32b

Bus IF

DLMB

MFSL 0..7 SFSL 0..7

Optional MicroBlaze feature

Which 1-1: the preceding processor Figure of MicroBlaze Core Block Diagram attributes may be inferred from this block Features The MicroBlaze embedded soft core is highly congurable, allowing users to select a diagram? 10 specic set of features required by their design. The processors xed feature set includes

croBlaze Architecture

iew

The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx eld programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core.
Instruction-side bus interface Data-side bus interface
DOPB

Simplied MicroBlaze Architecture

ALU
D-Cache

IOPB

Program Counter

_M

Special Purpose Registers

Shift Barrel Shift Multiplier Divider

DXCL_M DXCL_S

Harvard Architecture RISC Load/Store Architecture 3 or 5 Stage Pipeline (currently 5) 32-bit Datapaths Byte Addressable Big Endian Two Addressing Modes 2 or 3 Operand Instructions
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I-Cache

_S

Bus IF
ILMB

FPU Instruction Buffer Instruction Decode Register File 32 X 32b

Bus IF

DLMB

MFSL 0..7 SFSL 0..7

Optional MicroBlaze feature

Figure 1-1: MicroBlaze Core Block Diagram

Features

The MicroBlaze embedded soft core is highly congurable, allowing users to select a specic set of features required by their design. The processors xed feature set includes the following: Thirty-two 32-bit general purpose registers 32-bit address bus Single issue pipeline 32-bit instruction word with three operands and two addressing modes

ANSWERS
www.xilinx.com 1-800-255-7778

Processor Reference Guide 3) October 5, 2005

Advanced Processor Attributes

Superscalar Speculative, out-of-order execution Branch prediction Multi-threaded
These techniques improve performance, but increase power consumption For more info, click on the above links and/or take an advanced computer 12 architecture course

MicroBlaze Native Data Types 1/3

32-bit word
Address: Alignment: n n+1 n+2 n+3

(4 bytes)

n should be a multiple of 4 [0...31] [most,,,least]

Bit labeling: Byte signicance:

Example: 0x12345678 Viewed as a 32-bit word at address n 0x12 0x34 0x56 0x78

Big-endian

Viewed as a sequence of 4 bytes starting at address n

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MicroBlaze Native Data Types 2/3

16-bit word
Address: Alignment: n n+1

(2 bytes)

n should be a multiple of 2 [0..15] [most, least]

Bit labeling: Byte signicance:

Example: 0x2468 Viewed as a 16-bit word at address n 0x24 0x68

Big-endian

Viewed as a sequence of 2 bytes starting at address n 14

MicroBlaze Native Data Types 3/3

8-bit word
Address: Alignment: Bit signicance: Bit labeling: Example: 0x13 n none most least [0 7]

(1 byte)

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MicroBlaze Instruction Set

~ 124 instructions
22 integer arithmetic 8 logical 9 shift 36 branch 11 oating point 12 load/store 4 return 22 other
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2 addressing modes Type A

Up to 2 source registers 1 destination register

Type B
1 source register 1 immediate operand
16-bit or 32-bit

constant
1 destination register

Type A Instructions
Opcode Bit: 0 6 Destination reg Source reg A 11 16 Example: Add contents of r24 and r27, and store the sum in register r25 Assembly language: add r25, r24, r27 Machine code: 000000 11001 11000 11011 0 0 0 0 0 0 0 0 0 0 0 Source reg B 21 0 0 0 0 0 0 0 0 0 0 0 31

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Does Not Add Up

6-bit opcode => 64 instructions How are the other 60 instructions distinguished?

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Dealing Efciently with Constants

Occurrence

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10
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Questions
1. Why is it important for an embedded processor to deal efciently with constants? 2. How should we optimize using 0? 3. Should we make a special case of n-bit constants, where n < 32? 4. What if we need a 32-bit constant?
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