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Table Of Contents

1. Overview
1.1 Introduction to UVM
1.1.1 Coverage-Driven Verification (CDV)
1.1.2 Testbenches and Environments
1.2 Verification Component Overview
1.2.1 Data Item (Transaction)
1.2.2 Driver (BFM)
1.2.3 Sequencer
1.2.4 Monitor
1.2.6 Environment
1.3 The UVM Class Library
1.4 Other UVM Facilities
1.4.1 UVM Factory
1.4.2 Transaction-Level Modeling (TLM)
2. Transaction-Level Modeling (TLM)
2.2 TLM, TLM-1, and TLM-2.0
2.2.1 TLM-1 Implementation
2.2.2 TLM-2.0 Implementation
2.3.1 Transactions
2.3.2 Transaction-Level Communication
2.3.3 Basic TLM Communication
2.3.4 Communicating between Processes
2.3.5 Blocking versus Nonblocking
2.3.6 Connecting Transaction-Level Components
2.3.7 Peer-to-Peer connections
2.3.8 Port/Export Compatibility
2.4 Encapsulation and Hierarchy
2.4.1 Hierarchical Connections
2.4.2 Connection Types
2.5 Analysis Communication
2.5.1 Analysis Ports
2.5.2 Analysis Exports
2.6 Generic Payload
2.6.1 Attributes
2.6.2 Accessors
2.6.3 Extensions
2.7 Core Interfaces and Ports
2.8 Blocking Transport
2.9 Nonblocking Transport
2.12 Use Models
3. Developing Reusable Verification Components
3.1 Modeling Data Items for Generation
3.1.1 Inheritance and Constraint Layering
3.1.2 Defining Control Fields (“Knobs”)
3.2 Transaction-Level Components
3.3 Creating the Driver
3.4 Creating the Sequencer
3.5 Connecting the Driver and Sequencer
3.5.1 Basic Sequencer and Driver Interaction
3.5.2 Querying for the Randomized Item
3.5.3 Fetching Consecutive Randomized Items
3.5.4 Sending Processed Data back to the Sequencer
3.5.5 Using TLM-Based Drivers
3.6 Creating the Monitor
3.7 Instantiating Components
3.8 Creating the Agent
3.8.1 Operating Modes
3.8.2 Connecting Components
3.9 Creating the Environment
3.9.1 The Environment Class
3.9.2 The UVM Configuration Mechanism
3.10 Enabling Scenario Creation
3.10.1 Declaring User-Defined Sequences
3.10.2 Generating Stimulus with Sequences and Sequence Items
3.10.3 Configuring the Sequencer’s Default Sequence
3.10.4 Overriding Sequence Items and Sequences
3.11 Managing End of Test
3.12 Implementing Checks and Coverage
3.12.1 Implementing Checks and Coverage in Classes
3.12.2 Implementing Checks and Coverage in Interfaces
3.12.3 Controlling Checks and Coverage
4. Using Verification Components
4.1 Using a Verification Component
4.2 Testbench Class
4.3 Instantiating Verification Components
4.4 Test Class
4.5 Verification Component Configuration
4.5.1 Verification Component Configurable Parameters
4.5.2 Verification Component Configuration Mechanism
4.5.3 Choosing between uvm_resource_db and uvm_config_db
4.5.4 Using a Configuration Class
4.6 Creating and Selecting a User-Defined Test
4.6.1 Creating the Base Test
4.6.2 Creating Tests from a Test-Family Base Class
4.6.3 Test Selection
4.8.4 Connecting a Virtual Sequencer to Subsequencers
4.9 Checking for DUT Correctness
4.10 Scoreboards
4.10.1 Creating the Scoreboard
4.10.2 Adding Exports to uvm_scoreboard
4.10.3 Requirements of the TLM Implementation
4.10.4 Defining the Action Taken
4.10.5 Adding the Scoreboard to the Environment
4.10.6 Summary
4.11 Implementing a Coverage Model
4.11.1 Selecting a Coverage Method
4.11.2 Implementing a Functional Coverage Model
4.11.3 Enabling and Disabling Coverage
5. Using the Register Layer Classes
5.2.1 Sub-register Access
5.2.2 Mirroring
5.2.3 Memories are not Mirrored
5.3 Access API
5.3.1 read / write
5.4.2 Controlling Coverage Model Construction and Sampling
5.5 Constructing a Register Model
5.5.1 Field Types
5.5.2 Register Types
5.5.3 Register File Types
5.5.4 Memory Types
5.5.5 Block Types
5.5.6 Packaging a Register Model
5.5.7 Maximum Data Size
5.6 Back-door Access
5.6.1 Back-door read/write vs. peek/poke
5.6.2 Hierarchical HDL Paths
5.6.3 VPI-based Back-door Access
5.6.4 User-defined Back-door Access
5.6.5 Back-door Access for Protected Memories
5.6.6 Active Monitoring
5.7 Special Registers
5.7.1 Pre-defined Special Registers
5.7.2 Unmapped Registers and Memories
5.7.3 Aliased Registers
5.7.4 Unimplemented Registers
5.7.5 RO and WO Registers Sharing the Same Address
5.8 Integrating a Register Model in a Verification Environment
5.9 Integrating a Register Model
5.9.1 Transaction Adapter
5.9.2 Integrating Bus Sequencers
5.9.3 Integrating the Register Model with a Bus Monitor
5.10 Randomizing Field Values
5.11 Pre-defined Sequences
6. Advanced Topics
6.1 The uvm_component Base Class
6.2 The Built-In Factory and Overrides
6.2.1 About the Factory
6.2.2 Factory Registration
6.2.3 Component Overrides
6.3 Callbacks
6.3.1 Use Model
6.3.2 Example
6.4 The Sequence Library
6.5 Advanced Sequence Control
6.5.1 Implementing Complex Scenarios
6.5.2 Protocol Layering
6.5.3 Generating the Item or Sequence in Advance
6.5.4 Executing Sequences and Items on other Sequencers
6.6 Command Line Interface (CLI)
6.6.1 Introduction
6.6.2 Getting Started
6.6.3 UVM-aware Command Line Processing
7. UBus Verification Component Example
7.2 UBus Example Architecture
7.3 UBus Top Module
Example: test_lib.sv
7.5 Testbench Environment
7.6 UBus Environment
7.7 UBus Master Agent
7.8 UBus Master Sequencer
7.10 UBus Agent Monitor
7.11 UBus Bus Monitor
7.11.1 Collecting Transfers from the Bus
7.11.2 Number of Transfers
7.11.3 Notifiers Emitted by the UBus Bus Monitor
7.11.4 Checks and Coverage
7.12 UBus Interface
8. UBus Specification
8.1.1 Motivation
8.1.2 Bus Overview
8.2 Bus Description
8.2.1 Bus Signals
8.2.2 Clocking
8.3 Arbitration Phase
8.4 Address Phase
8.4.1 NOP Cycle
8.4.2 Normal Address Phase
8.5 Data Phase
8.5.1 Write Transfer
8.5.2 Error during Write Transfer
8.5.3 Read Transfer
8.5.4 Error during Read Transfer
8.6 How Data is Driven
8.7 Optional Pipelining Scheme
8.7.1 Pipelined Arbitration Phase
8.7.2 Pipelined Address Phase
8.7.3 Pipelined Data Phase
8.8 Example Timing Diagrams
A.1 Creating the Sequencer
A.2 Enabling Scenario Creation
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Uvm Users Guide 1.1

Uvm Users Guide 1.1

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Published by Mani Kiran

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Published by: Mani Kiran on Jun 05, 2012
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