Moore & Mealy Finite State Transducer Automation Implementation with Outputs A Comparative Case Study

Anish Chatterjee Digital Design & Fundamentals Theory of Computer Architecture Prof. Daniel Tylavsky Arizona State University April 2006

Objective
The purpose of this Capstone Design Project was to develop a synchronous machine that uses the transmitted data as input and then produces an output the negative of the input number by performing the twos complement operation on the incoming data. My project determines the application usage of finite state machines specifically in FSM Logic & Hardware applications, more specifically in any digital circuit, an FSM can be built using a programmable logic device, a programmable logic controller, logic gates and flip flops or relays. In order to implicate output based on a given input and/or a state using actions, two FSM Transducer models are constructed; moore & mealy machine to determine the best possible finite state machine implementation. As such the project is designed to gain experience in building a synchronous state machine model using the classical design techniques like state diagrams, state definition tables and Karnaugh maps. At the end of this project, the following guidelines of digital design fundamentals were achieved. Using classical design techniques (i.e. state diagrams, state transition table, and Karnaugh maps) to devise a synchronous sequential machine starting with a functional specification. Making scientific assumptions to complete an incomplete functional specification. Build and debug a synchronous sequential machine. Develop reasonable engineering criteria for comparing different designs. Apply engineering criteria to select the best design.

Designing Two Synchronous Sequential Finite State Machines (Analogous Digital Circuits)
The design implementation was set in motion by constructing two synchronous sequential machines that can perform the necessary twos complementary function. The circuit should have two 1-bit inputs: Data and Sync; and it should also have one 1-bit output for the twos complement of Data. The circuit also has a Clock signal which synchronizes all the basic functional actions within any particular electronic

Fig 1.1 A typical Clock Cycle medium, including flow of data due to changes in signal which is proportionate to time. Our prototype circuit can also become active at either the rising edge, falling edge, or both edges of this associated clock cycle (Fig 1.1). When Sync is 1, the data entered is recognized as a new potential word and the circuit starts the twos complementary function and Sync is made 0 until a new word is to be entered. The twos complementary function is performed such that starting with the LSB and moving toward the MSB, transcribe all zeroes until we reach the first 1; transcribe that 1 then complement every bit after that. The following table implements a few data input and output values which would give the readers a better understanding of testing which was carried out.

Fig 1.2 Data Transmission Table Sync 1 0 0 0 0 0 0 1 0 0 0 0 0 Data 0 0 0 1 1 0 1 1 1 0 0 1 0 Output 0 0 0 1 0 1 0 1 0 1 1 0 1

Then we will copy that 1, and complement all bits more significant than it. The following state diagram (Fig. 1.2) describes a finite state machine with one input X and one output Z. The FSM asserts its output Z when it recognizes the following input bit sequence: "1011". The machine will keep checking for the proper bit sequence and does not reset to the initial state after it has recognized the string. The output will assert only when it is in state S4 (after having seen the sequence 1011). The FSM is thus a Moore machine. .

S0 (A) S1 (B) S1 (B) S2 (C) S2 (C) S3 (D) S3 (D) S4 (E)

..1 ..10 ..101 ..1011

First Design - Principles and Description:

The goal of FSMs is to describe a circuit with inputs and outputs. We modify the FSM, by adding outputs to each state. The first design corresponds to the Moore Machine wherein the FSM uses only entry State S0 (A) S1 (B) Meaning Reset State = Initial State Output= 0 Receive the first input of the data Output = 1 (No previous ones has been received.) Received a second input = 1 - Output = 0 Received continuous 1s Output = 1 (initial zero) Received continuous 0s Output = 0 (initial one) Binary Value 0,0,0 Fig 1.4 Moore State Machine State E is a new state, because the output of 1 must be associated with some state.

0,0,1 Moore Programmatic Representation 0,1,0 0,1,1 1,0,0 A programmatic representation of Moore machine implementation of the sequence detector module is as follows Module Seqdetect1 Title 'Moore Machine Sequence Detector' Declarations "input and output signals" X, CLOCK, RST PIN; Z PIN istype 'com'; Q2, Q1, Q0 PIN istype 'reg'; "State register declarations

S2 (C) S3 (D) S4 (E)

Fig 1.3 Binary State Transition Table actions, i.e. when you transition into the state, the output corresponding to the state is only produced. The first step in building this circuit was making some basic assumptions that are needed to make the problem easier. In order to perform the twos complement we will use a simplified method to make the twos complement. Starting with the least significant bit, copy all bits until we reach the first 1.

SREG = [Q2,Q1,Q0]; S0 = [0,0,0]; S1 = [0,0,1]; S2 = [0,1,0]; S3 = [0,1,1]; S4 = [1,0,0]; "State machine clock signal Equations" [Q2,Q1,Q0].AR = RST; [Q2,Q1,Q0].CLK = CLOCK; "Define state diagram STATE_DIAGRAM SREG STATE S0: Z=0; IF X THEN S1 ELSE S0; STATE S1: Z=0; IF X THEN S1 ELSE S2; STATE S2: Z=0; IF X THEN S3 ELSE S0; STATE S3: Z=0; IF X THEN S4 ELSE S2; STATE S4: Z=1; IF X THEN S1 ELSE S2; end Seqdetect1

Present State S0 S0 S0 S0 S1 S1 S1 S1 S2 S2 S2 S2 S3 S3 S3 S3

Next State S0 S0 S3 S1 S1 S2 S3 S1 S1 S2 S3 S1 S3 S1 S3 S1

QB

QA

QB+

QA+

JB

KB

JA

KA

Output

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0

0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1

0 0 1 0 0 1 1 0 X X X X X X X X

X X X X X X X X 1 0 0 1 0 1 0 1

0 0 1 1 X X X 1 0 1 1 X X X X X

X X X X 0 1 0 X X X X 0 0 0 0 0

0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0

Fig 1.6 State Transition Table Moore Machine

Karnaugh Maps Moore Machine

Since the Moore Machine is a type of finite state machine built from sequential logic circuits whose output depends not only on the present input but also on the history of the input, it is essential to map out the transition sequence of the finite state machine based on current state and other outputs. Applying Boolean algebra can be awkward at times while simplifying complex expressions. Apart from being laborious (requiring to continuously remember all the laws) the method can lead to solutions which, may appear scientifically minimal, but is extremely nonmaterialistic. To minimize these Boolean expressions, a special arrangement of a truth table known as Karnaugh maps is widely used to group together expressions with common factors which eliminate any unwanted variables . Fig 1.7 K-Maps Moore Machine QB,QA/S,D 00 01 11 10 00 X 0 0 X 01 X 1 0 X 11 X 0 0 X 10 X 0 0 X KA=QBSD

Timing Diagram Moore Machine

The timing diagram for the Moore Machine is easier to comprehend by reading down the columns. The first column says that the machine is in state 00, with output 01. The second column says that the machine is in state 01, with output 11. The reason the second column says that is due to the input, x, read in at the first positive edge. The input x is 1, which caused the FSM to move from state 00 to state 01. Fig 1.5 Timing Diagram Moore Machine

QB,QA/S,D 00 01 11 10

00 0 0 X X

01 0 1 X X

11 0 0 X X

10 1 1 X X

QB,QA/S,D 00 01 11 10

00 0 1 0 0

01 0 1 0 0

11 0 1 0 0

10 0 1 0 0

JB = SD+QASD QB,QA/S,D 00 01 11 10 00 X X 0 1 01 X X 1 0 11 X X 1 1 10 X X 0 0

Output= QBQA

Moore Machine Lab - Results

Finally, the circuit was physically built in the lab to authenticate test results in the presence of the professor in charge of the project along with a teaching assistant. The following results were obtained for the output which was authenticated by the professor proving that the circuit worked without any glitches.
1 0 1 0 Res et

KB=SD+QAD+QASD QB,QA/S,D 00 01 11 10 00 0 X X 1 01 0 X X 0 11 1 X X 1 10 1

Clock S

1 0 D 1 0

X X
+5V +5V DEV1 QB Clock J Q C K R Q Res et S S Clock DEV1 QB J Q C QB' K R Q Res et

JA= S+ QBD The matrix groups which are generated are converted to a Boolean expression by locating and thus transcribing the variable formally attributed to the matrix box by various axiom laws of Boolean algebra.

QB' 0 QB'

Fig 1.8 A diagrammatic circuit representation of the Moore machine using LABView & LogicWorks.

Fig 1.9 Lab Data Results Sync 1 0 0 0 0 0 0 1 0 0 0 0 0 Data 0 0 0 1 1 0 1 1 1 0 0 1 0 Output 0 0 0 1 0 1 0 1 0 1 1 0 1

C has been split into two Moore states, one (C) with output 0, and one (E) with output 1. and does not reset to the initial state. When the machine is in the state D, the output will go high Fig 2.2 Mealy State Transition Diagram

Given below are the transition sequence numbers which the state remembers

Second design - Principles and Design

The second design implemented was the mealy machine. The same assumptions as described for the moore machine were also made and implemented for the mealy machine. As such the FSM uses only input actions i.e. the mealy machine requires one less state than the Moore machine because the output of Moore is only a function of the state unlike the Mealy, which is a function of the state and the input. State S0 S1 S2 S3 Meaning Reset and storing zeros Received first 1s Received second 1s Initial 1 & Output 1 Binary Representation 0, 0 0, 1 1, 0 1, 1

S0 (A) S1 (B) S1 (B) S2 (C) S2 (C) S3 (D)

..1 ..10 ..101

Mealy Programmatic Representation

A programmatic representation of Mealy machine implementation of the sequence detector module is as follows Module Seqdetect2 Title 'Mealy Machine Sequence Detector' Declarations "input and output signals" X, CLOCK, RST PIN; Z PIN istype 'com'; Q1, Q0 PIN istype 'reg'; "State register definitions " and assignments of state values SREG = [Q1,Q0]; S0 = [0,0]; S1 = [0,1]; S2 = [1,0]; S3 = [1,1];

Fig 2.1 Binary State Transition Table The following state diagram describes a finite state machine with one input X and one input Z. The FSM asserts its output Z when it recognizes the following input bit sequence 1011. The machine will keep checking for the bit sequence after the arrival of a "1" at the input. On comparing both the state diagrams it is clearly noticed that state E of the Moore machine is equivalent to state C in the Mealy diagram; Mealy state

State machine clock signal Equations [Q1,Q0].AR = RST; [Q1,Q0].CLK = CLOCK;

Inp

Fig 2.4 Mealy State Transition Table

Pre Sta Nxt Sta Present State Next State Q+B 0 0 0 0 0 1 0 0 1 1 0 0 Q+ A 0 1 0 1 1 0 0 1 0 0 0 1 Out

"Define state diagram STATE_DIAGRAM SREG STATE S0: IF X THEN S1 ELSE S0; STATE S1: IF X THEN S1 ELSE S2; STATE S2: IF X THEN S3 ELSE S0; STATE S3: IF X THEN S1 WITH Z=1; ELSE S2; end Seqdetect2
S 0 0 1 1 0 D 0 1 0 1 0 1 0 1 0 1 0 1

QB S0 S0 S0 S0 S1 S1 S1 S1 S2 S2 S2 S2 S0 S1 S0 S1 S1 S2 S0 S1 S2 S2 S0 S1 0 0 0 0 0 0 0 0 1 1 1 1

QA 0 0 0 0 1 1 1 1 0 0 0 0

JB 0 0 0 0 0 1 0 0 X X X X

KB X X X X X X X X 1 0 1 1

JA 0 1 0 1 X X X X 1 0 0 1

KA X X X X 0 1 1 0 X X X X 0 1 0 1 1 0 0 1 1 0 0 1

Mealy Timing Diagram

0

Initially, we're in state 00, with an output of 0. Unlike the Moore machine, a Mealy machine's output doesn't depend on the current state. From the (Fig 2.1) we notice that in state 00, we see an input of a 1. This takes us to state 01, with an output of 1. Reading the second column of numbers, we see 0 and a 1 (which is state 01, q1q0), followed by a 1 (which is the output z).

1 1 0 0 1 1

Next, the state transition table for the mealy machine was obtained to check for the input & output differences based on the state transitions. Fig 2.3 Mealy Timing Sequence

Karnaugh Maps Mealy Machine

The implementation of K-Maps for mealy machine is exactly the same as the moore machine. As such four variable minterm karnaugh maps are obtained based on permutations of the state and input. In some instances, "Don't care" possibilities (represented by a "X") are grouped only when the group created is larger than the group with "Don't care" is excluded. All "1s" or desired output possibilities are formally grouped to provide a sum-of-products in the Boolean expression. The state transition table for the same (Fig 2.2) gives us the various dimensional values that can be used to built the maps.

Fig 2.5 K-Maps Mealy Machine

QB,QA/S,D 00 01 11 10

00 0 0 X X

01 0 1 X X

11 0 0 X X

10 0 0 X X

QB,QA/S,D 00 01 11 10

00 0 1 X 1

01 1 0 X 0

11 1 1 X 1

10 0 0 X 0

Output= SD+QASD+QBSD+QBQAD JB= QA+S+D Fig 2.6 A diagrammatic circuit representation of the Moore machine using LABView & LogicWorks.

QB,QA/S,D 00 01 11 10

00 0 X X 1

01 1 X X 0

11 1 X X 1

10 0 X X 0
QB S S D A

+5V D S Clock D S S J Q C K R Q D Res et D Clock S

+5V

S J Q C K R Q Res et

QB

KB=S+D

D S

S D +5V 0 D Clock D Res et QB A Res et Clock S Q

QB,QA/S,D 00 01 11 10

00 X X X 1

01 X X X 0

11 X X X 1

10 X X X
QB

1 0 1 0 1 0 1 0

S D S QA

CR Q

1
D

JA=SD+QBSD+QBQAD

Finally, the circuit was physically built (along with the moore machine) in the lab to authenticate test results in the presence of the professor in charge of the project along with a teaching assistant. The following results were obtained for the output which was authenticated by the professor proving that the circuit worked without any glitches. . Sync 1 0 0 0 0 0 0 1 0 0 0 0 0 Data 0 0 0 1 1 0 1 1 1 0 0 1 0 Output 0 0 0 1 0 1 0 1 0 1 1 0 1

quality. While a moore model is often very easy to code, the transition may be often implemented just by constants as initialized tables. The mealy model on the other hand becomes very complex due to the amount of coding required to build the adjoining state machine. Although the Mealy machine results in the reduction of the number of states, my design logic and hypothesized experiments have led me to prefer the moore machine for hardware applications.

Conclusion:
Even though I prefer the mealy machine based on the justifications stated, it is noticeable that both the state machines are arbitrarily equivalent. A mealy state machines output depends on both input and state, so if we ignore the state, we should be able to convert a Moore machine to a Mealy machine. Hence, if both machines are fed the same sequence of inputs, they will both produce the same sequence of outputs. Since Moore machines generate output even if no input has been read in, by ignoring this initial output of the Moore machine we can convert between one machine and the other. On the other hand a Mealy machine can be converted to a Moore machine by increasing the number of states. For e.g. If we have a Mealy machine with N states, and there are k bits of input, we would need up to 2kN states in the equivalent Moore machine.

Fig 2.7 Mealy Test Results - Lab

Justification & Design Selection Criteria:

On an engineering basis for picking up the design the Moore machine would be the best option to choose. The criteria for choosing the most efficient and thus the better design would be the number of components used and the amount of the wiring while constructing the required physical hardware application. The Moore machine requires a much more simplified architecture which would result in the combination fewer circuit modifications. Since the physical hardware application needs to be tested to check the hypothesized outputs, the less number of physical apparatus (wires, pins, ICs) used, the more it is easier to find and solve any mistakes. The Moore circuits require less number of states which means less confusion during construction of the circuit. Since the Moore Machine has pre defined states which mean no confusion what a particular output would be for a particular state. It also does not require the additional D flip-flop which the Mealy machine requires. If the specified state machine is to be coded the model used has enormous influence on the program

Acknowledgements
This work and its contents were supported in part by Prof. Daniel Tylavsky, Associate Prof. Basam Matar and several other senior teaching assistants from the department of computer and electrical engineering in the IRA Fulton School of Engineering Studies I am also gratefully thankful to several librarians in the Nobel Science Engineering Library for providing me aid in my research throughout this capstone project.

References
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