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Capstone ResearchProject Moore Mealy Machine

Capstone ResearchProject Moore Mealy Machine

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Published by Anish Chatterjee

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Published by: Anish Chatterjee on Jun 09, 2012
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Moore & Mealy Finite State Transducer Automation Implementation withOutputs – A Comparative Case Study
Anish ChatterjeeDigital Design & Fundamentals – Theory of Computer ArchitectureProf. Daniel TylavskyArizona State UniversityApril 2006Objective
The purpose of this Capstone Design Project was todevelop a synchronous machine that uses thetransmitted data as input and then produces an outputthe negative of the input number by performing thetwo’s complement operation on the incoming data.My project determines the application usage of finitestate machines specifically in FSM Logic &Hardware applications, more specifically in anydigital circuit, an FSM can be built using a programmable logic device, a programmable logiccontroller, logic gates and flip flops or relays. Inorder to implicate output based on a given inputand/or a state using actions, two FSM Transducer models are constructed; moore & mealy machine todetermine the best possible finite state machineimplementation. As such the project is designed togain experience in building a synchronous statemachine model using the classical design techniqueslike state diagrams, state definition tables andKarnaugh maps. At the end of this project, thefollowing guidelines of digital design fundamentalswere achieved.
Using classical design techniques (i.e. statediagrams, state transition table, andKarnaugh maps) to devise a synchronoussequential machine starting with a functionalspecification.
Making scientific assumptions to completean incomplete functional specification.
Build and debug a synchronous sequentialmachine.
Develop reasonable engineering criteria for comparing different designs.
Apply engineering criteria to select the ‘best’design.
Designing Two Synchronous Sequential FiniteState Machines (Analogous Digital Circuits)
The design implementation was set in motion byconstructing two synchronous sequential machines thatcan perform the necessary two’s complementaryfunction. The circuit should have two 1-bit inputs: Dataand Sync; and it should also have one 1-bit output for the two’s complement of Data. The circuit also has aClock signal which synchronizes all the basicfunctional actions within any particular electronicFig 1.1 A typical Clock Cyclemedium, including flow of data due to changes insignal which is proportionate to time. Our prototypecircuit can also become active at either the rising edge,falling edge, or both edges of this associated clock cycle (Fig 1.1).When Sync is 1, the data entered is recognized as a new potential word and the circuit starts the two’scomplementary function and Sync is made 0 until anew word is to be entered. The two’s complementaryfunction is performed such that starting with the LSBand moving toward the MSB, transcribe all zeroes untilwe reach the first ‘1’; transcribe that ‘1’ thencomplement every bit after that.The following table implements a few data input andoutput values which would give the readers a better understanding of testing which was carried out.
Fig 1.2 Data Transmission TableSync Data Output100000010000000011011100100001010101101
First Design - Principles and Description
The goal of FSMs is to describe a circuit with inputsand outputs. We modify the FSM, by adding outputsto each state. The first design corresponds to theMoore Machine wherein the FSM uses only entryFig 1.3 Binary State Transition Tableactions, i.e. when you transition into the state, theoutput corresponding to the state is only produced.The first step in building this circuit was makingsome basic assumptions that are needed to make the problem easier. In order to perform the two’scomplement we will use a simplified method to makethe two’s complement. Starting with the leastsignificant bit, copy all bits until we reach the first 1.Then we will copy that 1, and complement all bits moresignificant than it.The following state diagram (Fig. 1.2) describes a finitestate machine with one input X and one output Z. TheFSM asserts its output Z when it recognizes thefollowing input bit sequence: "1011". The machine willkeep checking for the proper bit sequence and does notreset to the initial state after it has recognized the string.The output will assert only when it is in state S4 (after having seen the sequence 1011). The FSM is thus aMoore machine..
0 (A)
→ S
1 (B) ..1
1 (B)
→ S
2 (C) ..10
2 (C)
→ S
3 (D) ..101
3 (D)
→ S
4 (E)
Fig 1.4 Moore State MachineState E is a “new” state, because the output of 1 must be associated with some state.
Moore – Programmatic Representation
A programmatic representation of 
Moore machineimplementation of the sequence detector 
module isas followsModule Seqdetect1Title 'Moore Machine Sequence Detector'Declarations"input and output signals"X, CLOCK, RST PIN;Z PIN istype 'com';Q2, Q1, Q0 PIN istype 'reg';"State register declarationsState Meaning Binary ValueS
0 (A)
Reset State = Initial State – Output= 0 0,0,0S
1 (B)
Receive the first input of the data – Output = 1(No previous one’s has been received.)0,0,1S
2 (C)
Received a second input =1 - Output = 0 0,1,0S
3 (D)
Received continuous 1’s – Output = 1 (initial zero) 0,1,1S
4 (E)
Received continuous 0’s – Output = 0 (initial one) 1,0,0
SREG = [Q2,Q1,Q0];S0 = [0,0,0];S1 = [0,0,1];S2 = [0,1,0];S3 = [0,1,1];S4 = [1,0,0];"State machine clock signal Equations"[Q2,Q1,Q0].AR = RST;[Q2,Q1,Q0].CLK = CLOCK;"Define state diagramSTATE_DIAGRAM SREGSTATE S0: Z=0;IF X THEN S1 ELSE S0;STATE S1: Z=0;IF X THEN S1 ELSE S2;STATE S2: Z=0;IF X THEN S3 ELSE S0;STATE S3: Z=0;IF X THEN S4 ELSE S2;STATE S4: Z=1;IF X THEN S1 ELSE S2;end Seqdetect1
Timing Diagram – Moore Machine
The timing diagram for the Moore Machine is easier tocomprehend by reading down the columns. The firstcolumn says that the machine is in state 00, with output01. The second column says that the machine is in state01, with output 11. The reason the second column saysthat is due to the input, x, read in at the first positiveedge. The input x is 1, which caused the FSM to movefrom state 00 to state 01.Fig 1.5 Timing Diagram – Moore MachineFig 1.6 State Transition Table – Moore Machine
Karnaugh Maps – Moore Machine
Since the Moore Machine is a type of finite statemachine built from sequential logic circuits whoseoutput depends not only on the present input but also onthe history of the input, it is essential to map out thetransition sequence of the finite state machine based oncurrent state and other outputs.Applying Boolean algebra can be awkward at timeswhile simplifying complex expressions. Apart from being laborious (requiring to continuously remember allthe laws) the method can lead to solutions which, mayappear scientifically minimal, but is extremely non-materialistic. To minimize these Boolean expressions, aspecial arrangement of a truth table known as Karnaughmaps is widely used to group together expressions withcommon factors which eliminate any unwanted variables. Fig 1.7 K-Maps Moore Machine
S D PresentState NextStateQB QA QB+ QA+ JB KB JA KA Output00110011001100110101010101010101S0S0S0S0S1S1S1S1S2S2S2S2S3S3S3S3S0S0S3S1S1S2S3S1S1S2S3S1S3S1S3S1000000001111111100001111000011110010011001101010001110111011111100100110XXXXXXXXXXXXXXXX100101010011XXX1011XXXXXXXXX010XXXX000000000111100000000
/S,D 00 01 11 1000 X X X X01 0 1 0 011 0 0 0 010 X X X X

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