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IJERA (WWW.IJERA.COM) International Journal of Engineering Research and Applications
IJERA (WWW.IJERA.COM) International Journal of Engineering Research and Applications

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RAVALI.PENNADA, B.JYOTHI / International Journal of Engineering Research and Applications (IJERA)ISSN: 2248-9622 www.ijera.com
 
Vol. 2, Issue 3, May-Jun 2012, pp.1230-1235
 
1230 | Page
Modeling of Switched-Capacitor and Diode-Clamped MultilevelConverter for Induction Motor Application
RAVALI. PENNADA B.JYOTHI
M-Tech Scholar, Power Electronics and Drives, Assistant Professor in Electrical and Electronics EngineeringDepartment Of Electrical And Electronics Engineering, Department Of Electrical And Electronics Engineering,Koneru Lakshmaiah University, Guntur,(A.P), Koneru Lakshmaiah University, Guntur,(A.P),India. India.
 Abstract 
-
 
The concept of multilevel inverters,introduced about 20 years ago entails performing powerconversion in multiple voltage steps to obtain improvedpower quality, lower switching losses, betterelectromagnetic compatibility, and higher voltagecapability. The benefits are especially clear for medium-voltage drives in industrial applications and are beingconsidered for future naval ship propulsion systems.
Thenovel multilevel circuit topologies are proposed in this paper.They are called multilevel circuit topologies based on switched-capacitor and diode-clamped converters (MCT-BSD). Thetopology structure and the operation principle, including the
working states’ transitions of the diode
-clamped part, thevoltages balancing mechanism of the dc link capacitors, andthe pulse width modulated carrier control strategy are given.The switchedcapacitor circuits contribute not only to balancingthe voltages of capacitors but also to boosting the outputvoltage with a certain input dc voltage. Finally a three phaseinduction motor is driven thorough the proposed converter.
Keywords-
Induction Motor, Multilevel Inverter,Cascaded H-Bridge
.
 
I.
 
I
NTRODUCTION
With the advancement of power electronics andemergence of new multilevel converter topologies, it ispossible to work at voltage levels beyond the classicsemiconductor limits. The multilevel converters achievehigh-voltage switching by means of a series of voltagesteps, each of which lies within the ratings of the individualpower devices. Among the multilevel Converters [1-4], thecascaded H-bridge topology (CHB) is particularly attractivein high-voltage applications, because it requires the leastnumber of components to synthesize the same number of voltage levels.Additionally, due to its modular structure, thehardware implementation is rather simple and themaintenance operation is easier than alternative multilevelconverters. The multilevel voltage source inverter isrecently applied in many industrial applications such as acpower supplies, static VAR compensators, drive systems,etc. One of the significant advantages of multilevelconfiguration is the harmonic reduction in the outputwaveform without increasing switching frequency ordecreasing the inverter power output [5-11]. The outputvoltage waveform of a multilevel inverter is composed of the number of levels of voltages, typically obtained fromcapacitor voltage sources. The so-called multilevel startsfrom three levels. As the number of levels reach infinity, theoutput THD approaches zero.To balance the voltage of dc link series capacitors,three main approaches have been proposed in the publishedpapers: 1) using separate dc sources [9]; 2) adding someauxiliary balancing circuits [10], [11]; 3) improving thecontrol method by selecting redundant switching states [13],[14]. In some proposed auxiliary balancing circuits, SMPSinductors or series-resonance circuits are adopted to transferenergy between unbalanced capacitors [10], [11]. Byauxiliary circuits, the transferred current or power can becontrolled accurately, but the additional feedback controlstrategies are also needed, so the control of these convertersbecomes more complicated, and converters are less reliable.A four-leg NPC inverter based on the flying capacitortopology is presented in [12]. The fourth leg is added to atraditional three-level inverter to balance the capacitors withits redundant states, which is able to substitute any otherlegs in the case of failure. But the detection of the voltagesof capacitors and the directions of currents through thecapacitors are needed. For a higher level converter, thedetections become rather complex. For three-phasemultilevel inverters with the space vector pulse widthmodulation (SVPWM) method [13], [14], some redundantstates can be selected to balance dc link capacitor voltageswithout any auxiliary circuits. However, the SVPWMmethod works only in a low modulation index range, andresults in degradation of output voltage quality. On the otherhand, the control algorithm complexity of the SVPWMmethod is increased dramatically with the increase of levelnumber. For a three-level diode-clamped converter, theunbalance problems are solved well by such aforesaidapproaches, but for higher level ones, more suitableapproaches are still needed.
 
RAVALI.PENNADA, B.JYOTHI / International Journal of Engineering Research and Applications (IJERA)ISSN: 2248-9622 www.ijera.com
 
Vol. 2, Issue 3, May-Jun 2012, pp.1230-1235
 
1231 | Page
The multilevel converter topologies based onswitched capacitor converter and diode-clamped converter(MCT-BSD) are proposed in this paper. The switched-capacitor circuits are adopted to balance the capacitorsunder any load conditions, and they also participate insynthesizing the output voltage level. The diode-clampedcircuits play the same role as those of the conventionaldiode-clamped multilevel converter. The proposed topologycan not only balance dc link capacitor voltages, but alsoboost the output voltages with kinds of boosting modes.Furthermore, the number of dc link capacitors is two lessthan those of the conventional diode-clamped multilevelconverter. The validity of the MCT-BSD is verified bysimulations on a five-level inverter. The possibility toextend this structure to four, seven, or higher levelconverters is further discussed.
Finally a three phaseinduction motor is driven thorough the proposedconverter.
II.
 
H
IGH
P
OWER
C
ONVERTERS
C
LASSIFICATIONS
Figure 1
 
Classification of High power Converters
Fig.1 shows the classification of high power converters. Outof all converters Cascaded bridge configuration is morepopular. Cascaded bridge configuration is again classifiedinto 2 types 1) Cascaded Half Bridge 2) Cascaded FullBridge or Cascaded H-Bridge. In this paper a novelcascaded hybrid H- Bridge topology is proposed for PVapplication
.
 A. Diode-Clamped Multilevel Inverter (DCMI)
The diode-clamped multilevel inverter usescapacitors in series to divide up the dc bus voltage into a setof voltage levels. To produce m levels of the phase voltage,an m-level diode-clamp inverter needs m-1 capacitors onthe dc bus. A single-phase five-level diode-clampedinverter, which can produce a nine-level phase to phasevoltage waveform, is shown in Fig. 2.Figure 2 A single-phase five-level diode-clamped inverter.The dc bus consists of four capacitors, i.e., C
1
, C
2
, C
3
, andC
4
. For a dc bus voltage V
dc
, the voltage across eachcapacitor is V
dc
 /4, and each device voltage stress will belimited to one capacitor voltage level, V
dc
 /4, throughclamping diodes. DCMI output voltage synthesis isrelatively straightforward. To explain how the staircasevoltage is synthesized, point O is considered as the outputphase voltage reference point. Using the five-level invertershown in Fig. 2, there are five switch combinations togenerate five level voltages across A and O.
 B. Flying-Capacitor Multilevel Inverter (FCMI)
Probably the most important multilevel topologyto appear recently is the flying capacitor inverter, orimbricated cells multilevel inverter, proposed by Meynardand Foch. A FCMI shown in Fig. 3 uses a ladder structureof dc side capacitors where the voltage on each capacitordiffers from that of the next capacitor. To generate m-levelstaircase output voltage, m-1 capacitors in the dc bus are
 
RAVALI.PENNADA, B.JYOTHI / International Journal of Engineering Research and Applications (IJERA)ISSN: 2248-9622 www.ijera.com
 
Vol. 2, Issue 3, May-Jun 2012, pp.1230-1235
 
1232 | Page
needed. Each phase-leg has an identical structure. The sizeof the voltage increment between two capacitorsdetermines the size of the voltage levels in the outputwaveform.Figure 3 A single-phase five-level flying-capacitorinverter.Here the switch pair-
capacitor ‗cell‘ is isolated and inserted
within a similar cell
 – 
hence the term imbricated cellsinverter. This inner pair of switches and their associated
capacitor now ‗flies‘
as the outer pair of devices switch. Thecombination of conducting switches and capacitors ensuresthat the voltage across any blocking switch is always welldefined.
C. Cascaded-Inverters with Separated DC Sources
 
The last structure introduced here is a multilevelinverter, which uses cascaded inverters with separate dcsources (SDCSs). The general function of this multilevelinverter is the same as that of the other two previousinverters. The multilevel inverter using cascaded-inverterwith SDCSs synthesizes a desired voltage from severalindependent sources of dc voltages, which may be obtainedfrom batteries, fuel cells, or solar cells. This configurationrecently becomes very popular in ac power supply andadjustable speed drive applications. This new inverter canavoid extra clamping diodes or voltage balancingcapacitors. A single-phase two-cell series configuration of such an inverter is shown in Fig 4.Each SDCS is associated with a single-phase full-bridge inverter. The ac terminal voltages of different levelinverters are connected in series. By different combinationsof the four switches, S
1
-S
4
, each inverter level can generatethree different voltage outputs, +V
dc
, -V
dc
, and zero. The acoutput of each of the different level of full-bridge invertersare connected in series such that the synthesized voltagewaveform is the sum of the inverter outputs. Note that thenumber of output phase voltage levels is defined indifferent way from those of two previous inverters. In thistopology, the number of output phase voltage levels isdefined by m=2s+1, where s is the number of dc sources.Figure 4 Single-phase structure of a two-cell cascadedinverter.
III. DYNAMIC MODEL OF INDUCTIONMOTOR
The induction machine d-q or dynamic equivalent circuit isshown in Fig. 5 and 6. One of the most popular inductionmotor models derived from this equivalent circuit is
Krause‘s model detailed in [5]. According to his model, the
modeling equations in flux linkage form are as follows:
Fig. 6 Dynamic d-axis model
 
Fig. 5 Dynamic q-axis model

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