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XAPP098 November 13, 1998 (Version 1.0)1
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.A brief summary of Spartan slave serial configuration, its protocol and signals, lays the groundwork for a discussion on waysto reduce bitstream storage and processing requirements. A detailed example illustrates how these techniques can be putinto practice. Finally, different formats for configuration data are described along with instructions for their use.
Xilinx Family
Spartan and Spartan
XL families
In today’s markets for electronic products, the designerstrives for the continuous improvement of products.Cheaper components must be used to create more func-tionality with less board space. The low-cost, feature-richSpartan series of FPGAs, consisting of the 5-Volt Spartanfamily and the 3.3-Volt SpartanXL family, plays a major rolein helping the designer achieve these goals. This role isconsiderably enhanced when FPGAs are configured with-out the use of dedicated storage and processing resources.This application note describes a number of techniques forachieving low-cost, efficient serial configuration. Extraroom in on-board RAM or in a hard drive off the board canbe used to store the configuration data. The idle time of acontroller, whose primary purpose lies in executing othertasks, can be used to coordinate the loading of the bit-stream into the Spartan device. Unused register bits acces-sible to the processor can be used for holding control, dataand status bits. As a result, it is possible to configure Spar-tan FPGAs without the use of a PROM. Board space andcomponent costs are saved. Besides these benefits, thereare numerous others, including the following:The Spartan serial configuration
can beintegrated with other initialization activities as part of thecontroller’s general program. This makes board resetand initialization easier to coordinate.As part of the controller’s program, the Spartanconfiguration protocol can be modified with relativeease. This can be useful not only for prototypedevelopment, but also product upgrades. For example,consider the case where, for a product underdevelopment, a new member is added to a daisy chainof existing Spartan devices.The Spartan
can be embedded into theprocessor’s program. Fewer separate code files areeasier to manage.This application note begins with some preliminary back-ground on the serial configuration mode for SpartanFPGAs, including a description of the pertinent signals andtheir respective timing. Next, instructions show how an on-board controller can be used to program Spartan FPGAswithout a dedicated PROM. Finally, information is providedon how to make the Spartan bitstream suitable for handlingby the processor.
Spartan Serial Configuration
There are a number of different modes for configuringSpartan devices, including Slave Serial, Master Serial,JTAG, and Express (for SpartanXL only). Among these, thetwo serial modes, employing the least number of interfacesignals (a minimum of four), are the easiest to implement.In the present application, a controller, writing configurationdata, plays the controlling role of “master”, whereas theSpartan FPGA, receiving the data, serves as a “slave”. Forthese reasons, this application note considers only thecase of slave serial configuration.As many as nine pins on the Spartan device may be usedin Slave Serial Configuration: MODE, DIN, DOUT, CCLK,PROGRAM, INIT, DONE, HDC and LDC. A minimum offour signals, PROGRAM, INIT, DATA and CCLK arerequired. The principal functionsof the nine signals aredescribed inTable1.Refer to theSpartan data sheet for more detailed information.
The Low-Cost, Efficient SerialConfiguration of Spartan FPGAs
XAPP098 November 13, 1998 (Version 1.0)Application Note by Kim Goldblatt
2XAPP098 November 13, 1998 (Version 1.0)
Steps in the Configuration Process
The Slave Serial mode consists of four steps:1. Clearing Configuration Memory2. Initialization3. Configuration4. Start-Up
Let’s have a look at each of these steps so that we mayunderstand how the nine configuration signals worktogether to program a Spartan device. Refer to the Spartandatasheet for more details.
Clearing Configuration Memory 
On power-up, once V
reaches the Power-On-Resetthreshold, the device automatically begins clearing the con-figuration memory. It is also possible to begin the clearingoperation by applying a Low-level pulse to the PROGRAMinput.This line makes
possible at any time duringdevice operation. It is particularly useful when the controllerneeds to initiate Spartan configuration at a specific point inthe power-up sequence.As long as PROGRAM is Low, the device continues tocycle through the clearing step. After each pass throughthe configuration memory, PROGRAM is sampled. If PRO-GRAM is High, then one last clearing pass takes place,which concludes with a Low-to-High transition on INIT.Do not hold PROGRAM LOW for more than 500
s. There-fore, PROGRAM should not be used to delay the configu-ration process for periods of this magnitude. Hold INIT Lowinstead.
Since INIT is an open-drain output, it requires a pull-upresistor to achieve a High level. Now that INIT has goneHigh, the internal memory is completely clear. At this point,the device identifies the selected configuration mode bysampling the level on the mode pins, after which it activatesthe appropriate configuration logic. The device is ready tobegin the configuration step. Note that holding INIT Lowcan be used to delay the entry to the configuration step.To select slave serial mode (which is required for theapproach discussed in this application note) for the Spartanfamily, the MODE pin is tied High; for the SpartanXL family,the M0 and M1 pins are tied High.
After INIT goes High, it is necessary for the controller towait for a period
of 4
s before drivingthe CCLK input with the clock signal that transfers the bit-stream.DIN is the input for serial configuration data. DOUT is usedwhen more than one device is connected in a daisy chain.SeeFigure2for an example. The bitstream, having filledthe first device in the chain, will exit its DOUT line, whichleads to the DIN line of the next device where configurationcontinues. The data exiting DOUT is clocked on the fallingedge of CCLK. The data entering DIN is clocked on the ris-ing edge of CCLK as shown inFigure1. The clock oscilla-tor internal to the device is not used in Slave Serial Mode totransfer data; it is only used during Initialization.
The Start-Up step provides a smooth transition from config-uration to user operation. Three major events occur duringStart-Up: The DONE output goes High, the I/Os go activeand the GSR (Global Set/Reset) Net is released. Start-Uptakes place over a period of four cycles labeled C1, C2, C3and C4. Options in
, the bitstream generation pro-gram in the Xilinx development software, determine whichevent takes place in which cycle. The menu for theseoptions can be located as follows:
Table 1: Signals for Spartan ConfigurationSignal TypeDirectionDescriptionMODE (Spartan)M0, M1 (SpartanXL)
Mode selectInputTo select Slave Serial mode on Spartan devices, tie ModeHigh; on SpartanXL devices, tie both M0 and M1 High.
DataInputWrite configuration data into the Spartan device
DataOutputRead configuration data from the Spartan device
ClockInputSynchronizes data on the rising edge
ControlInputBegin clearing the Spartan configuration memory
StatusOpen-drain outputA transition from Low to High indicates that the Spartan con-figuration memory is clear and ready to receive the bitstream
StatusOpen-drain outputA High indicates that the configuration process is complete
StatusOutputHigh throughout configuration, until the I/Os go active
StatusOutputLow throughout configuration, until the I/Os go active
XAPP098 November 13, 1998 (Version 1.0)31. Open the Design Manager.2. Select Implement from under the
menu.3. Choose the
button.4. Click on
Edit Template
for Configuration.5. Select the
tab. A menu will appear that permitsthe three events to be assigned to different cycles.As an alternative,
options can also be selectedusing
Template Manager
, which is found under the
menu of the Design Manager.The customary default option, known as CCLK_NOSYNC,is the most practical, since DONE goes High in C1, discon-necting the data source; I/Os go active in C2, avoiding con-tention; GSR released in C3, ensuring stable internalconditions. The CCLK is used to measure out the four start-up cycles. This application note only considers the defaultoption.There are two conditions that determine when the Start-Upstep begins: (1) length count match and a (2) full configura-tion memory. The 24-bit length count is part of the bitstreamheader, that, once written to the Spartan device, is stored ina register. (See
“The Anatomy of a Spartan Bitstream” onpage7.) From the time INIT goes High, a counter within thedevice begins counting, incrementing by one for eachCCLK rising edge and comparing the result to the lengthcount. Once the counter’s contents match length count, thefirst condition is met. Meeting the second condition occurswhen all the configuration
for a given Spartan devicehas been loaded into configuration memory.A High on DONE is a result of the Start-Up process. Whilethis transition on DONE indicates the completion of theconfiguration
, the configuration process, as a whole,ends with the last cycle of the Start-Up step, C4. It is impor-tant to provide CCLK rising edges for all four start-upcycles. This amounts to clocking the entire bitstream, fromthe first bits of the header to the last bit of the post-amble.Note that the total number of CCLK cycles required to writethe bitstream equals the length count plus the four start-upcycles.DONE is an optional signal, since the master knows howmany bits of configuration bits need to be written. DONE’sfailure to go High generally indicates a problem with config-uration (i.e. a bit error or incomplete loading of configura-tion data).Like DONE, the HDC and LDC outputs provide status onthe device’s progress to user operation. HDC is High duringconfiguration and takes on whatever I/O function isassigned to it at the time when all I/Os go active, in theStart-up step. Similarly, LDC is Low during configurationand takes on its respective I/O function when the I/Os goactive as well.
The Controller Interface
By following three simple techniques, it is possible to imple-ment serial configuration without adding any dedicatedlogic to a design.1. Store the Spartan configuration data either in unused on-board memory or at an off-board location.2. Use the idle time of an on-board controller for coordinat-ing configuration.3. A free register on-board (e.g., in a CPLD or an I/O port)can be used as a synchronous interface between thecontroller and the Spartan device.These techniques can also be used independently. Theyare discussed in the sections that follow.
Storing the Spartan Bitstream
Storing the Spartan bitstream in unused
memoryor downloading it from an
source means thatadditional memory components (i.e. PROMs) for storingconfiguration are unnecessary. This saves componentcosts and board space.In the on-board case, a form of nonvolatile memory, suchas ROM, is used to hold the configuration data. Generally,
Bit nBit n + 1Bit nBit n - 1T
Figure 1: Loading and Readback of the Bitstream in Slave Serial Mode

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