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10.1.1.1.4144

10.1.1.1.4144

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Published by: Bainan Chen on Jun 18, 2012
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REPRINT OF IRISH SIGNALS AND SYSTEMS CONFERENCE 2000, DUBLIN, IRELAND, PP. 368-375, JUNE 2000.
Constant Divider Structures of the Form 2
n
±±±±
1
A.Th. Schwarzbacher
1,3,++
, M. Brutscheck 
1,2
, O. Schwingel
1,2
and J.B. Foley
31
Dublin Institute of Technology, Dublin, Ireland
1
Fachhochschule Merseburg, Germany
3
Trinity College, Dublin, Ireland
 Abstract
Constant operations are one of the key elements in digital signal processing (DSP) systems. Theimplementation of such constant operations is usually performed through the use of standardmodules which are not optimised for one particular function. The primary reason for the usethese standard modules is that in commercial projects time to market is always one of the mainobjectives. This paper addresses the particular problem of the implementation of constantdivider structures of the form 2
n
±
1. As will be shown alternative algorithms can havesignificantly improved performance over standard modules.
 Keywords
: Standard Binary Division, Constant Division Algorithm, High-Level CMOS Design.
1 Theoretical Background
This paper was originally inspired by a problem encountered during the implementation of ahigh performance image processing system. In this system a divider by three was required.However, the initial approach of using a standard module revealed an insufficient timingbehaviour of the module. Therefore, alternative implementations were investigated usingvarious division algorithms that have been suggested in the past. In the following sections sixapproaches will be presented before their features in respect to a silicon implementation arediscussed.
1.1 A Constant Division Algorithm by Petry and Srinivasan
The constant division algorithm as proposed by Petry and Srinivasan [1] is an iterativealgorithm, which was developed for division of the form 2
n
±
1. The computation of the quotientcan be described as
 
QhA
iinim
=
=
()
11
2
(1)As illustrated in Figure 1, it is possible to describe (1) as an array of grouped dividend bits.Therefore, the equation can be rewritten as shown in (2). Using this equation only shift andaddition operations are required to solve the quotient
Q
, where
Q
consists of quotient bits
q
i
andthe remainder
 R
.
++
Author to whom correspondence may be directed: Andreas Schwarzbacher, aschwarzbacher@electronics.dit.ieDublin Institute of Technology, Dept. of Electronics and Communication Engineering, Dublin8, Ireland.
 
 
REPRINT OF IRISH SIGNALS AND SYSTEMS CONFERENCE 2000, DUBLIN, IRELAND, PP. 368-375, JUNE 2000.
 Rqqqq ahaahaaah aaaah aaaaah
mmmmmmmmmmmmmm
..*.*.*.*.*
0432 1121223121221 101321 0
++++
 
Figure 1: Iterative Division by 2
n
+1 and 2
n
-1
Equation (1) was analysed and optimised for the task of carrying out the division by three. Itcan be seen from (1) that the use of 
h
= 1 is preferable to perform this division to avoid analternating function. The reason for this is that alternating functions require more area and alsohave a higher power consumption than non-alternating functions [2]. The dividend
 A
isindependent of 
i
and the equation can be simplified to
QA
inim
=
=
2
1
(2)In this equation
n
is equal to two because the divisor is three while
m
only depends on thebitwidth of the dividend
 A
. For a 10 bit wide input bus
m
is equal to 10. Hence, the wholeequation can be rewritten as
=
=
1012
2
ii
 AQ
(3)If a deviation of 1 bit is acceptable, this constant division algorithm, as presented in [2],achieves a higher accuracy as required. An investigation of (3) shows that only four termsinstead of 10 are required. For this reason the maximum deviation can be written as
maximum deviation
=
12256
8
=
bitAs described above a deviation of one bit occurs for a quotient range of 0 to 255. The optimisedformula can be generalised as
)2222(*2
8642 412
=
+++==
 A AQ
ii
(4)In (4) it can be seen that the division by three is reducible to a multiplication by a value whichis a close approximation of 1/3. As illustrated in Figure 2 only shift steps and one additionoperation is required for an implementation.
(9:0)(15:0)(9:0)(11:2)(13:4)
(15:6)
(15:0)(15:8)10-bit AdderInput
 
Output6-bitshifting8-bittrun-cating
 
Figure 2: Implementation of the Optimised Algorithm
 
REPRINT OF IRISH SIGNALS AND SYSTEMS CONFERENCE 2000, DUBLIN, IRELAND, PP. 368-375, JUNE 2000.
1.2 A Residue Number System based Division Architecture for Constant Divisors
The Residue Number System (RNS) [3] can be used for constant divisors of the form 2
n
±
1. Adividend
 A
can be written as follows.
 Aaaaaa
 N
=
12210
....
(5)In (5), the dividend is a positive
 N 
bit number where the number of bits
m= N/n
. The dividend
 A
can be written as a number of 
m
digits where each digit
 A
i
consists of 
n
bits. For a hardwareimplementation it may be necessary to append zero bits to the most significant bits of 
 A
topresent
 N=n*m
as follows.
 AAAAAAAAA
mmmnmnn
= = + + + +
12101122100
2222........
()
(6)Taking
 A=D*Q+R
and replacing
 A
in (6) the equation can now be written as
 
 A D AAAA
nnmnmn
=+ + + +
0012211
222221....
()
(7)Since 2
2n
= 2
n
* 2
n
and 2
n
= (2
n
-1) +1, (7) can be simplified by using 2
n
-1 as shown in (8).
 
 A D A AAAA
iimniimiimniimnmmn
=+ + + + +
====
01112131212
21222....
()
(8)The components of the remainder
 R
and the quotient
Q
can be written as follows.
 
 R A
iimn
=
=
01
21
(9)
QAAAA
iimiimniimnmmn
= + + + +
===
112131212
222....
()
(10)An analysis shows that it is useful to focus on the form 2
n
-1 to avoid the implementation of analternating function. For an implementation the input must be analysed and split into differentbits. This analysis is necessary to calculate
m
.
5
==
n N m
(11)After determining
m
(10) can be written as follows
= = = =
+++=
41424344642
2*2*2*
iiiiiiii
 A A A AQ
(12)As seen in (12), it is not necessary to compute the digit
 A
0
. Only the digits
 A
1
-A
4
 
are required tocompute
Q
. Figure 3 presents the block diagram of the VLSI implementation of the RNSalgorithm. Here, it can be seen that the division by three was reduced to a combination of shiftand add operations. Furthermore, Figure 3 shows that the input bus was split into smaller buseseach containing 2 bits.

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