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a7ca3519-3fa3-455f-a784-528d1bc12a51

a7ca3519-3fa3-455f-a784-528d1bc12a51

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Published by Vineet Roy

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Published by: Vineet Roy on Jun 23, 2012
Copyright:Attribution Non-commercial

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12/21/2012

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Chapter 8 – Pipelining
8.1. (
  
) The operation performed in each step and the operands involved are as givenin the figure below.
FetchDecode,20, 2000AddFetchDecode,3, 50MulFetchDecode,$3A, 50AndFetchDecode,2000, 50AddR1
2020R3
150R4
50R5
2050Clock cycle 1 2 3 4 5 6 7I
2
: MulI
3
: AndI
4
: AddI
1
: AddInstruction
(
¡
)Clock cycle 2 3 4 5Buffer B1 Add instruction(I
¢
)Mul instruction(I
£
)And instruction(I
¤
)Add instruction(I
¥
)Buffer B2 Informationfrom a previousinstructionDecoded I
¢
Sourceoperands:20, 2000Decoded I
£
Sourceoperands:3, 50Decoded I
¤
Sourceoperands:$3A, 50Buffer B3 Informationfrom a previousinstructionInformationfrom a previousinstructionResult of I
¢
:2020Destination
¦
R1Result of I
£
:150Destination
¦
R31
 
8.2. (
  
)
FetchDecode,20, 2000AddFetchDecode,3, 50MulFetchDecode,$3A, 2020AndFetchDecode,2000, 50AddR1
2020R3
150R4
32R5
2050Clock cycle 1 2 3 4 5 6 7MulAndAddAddInstruction$3A, ?
(
¡
) Cycles 2 to 4 are the same as in P8.1, but contents of R1 are not availableuntil cycle 5. In cycle 5, B1 and B2 have the same contents as in cycle 4. B3contains the result of the multiply instruction.8.3. Step D
£
may be abandoned, to be repeated in cycle 5, as shown below. But,instruction I
¢
must remain in buffer B1. For I
¤
to proceed, buffer B1 must becapable of holding two instructions. The decode step for I
¥
has to be delayed asshown, assuming that only one instruction can be decoded at a time.
F
1
E
1
Clock cycle 1 2 3 4 5 6 7I
2
(Add)I
3
I
4
I
1
(Mul)InstructionD
1
W
1
F
2
E
2
D
2
W
2
F
3
E
3
D
3
W
3
F
4
E
4
D
4
W
4
D
2
8
2
 
8.4. If all decode and execute stages can handle two instructions at a time, only in-struction I
£
is delayed, as shown below. In this case, all buffers must be capableof holding information for two instructions. Note that completing instruction I
¤
before I
£
could cause problems. See Section 8.6.1.
F
1
E
1
Clock cycle 1 2 3 4 5 6 7I
2
(Add)I
3
I
4
I
1
(Mul)InstructionD
1
W
1
F
2
E
2
D
2
W
2
F
3
E
3
D
3
W
3
F
4
E
4
D
4
W
4
8.5. Execution proceeds as follows.
F
1
E
1
Clock cycle 1 2 3 4 5 6 7I
2
I
3
I
4
I
1
InstructionD
1
W
1
F
2
E
2
D
2
W
2
E
3
D
3
W
3
F
4
E
4
D
4
W
4
F
3
98
8.6. The instruction immediately preceding the branch should be placed after thebranch.LOOP Instruction 1 LOOP Instruction 1
§¨§©§§©§¨§
Instruction
Instruction
Instruction
Conditional Branch LOOPConditional Branch LOOP Instruction
This reorganization is possible only if the branch instruction does not depend oninstruction
.3

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