Computer Architechture & Organization

By - Aeikansh

Architecture the building blocks

Structure -static arrangement of the parts (plan) Organization - dynamic interaction of these parts and their management (design) Implementation - the design of specific building blocks (construction) Performance evaluation - the behavior study of the system (decorative treatment)

Wolf Radius Bone

Wolf radius bone ca. 25,00030,000 B.C. showing 55 cuts in groups of five, suggesting a rudimentary form of multiplication or division.

(Source: Illustrated London News, October 2, 1937.)

Tally Sticks
Original wooden tally sticks from Westminster, England, ca. 12501275 A.D.

( SSPL/The ImageWorks.)

Chinese Abacus
Representation of 39,017 on a Chinese abacus.

Cylinder Music Box

Victorian Swiss cylinder music box, dated 1862.

(Source: http://www.liveauctioneers.com/auctions/ebay/497199.html.)

Pascals Calculating Machine

Performs basic arithmetic operations (early to mid 1600s). Does not have what may be considered the basic parts of a computer.

(Source: IBM Archives photograph.)

Babbages Difference Engine #1

known automatic calculator.

Working portion of Babbages Difference Engine No. 1, which is the first

( SSPL/The ImageWorks.)

The Jacquard Pattern Weaving Loom

The Jacquard pattern weaving loom (ca. 1804).

(Source: The Deutsche Museum.)

Enigma
Siemens Halkse T-52 Sturgeon (Enigma) cipher machine.

(Photo and copy courtesy John Alexander, G7GCK Leicester, England.)

Colossus
The Colossus (ca. 1944).

(Source: http://www.turing.org.uk/turing/scrapbook/electronic.html.)

The ENIAC

(Time & Life Pictures/Getty Images.)

Moores Law
Computing power doubles every 18 months, for the same price.

UltraSPARC IV+ Layout

Die photo of UltraSPARC IV+, 295 million transistors, 19.7 mm 17.0 mm

(Source: Best Servers of 2004, Kevin Krewell, 1/18/05, Microprocessor, www.MPRonline.com, Reed Electronics Group, ref: h10018.www1.hp.com/.)

The von Neumann Model

The von Neumann model consists of five major components: (1) input unit; (2) output unit; (3) arithmetic logic unit; (4) memory unit; (5) control unit.

The System Bus Model

A refinement of the von Neumann model, the system bus model has a CP (ALU and control), memory, and an input/output unit.

Communication among components is handled by a shared pathway calle the system bus, which is made up of the data bus, the address bus, and the control bus. There is also a power bus, and some architectures may also ha a separate I/O bus.

A Typical Computer System

(Computer case source http://www.baber.com/cases/mpe_md14_silver.htm. Motherboard source ftp://ftp.tyan.com/img_mobo/i_s2895.tif)

The Motherboard
An AMD Opteron 200 based motherboard.

Source: Courtesy Tyan Computer Corp. (USA).

Memory & Storage

AMD Phenom 2 Die

Intel Nehalem (Core i7) Processor Die

Intel Nehalem (Core i7) Processor Wafer

Combinational vs. sequential digital circuits

A simple model of a digital system is a unit with inputs and outputs:

inputs system outputs

Combinational means "memory-less

a digital circuit is combinational if its output values only depend on its input values

Sequential systems have memory

The output values depend on the input values and previous input values

Combinational logic topics

Logic functions, truth tables, and switches NOT, AND, OR, NAND, NOR, XOR, . . .

minimal set

Axioms and theorems of Boolean algebra proofs by re-writing proofs by perfect induction

Gate logic

networks of Boolean functions

time behavior

Canonical forms two-level incompletely specified functions

Simplification Boolean cubes and Karnaugh maps two-level simplification

The Combinational Logic Unit

Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, 1 and 0, 0 and 1, or 5 V. and 0 V. for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. A set of inputs i0 in are presented to the CLU, which produces a set of outputs according to mapping functions f0 fm.

Truth Tables
Developed in 1854 by George Boole further developed by Claude Shannon (Bell Labs) Outputs are computed for all possible input combinations (how many input combinations are there?

Alternate Assignments of Outputs to Switch Settings

Logically identical truth table to the original (see previous slide), if the switches are configured up-side down.

Truth Tables Showing All Possible Functions of Two Binary Variables

The more frequently used functions have names: AND, XOR, OR, NOR, XOR, and NAND. (Always use upper case spelling.)

Logic functions and truth tables

NOT

X
X X Y Z Y

X 0 1 X 0 0 1 1 X 0 0 1 1 Y 0 1 0 1

Y 1 0 Z 0 0 0 1 Z 0 1 1 1

AND X.Y

XY

OR

X+Y

X Y

Y 0 1 0 1

Logic functions and truth tables (ctd)

X NAND X.Y XY Y Z X 0 0 1 1 X 0 0 1 1 Y 0 1 0 1 Y 0 1 0 1 Z 1 1 1 0 Z 1 0 0 0

NOR X+Y

X Y

XOR X Y

X Y

X Y Z 0 0 00 1 11 0 11 1 0

Minimal set of functions

All logic functions can be implemented from NOT, AND, and OR

Can we do it with only 2 of the 3?

Can we implement all logic functions from NOT, NOR, and NAND?
For example, implementing X and Y is the same as implementing not (X nand Y)

In fact, we can do it with only NOR or only NAND

NOT is just a NAND or a NOR with both inputs tied together
X = X nand X X = X nor X

NAND and NOR are "duals", that is, its easy to implement one using the other
X nand Y not ( (not X) nor (not Y) ) X nor Y not ( (not X) nand (not Y) )

From (logic) expressions to gates

More than one way to map expressions to gates e.g., Z = A' B' (C + D) = (A' (B' (C + D)))
T2 T1

use of 3-input gate

A B C D T2 T1

B
C D

What is the optimal gate realization?

We can use the theorems and axioms of Boolean algebra to optimize our designs Design goals vary depending on the technology. For example:

Reduce the number of inputs? (variables, e.g., A, X and their complements, e.g., A are also called literals) Reduce number of gates? Reduce number of levels? More options (e.g., limited fan-in and fan-out)

How do we explore the trade-offs?

CAD tools Logic minimization: Reduce number of gates and complexity Logic optimization: Minimization vs. speed and delay

The Mathematics: Boolean algebra

A Boolean algebra is an algebraic structure that consists of

a set of elements B; B = {0, 1} binary operations { + , }; + is logical OR, is logical AND and a unary operation { ' }; ' is logical NOT such that the following axioms (laws) hold:

1. the set B contains at least two elements, a, b, such that a b 2. closure: a + b is in B a b is in B 3. commutativity: a+b=b+a ab=ba 4. associativity: a + (b + c) = (a + b) + c a (b c) = (a b) c 5. identity: a+0=a a1=a 6. distributivity: a + (b c) = (a + b) (a + c) a (b + c) = (a b) + (a c) 7. complementarity: a + a' = 1 a a' = 0

Logic functions and Boolean algebra

Any logic function that can be expressed as a truth table can be written as an expression in Boolean algebra using the operators: ', +, and
Y 0 1 0 1 XY 0 0 0 1 X 0 0 1 1 Y 0 1 0 1 X' 1 1 0 0 X' Y 0 1 0 0

X 0 0 1 1

X 0 0 1 1

Y 0 1 0 1

X' 1 1 0 0

Y' 1 0 1 0

XY 0 0 0 1

X' Y' 1 0 0 0

( X Y ) + ( X' Y' ) 1 0 ( X Y ) + ( X' Y' ) 0 1

X=Y

X, Y are Boolean algebra variables

Boolean expression that is true when the variables X and Y have the same value and false, otherwise

Useful laws (Axioms) and theorems

Identity
Null
Idempotent Involution Commutativity

a+0=a

a1=a

a+1=1
a+a=a (a) = a

a0=0
aa=a a a' = 0 ab=ba

Complementarity a + a' = 1 a+b=b+a

Associativity
Distributivity Uniting Absorbtion Absorbtion # 2

a + (b + c) = (a + b) + c
a + (b c) = (a + b) (a + c) a b + a b = a a+ab=a (a + b) b = a b

a (b c) = (a b) c
a (b + c) = (a b) + (a c) (a+b) (a + b) = a a (a + b) = a (a b)+ b = a+ b

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deMorgans law and some more useful ones

de Morgan's (a + b + ...)' = a' b' ...

(a b ...)' = a' + b' + ...

generalized de Morgan's: f'(X1,X2,...,Xn,0,1,+,) = f(X1',X2',...,Xn',1,0,,+)

establishes relationship between and + Duality (a+b+c+ )D = (a b c )
(a b c

)D = (a+b+c+..)

Generalized duality {f(X1,X2,...,Xn,0,1,+,) } D = f(X1,X2,...,Xn,1,0,,+) Factoring (a+b) (a+c) = a c + ab (a b)+(a c) = (a+c) (a+b) (a+b) (b+c) (a+c) = (a+b) (a+c)

Consensus a b + b c + a c = a b + a c

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Product-of-sums canonical form

Also known as conjunctive normal form Also known as maxterm expansion

F= 000 010 100 F = (A + B + C) (A + B' + C) (A' + B + C) A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 0 1 0 1 1 1 F' 1 0 1 0 1 0 0 0

F' = (A + B + C') (A + B' + C') (A' + B + C') (A' + B' + C) (A' + B' + C')
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S-o-P, P-o-S, and de Morgans theorem

Sum-of-products
F' = A'B'C' + A'BC' + AB'C'

Apply de Morgan's
(F')' = (A'B'C' + A'BC' + AB'C')' F = (A + B + C) (A + B' + C) (A' + B + C)

Product-of-sums
F' = (A + B + C') (A + B' + C') (A' + B + C') (A' + B' + C) (A' + B' + C')

Apply de Morgan's
(F')' = ( (A + B + C')(A + B' + C')(A' + B + C')(A' + B' + C)(A' + B' + C') )' F = A'B'C + A'BC + AB'C + ABC' + ABC
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Implementations of two-level logic

Sum-of-products AND gates to form product terms (minterms)

OR gate to form sum

F = ABC + AB + BC

Product-of-sums OR gates to form sum terms (maxterms) AND gates to form product

G = (A+B)(B+C)(A+B+C)

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Two-level logic using NAND gates

Step 1: Replace minterm AND gates with NAND gates and place compensating inversion at inputs of OR gate

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Two-level logic using NAND gates (contd)

Step 2: OR gate with inverted inputs is a NAND gate de Morgan's: A' + B' = (A B)'

Two-level NAND-NAND network

inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed

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Two-level logic using NOR gates

Step 1: Replace maxterm OR gates with NOR gates and place compensating inversion at inputs of AND gate

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Two-level logic using NOR gates (contd)

Step 2: AND gate with inverted inputs is a NOR gate de Morgan's: A' B' = (A + B)' Two-level NOR-NOR network inverted inputs are not counted in a typical circuit, inversion is done once and signal distributed

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Multi-level logic

x=ADF + AEF + BDF + BEF + CDF + CEF + G reduced sum-of-products form already simplified

6 x 3-input AND gates + 1 x 7-input OR gate (that may not even exist!)
25 wires (19 literals plus 6 internal wires)

x = (A + B + C) (D + E) F + G

factored form not written as two-level S-o-P

1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires)
A B C D E F G
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Choosing the best realization

Two-level logic: usually has minimal delay

Usually means faster circuits
But with more gates (more transistors) and more wires (larger circuit area); hence requires more power.

Easy to eliminate static hazards (see later) Sometimes requires large fan-ins

Multilevel logic usually requires less gates

Usually means smaller circuits
Less gates, less wires, shorter wires

Harder to eliminate hazards

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Issues with multilevel design

No global definition of an optimal multilevel circuit

Depends on user-defined goals (number of gates, delay etc.) Use of synthesis (starting with a formal description and proceeding to a logic diagram) to meet the design goals

Synthesis requires CAD-tool help

No simple hand methods like Karnaugh maps CAD tools manipulate Boolean expressions with some heurisitics to achieve goals
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The Multiplexer

Multiplexers (aka selectors)

Multiplexers/selectors: general concept 2n data inputs, n control inputs (called "selects"), 1 output

used to connect 2n points to a single point

control signal pattern forms binary index of input connected to output
Z = A' I0 + A I1 A is control I0 , I1 are input Z is output

A 0 1

Z I0 I1

functional form logical form two alternative forms for a 2:1 Mux truth table

I1 0 0 0 0 1 1 1 1

I0 0 0 1 1 0 0 1 1

A 0 1 0 1 0 1 0 1

Z 0 0 1 0 0 1 1 1

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Multiplexers/selectors (cont'd)

2:1 mux: Z = A' I0 + A I1 4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 8:1 mux: Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3 + A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7 In general, Z = (mkIk)

in minterm shorthand form for a 2n:1 Mux

2 n -1 k=0

I0 I1

2:1 mux A

I0 I1 I2 I3

4:1 mux

I0 I1 I2 I3 I4 I5 I6 I7

8:1 mux

A B
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A B C

CSE 370 Winter 2002 - Hazards - 50

Gate level implementation of muxes

2:1 mux

4:1 mux

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Gate-Level Layout of Multiplexer

Multiplexers as general-purpose logic

A 2n:1 multiplexer can implement any function of n variables with the variables used as control inputs and the data inputs tied to 0 or 1

in essence, a lookup table

Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC

1 0 1 0 0 0 1 1 0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0 A B

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Multiplexers as general-purpose logic (contd)

A 2n-1:1 multiplexer can implement any function of n variables with n-1 variables used as control inputs and the data inputs tied to the last variable or its complement

Example:
F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC = A'B'(C') + A'B(C') + AB'(0) + AB(1)

1 0 1 0 0 0 1 1

0 1 2 3 4 8:1 MUX 5 6 7 S2 S1 S0

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

C 0 1 0 1 0 1 0 1

F 1 0 1 0 0 0 1 1

C' C' 0 1

C' C' 0 1

0 1 4:1 MUX 2 3 S1 S0 A B

C
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Implementing the Majority Function with an 8-1 Mux

Principle: Use the mux select to pick out the selected minterms of the function.

Efficiency: Using a 4-1 Mux to Implement the Majority Function

Principle: Use the A and B inputs to select a pair of minterms. The value applied to the MUX input is selected from {0, 1, C, C} to pick the desired behavior of the minterm pair.

The Demultiplexer (DEMUX)

Demultiplexers (aka decoders)

Decoders/demultiplexers: general concept single data input, n control inputs, 2n outputs

control inputs (called selects (S)) represent binary index of output to which the input is connected
data input usually called enable (G)

1:2 Decoder: O0 = G S O1 = G S 2:4 Decoder: O0 = G S1 O1 = G S1 O2 = G S1 O3 = G S1

S0 S0 S0 S0

O0 O1 O2 O3 O4 O5 O6 O7

3:8 Decoder: = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0 = G S2 S1 S0

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Demultiplexers as general-purpose logic (contd)

F1 = A' B C' D + A' B' C D + A B C D F2 = A B C' D + A B C 0 1 F3 = (A' + B' + C' + D')

Enable

2 3 4 5 6 4:16 7 DEC 8 9 10 11 12 13 14 15

A'B'C'D' A'B'C'D A'B'CD' A'B'CD A'BC'D' A'BC'D A'BCD' A'BCD AB'C'D' AB'C'D AB'CD' AB'CD ABC'D' ABC'D ABCD' ABCD

F1

F2

F3

A B C D
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The Demultiplexer is a Decoder with an Enable Input

A 2-to-4 Decoder

Using a 3-to-8 Decoder to Implement the Majority Function

Sequential Logic
The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs.

There is a need for circuits with memory, which behave differently depending upon their previous state.
An example is a vending machine, which must remember how many coins and what kinds of coins have been inserted. The machine should behave according to not only the current coin inserted, but also upon how many coins and what kinds of coins have been inserted previously. These are referred to as finite state machines, because they can have at most a finite number of states.

S-R Flip-Flop
The S-R flip-flop is an active high (positive logic) device.

NAND Implementation of S-R FlipFlop

A NOR implementation of an S-R flip-flop is converted into a NAND implementation.

A Hazard

It is desirable to be able to turn off the flip-flop so it does not respond to such hazards.

Clocked S-R Flip-Flop

The clock signal, CLK, enables the S and R inputs to the flip-flop.

Clocked D Flip-Flop

The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The Master-Slave flip-flop (next slide) addresses this problem.

Clocked T Flip-Flop

The presence of a constant 1 at J and K means that the flip-flop will change its state from 0 to 1 or 1 to 0 each time it is clocked by the T (Toggle) input.

Clocked J-K Flip-Flop

The J-K flip-flop eliminates the disallowed S=R=1 problem of the S-R flipflop, because Q enables J while Q disables K, and vice-versa. However, there is still a problem. If J goes momentarily to 1 and then back to 0 while the flip-flop is active and in the reset state, the flip-flop will catch the 1. This is referred to as 1s catching. The J-K Master-Slave flip-flop (next slide) addresses this problem.

Master-Slave Flip-Flop

The rising edge of the clock loads new data into the master, while the slave continues to hold previous data. The falling edge of the clock loads the new master data into the slave.

Master-Slave J-K Flip-Flop