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SBU ModelSim 6.5 Tutorial (1)

SBU ModelSim 6.5 Tutorial (1)

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Published by Hamid Reza Habibi

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Published by: Hamid Reza Habibi on Jun 24, 2012
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In the name of GodDigital Logic – Shahid Beheshti University – fall semester 2011ModelSim 6.5 Brief Tutorial
Here are some tips for you to get used to Verilog Language andModelSim 6.5 environment.After Installing ModelSim go tocrk folder and run MentorKG thenIf it’s your first time opening ModelSim or if you encounter  problems with licenses, you can run the license wizard:Start > AllPrograms > ModelSim SE > Licensing Wizard. Choose install a new license and select the fileLICENSE.TXTincrk Folder, you must see a congratulation message that you crackedsuccessfully!It’s time to see different parts of modelsim, we’ll go through it step by step with and example of designing a full adder module, I’llexplain important part to you when we encountered them.First you’ll see something like the picture below, start by choosingnew Project, name it fullAdder:
ok, now choosenew file,name it whatever you like, consider tochoose Verilog, the default is VHDL, now you’ll see your file andthe status is ? it means it didn’t compile yet,first of all let’s sharpen our tools by choosing right component inmodelSim, so go to view tab and be sure theLibrary, Objects ,Project , Transcript and Wave are selected.
 Library:A directory that contains compiled design units, such asmodules.Projects:A collection of various files for designs under test, such asVerilog source files, local working libraries, references to resourcelibraries, and simulation configuration (*.mpf files).Objects:is where you can find you variables, input outputs, etc.Wave:Here you can see the input/outputs of your module inwaveform.Transcript:this tool will allow you to execute your commands bytyping (something like command prompt in window)e.g. instead of click a file to compile you can type
vlog –work [working library] [filename.v] Example: vlog –work work fullAdder.

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