SPICECompatible Behavioral PhaseSpace Simulation Techniques for PhaseLocked Systems

Paul Van Halen, Member IEEE

Department Of Electrical Engineering Portland State University P.O. Box 751 Portland, Oregon 97207 Tel. (503)7255395 Fax (503)7253807 email address: vanhalen@ee.pdx.edu

Graeme R. Boyle, Member IEEE

EDA Tool Development Tektronix Inc. P.O. Box 500 Beaverton, Oregon 97077

Abstract In this paper we present nonlinear phasespacevstime simulation techniques for phaselocked systems. Eliminating the two time scale problem, (the disparity between the VCO and loop time constants), results in a two to three order magnitude speed up compared to traditional voltagevstime simulations at the macromodel or transistor level. Building blocks for the phase space simulation approach are developed. Application examples demonstrate the flexibility, accuracy and efficiency of the method.

analysis reduces the simulation time and provides information about the behavior and stability of the system, the inherent system nonlinearities are difficult to model in the frequency domain. The resulting twopronged simulation approach with the nonlinear time domain and the linearized Laplace domain models, and the accompanying potential for inconsistencies, form one more hurdle on the road towards a successful PLL design. In this paper we propose phasespace simulation as a solution to the quest for a consistent, faster, SPICE compatible systems approach to PLL design. In Section II we develop the concept for the phasespace description of the PLL. In Section III these concepts are developed into models. Examples in this section will demonstrate the power of the phasespace simulation technique.

I. INTRODUCTION Phaselocked loops (PLLs), an important part of the class of mixedmode nonlinear dynamic systems, have many applications; they are used in transmitter/receiver systems (modulation/demodulation), clock recovery [1], frequency/clock synthesis [2], etc. The PLL can be difficult to simulate using conventional tools such as SPICE because of the two time scale problem. The first, and fastest, time scale is set by the Voltage Controlled Oscillator (VCO), while the second time scale is set by the time constants associated with the closed loop system formed by the VCO, phase detector (PD), and loop filter. In systems where these time scales differ by orders of magnitude, (the norm rather than the exception), analog simulation times of traditional macro/transistor level voltagevstime simulation techniques tend to become prohibitive rather quickly, particularly in the initial stages of the design cycle where one is concerned with system level operation and functionality. In addition, loop bandwidth and stability are difficult to model in the time domain. While linearized Laplace domain

II. PLL PHASESPACE MODEL DEVELOPMENT Focussing on signals that are of importance in a PLL enables us to develop a SPICE compatible, system level model for PLLs, which will allow us to model both time and frequency domain phenomena without modifying the model, while producing results in a timely fashion. As their name indicates, the information in the signals that drive a PLL is contained not in their voltagevstime behavior, but in the frequency/phase of these signals. Frequency and phase of a signal of course are related through the following expressions df(t) + 2pf (t) dt or f(t) + 2p f (t)dt (1)

where, as indicated the frequency can be timedependent. Equation (1) is the key to the concept of phasespacevstime modeling of the PLL system. Behavioral models for the system components of the PLL, the phase detector (PD) and the voltage controlled oscillator (VCO), will now be developed. The PD produces an output signal which is proportional to the phase difference between its input signals V d + K D(f in * f osc) (2)

block. Integrating one more time produces the output phase which is the second input of the PD. A voltage source V a representing the input signal amplitude, affecting K D according to Eq. (4), and a voltage source V f0 and summing block s1, which account for the VCO free running frequency, complete the block diagram in Fig. 1. The 2p scaling factors in the integrators convert frequency to angular frequency. The first important benefit of this phasespace model is immediate access to all important signals: input and output frequency and phase, and the output voltages of the PD and the loop filter. The phasespace model transform correctly into the Laplace domain. Where the nonlinear, harmonic generating, multiplying properties of voltagevstime models are at best difficult to linearize, the correct (automatic while performing an AC analysis in SPICE) linearization of the phasespace KD model, makes the model useful for bandwidth and loop stability analysis. Since the only voltagevstime signals in the model are the PD and loop filter outputs, with the VCO signals represented as frequency and phasevstime the two time scale problem has been eliminated. As a result simulation time has been reduced significantly. III. MODEL IMPLEMENTATION AND APPLICATIONS All elements discussed so far, integration, scaling, summing and sin(), are easily implemented in SPICE (Spice3, PSpice, etc) at the circuit level using functional controlled sources. Fig. 1 shows a schematic implementation of a complete PLL in phasespace. With a PD conversion gain of 1.27 V/rad, a VCO free running frequency of 100 kHz and a conversion gain of 20.69 kHz/V and loop filter parameters as shown in the diagram, this circuit has been used for various experiments to demonstrate the capabilities of the spacephase approach. Fig. 2 shows the results of a frequency step at the input. The input signal is a piecewiselinear voltage source, starting at a value of 100K, which after 200 ms is stepped up to 104.25K and 108.25K. The outputs of the PD and of the loop filter are shown. For the larger step, the PLL can be observed to unlock and relock. With instantaneous frequency and phase available in the circuit, this transient response is easily transformed into a parametric phase errorvsfrequency plot as shown in Fig. 3. Sweeping the input frequency over a wide range shows the capture characteristics of the PLL. From Fig. 4 the capture range and lock range of the PLL can easily be calculated.

where the PD conversion gain K D can be a function of the amplitude of the input signal. The essential nonlinearity of a PLL system arises from the periodic nature of the PD. Time shifting one of the two input signal over 2p radians produces an identical phase difference, and the PD output will reflect that fact. This 2p periodicity can be extended through well known techniques [3, 4] but the operation remains periodic. In its simplest form this periodic behavior is represented by V d + K D sin(fin * f osc) with K D V 2 K D + p tanh a V ref (4) (3)

The hyperbolic tangent function guarantees the value of K D to saturate to some final value when the amplitude V a exceeds a certain reference V ref, in analogy with the behavior of transistor level PDs. The VCO produces a fixed amplitude output signal with a frequency f o + f free ) K 0V c (5)

where f free represents the free running frequency, K 0 the VCO conversion gain, and V c the VCO input voltage. As illustrated in the diagram in Fig. 1, the input signal to the system represents the input frequencyvstime to the system. Using Eq. (1) this signal is converted to phasevstime. This phase signal, as well as the fedback output phase signal is used in the PD to create the PD output signal. This voltage vstime signal is then filtered with traditional filtering circuitry to produce the filtered voltagevstime signal. The VCO converts its voltage input into a frequency and thus the VCO model is no more than a gain block which scales the voltage input to produce an output voltage which represents the output frequency. Nonlinearities and frequency dependencies of the VCO conversion gain can easily be implemented in this gain

The results of an AC loop analysis are shown in Fig. 5. The ratio of output phase over input phase is the overall gain of the PLL. The ratio of output phase over phase error (the difference between input phase and output phase) is the loop gain of the PLL. For both characteristics the magnitude (dB) and the phase is shown in Fig. 5. All analyses shown in this section required fewer than 5 seconds of computation time on a SPARC 2 workstation. Compared with macro and transistor level voltagevstime simulations, this represents a one to three orders of magnitude savings in analysis time. IV. CONCLUSION In conclusion, the phasespace approach to simulating phaselocked systems eliminates the two time scale problem which plagues the more traditional voltagevstime macro and transistor level SPICEtype simulations of these systems. As a result a 10X to 1000X improvement in analysis speed has been demonstrated, giving the designer an efficient

tool to determine and verify all mission critical PLL characteristics in a familiar SPICE environment. Since the phasespace approach casts the essential PLL nonlinearity in a form which can be linearized correctly, phasespace modeling provides the designer with a unified model for both time and frequency domain analysis. REFERENCES [1] T.H. Lee and J.F. Bulzacchelli, A 155 MHz clock recovery delay and phaselocked loop, IEEE Journal of SolidState Circuits, vol. 27, No. 12, December 1992. [2] L.A. Young et al, A PLL clock generator with 5 to 110 MHz of lock range for microprocessors, IEEE Journal of SolidState Circuits, vol. 27, No. 11, November 1992. [3] D.H. Wolaver, Phaselocked Loop Circuit Design, PrenticeHall, 1991. [4] R. Best, Phaselocked loops, Theory, Design and Applications, 2nd Ed., McGraw Hill, 1993 [5] ADS User Manual, Tektronix T0636000, Jan. 1994.

Fig. 1: Block diagram of the phasespace PLL model. Integration of a voltage representing frequency produces a phase signal, which is converted to a voltage signal in the PD. After filtering this signal is converted back to frequency and, through integration, to output phase.
1

(1a) PD and filter output voltage

(1b) (2a) (2b)

1 0 1m 2m

Time Fig. 2: Input frequency step response. (1a) and (1b) are the PD and filter output voltages respectively for a 4.25 kHz frequency step at the input. The PLL stays locked. (2a) and (2b) are the PD and filter output voltages for a 8.25 kHz step. In this case the PLL unlocks and relocks.

(1)
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Phase error signal

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15

(2)
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25 98k 100k 102k 104k 106k 108k 110k 112k

Frequency Fig. 3: Input frequency step response, shown as phase error versus output frequency. (1) 4.25 kHz input step. (2) 8.25 kHz input step. (the unlocking and relocking is clearly observable)
125k

115k

Output Frequency

105k

95k

85k 80k 90k 100k 110k 120k 130k 140k

Input Frequency Fig. 4: Transient analysis with frequency swept from 80 KHz to 140 KHz, showing the output frequency as a function of the input frequency.
0 80 20 60 40

(2a)

(1b)

60

Magnitude (dB)

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Phase

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80

(1a) (2b)

100

20 120 40 140 1 10 100

1k

10k

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1M

Frequency Fig. 5: (1a) and (1b): Magnitude (dB) and phase respectively of the overall frequency response of the PLL; (2a) and (2b): Magnitude and phase of the loop gain of the system.