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Published by Peram Nagireddy

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Published by: Peram Nagireddy on Jun 27, 2012
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Chapter 7
Olivier Coudert
A physical design flow consists of producing a production-worthy layoutfrom a gate-level netlist subject to a set of constraints. This chapterfocuses on the problems imposed by shrinking process technologies, andtheir solutions in the context of design flows with an emphasis on thecomplex interactions between logic optimization, placement, and rout-ing. The chapter exposes the problems of timing and design closure,signal integrity, design variable dependencies, clock and power/groundrouting, and design signoff. It also surveys logical and physical designflows, and describes a refinement-based flow.
Creating a chip layout worthy of fabrication is achieved through asequence of steps, coined as a
design flow 
. Since the event of logicsynthesis in the mid-80’s, design flows have been characterized by a clearseparation between the logical and the physical domains. Logic synthesisproduces a gate-level netlist from an abstract specification (behavioral,RTL). Place and route produces the layout from the gate-level netlistand technology files. Specific tools have been used to create the clocktree and the power/ground (P/G) routing, and to achieve final signoff.Reconsidering the logical aspects during the physical design phase wasunnecessary, because timing signoff could be done at the gate level, andsignal integrity was rarely an issue.A flow consisting of logic synthesis followed by place-and-route cannotwork with deep submicron (DSM). At 0
and beyond, interconnectbecomes a dominant factor and breaks the dichotomy between the logicaland physical domains. First, we can no longer neglect the impact of the interconnect on timing because interconnect dominates gate delays.1
2Second, increasing design complexity makes managing congestion morechallenging. Third, finer geometry, higher clock frequency, and lowervoltage produce signal integrity problems. Logical and physical aspectsare tied together and can no longer be looked at separately: there isa need for design tools and design flows that enable the simultaneousoptimization of the logical and physical aspects of a design.This chapter discusses logical and physical design from a flow per-spective. Section 7.2 explains why the logical and physical variables areinterdependent, and why they must be considered together during thephysical implementation phase. Section 7.4 first discusses the uncer-tainty/refinement principle, then presents the details of a refinement-based design flow, a promising approach to solve the problems broughtby DSM. The chapter concludes with some thoughts on a full-chip hier-archical design flow.
VLSI physical design is the process of producing a GDSII (a maskdescribing the complete layout that will be fabricated) from a gate-leveldescription while satisfying a set of constraints. The gate-level netlistis a logical description of the circuit in terms of cells (e.g., I/O pads,RAMs, IP blocks, logical gates, flip-flops, etc.) and their interconnec-tions. The constraints include timing (setup, hold, slope, min/max pathdelays, multicycle paths, false paths), area, place keepouts (regions of the die where cells cannot be placed), and route keepouts (regions of thedie through which nets cannot be routed), power consumption, and tech-nology constraints (e.g., maximum output load, electromigration rules).This section presents the challenges that must be addressed by a physicaldesign flow intended for DSM designs.
Timing closure is the problem of achieving the timing constraints of adesign. Until the mid-90’s, most of the delay was in the gates, and the netcapacitance was a relatively small contributor to the total output loadof the gates. Thus the impact of nets on timing could be disregarded.Consequently timing signoff could be done with static timing analysison a gate-level netlist, right after synthesis (Fig. 7.1, left). From there,the netlist could be handed off to physical implementation.As process geometries scale down, interconnect becomes the predom-inant factor in determining the delay. First, the gate delay depends
Logical and Physical Design:A flow Perspective
 Logical Domain
 Netlist signoff 
Timing libraryRoutingExtractionClock treePlacementSynthesisGDSIISystem design
Statistical WLM
Timing libraryRoutingPlacementSynthesisGDSIISystem design
Physical Domain
Clock treeExtraction
Figure 7.1.
Flows until mid-1990’s.
mostly on the output capacitance it drives, of which the net capacitancebecomes the largest contributor. Second, the delay of long nets, whichdepends on their capacitance and resistance, becomes larger than gatedelays.Timing signoff is the process of guaranteeing that the timing con-straints will be met. Post-synthesis signowas possible when inter-connect contributed less than 20% of the total output capacitance. Nowthat net capacitance is becoming more dominant with every new processgeneration, accurate timing estimation without knowing net topologiesand placements is not possible. Since timing cannot be realistically es-timated from a netlist alone, it is not practical to think in terms of apost-synthesis netlist signoff.One could attempt to account for interconnect delays by using a sta-tistical wire load model (WLM) based on pin count. The problem isthat timing is determined by a
path delay, and although sucha wire load model is actually a good predictor of the
wire load,the deviation is so large that timing becomes grossly mispredicted.Moreover, coupling capacitance becomes more dominant over inter-layer capacitance with every new process technology because the wiresare getting much closer to each other and the interconnect aspect ratio of height to width is increasing (Fig. 7.2). In 1999, the coupling capacitance
—the lateral coupling capacitance between interconnects on the samelayer— was about three times larger than the inter-layer capacitance
—the capacitance due to overlapping of interconnect between differentlayers—. The ratio is projected to increase to five in 2006 (Fig. 7.2).This means that the capacitance of a net cannot be determined withoutknowing both its route
that of its neighbors.

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->