1278 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 9, SEPTEMBER 2004
chronous hardware implementation from an operation-centricdescription. The paper provides algorithms for
a hardwired arbitration logic to coordinate the concurrentexecution in an implementation.This paper is organized as follows. Section II
rst presentsthe abstract transition systems (ATS), an simple operation-cen-tric hardware formalism used to develop and explain the syn-thesis procedures. Section III next describes the basic synthesisprocedure to create a reference implementation that is function-ally correct but inef
cient. The inef
ciencies of the referenceimplementation are addressed in Sections IV and V using twooptimizations based on the concurrent execution of
operations, respectively. The re-sulting optimized implementation incorporates a hardwired ar-bitration logic that enables the concurrent execution of con-
ict-free and sequentially composable operations. Section VIpresents a comparison of designs synthesized from an opera-tion-centric description versus an state-centric RTL description.Section VII discusses related work, and Section VIII concludeswith a summary.II. O
We have developed an source-level language called TRSPECto support operation-centric hardware design speci
s syntax and semantics are adaptations of awell-known formalism, TRS . To avoid the complicationsof a source language, instead, we present a low-level opera-tion-centric hardware formalism called ATS. ATS is developedas the intermediate representation in our TRSPEC compiler.In this paper, we use ATS to explain how to synthesize anef
cient implementation from an operation-centric hardwarespeci
A. ATS Overview
ThestructureofATSissummarizedinFig.1.Atthetoplevel,an ATS is de
ned as a triple . is a list of explicitlydeclared state elements, including registers , arrays and
rst-out (FIFO) queues . is a list of initial valuesfor the elements in . is a set of operation-centric transi-tions,whereeachtransitionisapair .Inatransition, isaboolean predicate expression, and is a list of simultaneous ac-tions,exactlyoneactionforeachstateelementin .(Anaccept-able action for all state-element types is the null action
)In an ATS, if of is enabled in a state [abbreviated as, or simply ], then the simultaneous ac-tions prescribed by are applied atomically to update to. We use the notation to mean the resulting state . Inother words, is the functional equivalent of .
B. ATS State Elements and Actions
In this paper, we concentrate on the synthesis of ATS withthree types of state elements: , , and . The three types of state elements are depicted in Fig. 2 with signals of their sup-ported interfaces. Below, we describe the three types of stateelements and their usage.
Fig. 1. ATS summary.Fig. 2. Synchronous state primitives.
A register can store an integer value up to a speci
ed max-imum word size. The value stored in a register can be refer-enced using the side-effect-free query and set to usingthe action (written as and , respectively).An entry of an array can be referenced using the side-effect-freequeryandsetto usingthe action.Forbrevity, we abbreviate as in our examples.The oldest value in a FIFO can be referenced using the side-ef-fect-free query, and can be removed by the action.A new value can be added to a FIFO using the action.The actionisacompoundactionthatconceptually
dequeues the oldest entry before enqueuing a new entry. In ad-dition, the contents of a FIFO can be cleared using theaction. The status of a FIFO can be queried using the side-ef-fect-free and queries. Conceptually, anATS FIFO has a bounded but unspeci
ed size. The exact sizeis only set at implementation time, and hence a speci
cationmust be valid for all possible sizes. Applying an to a fullFIFO or applying to an empty FIFO is illegal. (Applyingaction to a full FIFO is legal however.) Any transi-tion that queries or acts on a FIFO must include the appropriateor queries in its predicate condition.