Chapter 10 Design Submission

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Case Study: AMCC Design Submission (1990) Submission List Continued Submission List Continued Functional Simulation Submission (Required) At-Speed Simulation Submission (Required) AC Tests Path Delay Vector Submission (Optional) Parametric Vectors (Required or Optional) AMCC Simulation Forms - Vocabulary

Design Submission
On the completion of the design verification and simulation for the circuit, the design submission package is assembled. This package must pass through a design acceptance review before the array vendor will accept it. The requirement of design submission is specific - provide the array vendor with sufficient information to be able to evaluate the design, reproduce the simulation on their own internal systems, place and route the circuit, and produce Back-Annotated simulations that meet the customer's requirements. Design submission requirements vary widely in their specific forms and supplemental material. As an added support feature, AMCC created AMCCSUBMIT - a design submission documentation program that prompts for design validation questions and for information required to document submitted simulation files. To better discuss this process, the following is the current AMCC design submission document, referencing AMCCSUMBIT and the validation questions. Regardless of the forms it may take or be required to be in, the same basic information is required for any design submission. Variations occur when the array vendor is contracted to perform some or all of the design process to the customer's specifications.

Case Study: AMCC Design Submission

Submitting a Circuit Design to AMCC (1990)
The following document has been designed to ensure the AMCC customer, of a successful transition from concept to finished part. It is a summary of the items required for the submission of a BiCMOS or bipolar array-based circuit design to AMCC when:

the schematic capture and simulation vector generation has been performed by the customer; the design entry is via a description language or netlist and simulation vector generation has been performed by the customer.

The items described herein must be submitted to AMCC for use in the acceptance design review prior to committing the design to layout. These are the critical information transfers which, if not completed, may delay the acceptance of the circuit. Schematics are to be prepared following AMCC schematic conventions. Refer to the design manual for further information. Sections provide a detailed description of the AMCC rules for both EWS-generated and non-EWS-generated schematics. A design cannot be processed without the required test vectors. Functional simulation and at-speed simulation or timing verification are required prior to releasing a design to layout. Parametric simulation may also be required. AC Tests are optional. For information on the test vector requirements and simulation procedures, refer to Volume II, Section 4, "Vector Submission Rules and Guidelines".

AMCC Array Design Submission With AMCCSUBMIT AMCCSUBMIT must be run and the questions answered. It will produce a summary of the documentation required for a successful design submission. Where information is requested that is not available due to the type of design submission and the contract, indicate why the information is not being supplied.

AMCC Assigned Circuit Name (required identification) AMCC PRODUCT_NAME When AMCC has received a purchase order for a circuit, AMCC assigns a code name (a.k.a circuit name, product name) to protect the proprietary nature of the circuit. This code name should appear on the submission document and on all hardcopy documents as a single point of reference. It should be attached to the schematic chip macro as the PRODUCT_NAME parameter. If no such name assignment exists, use the first 4-6 letters of the company name as the code name ID.

AMCC Assigned DEVICE_NUMBER [may use default] Assigned with the PRODUCT_NAME, the DEVICE_NUMBER serves to identify the individual circuit. It may be defaulted if no number has been assigned.

Array Series and Specific Array Clearly identify which array family and which array within that family is the one used for this design. The selection should match the chip macro identification.

Macro Library Version (required identification) The macro library: release version number is on the label of the release media and on the upper right hand corner of the chip macros. The version used for the drawings and all execution files must be supplied on the submission checklist. Designers should always verify that they have the latest version of a library immediately prior to beginning schematic capture.

MacroMatrix Release Version The MacroMatrix: release number may vary from the library release. Supply this number on the checklist. EWS System Operating System and Software Version AMCC-system release compatibility is defined in the Operation and Installation section of the AMCC Design Manual and is the minimum release level that is compatible with the AMCC MacroMatrix package. Where a CAD/CAE software package is available on several platforms, that information is also clearly defined.

Index file for Floppy Disks; Tapes (required) Each floppy disk (tape) submitted must contain its own text index file (read.me) listing all files contained on that disk (tape), with a description of each file. Each disk (tape) should be clearly labeled as to its name and contents. All file names should be

meaningful. One disk (tape) should contain a master index file listing all disk (tape) files and their contents. A hardcopy of this master index file should also be submitted. All files should be on AMCC-readable magnetic media.

Schematic Drawing Pages (may be required) The final versions of all submitted schematic pages are to be on both magnetic media and in hardcopy format. Two sets of the printed schematics (minimum) are required; three sets for non-EWS schematics. One set must be clearly marked (highlighted) to show AC Test paths and critical paths. Label AC Test paths with the documentation AC Test number. Label the critical paths with the timing correlation report path number.

AGIF Netlist - circuit.sdi (required) The final version of the AGIF (AMCC Generic Interface Format) netlist that was used as input to the MacroMatrix AMCCERC, AMCCANN, AMCCSIMFMT, AMCCVRC and AMCCSUBMIT programs must be included on the media (disk or tape). They require the use of the AGIF netlist. The netlist file is called circuit.sdi and is located in the .../ERC subdirectory. There should only be one of these files for any given set of simulations running on the same library (MILMAX, etc.)

AMCCERC (Rules Check) Report (required) The printed AMCCERC report, AMCCERC.LST, must be submitted with the hardcopy and media documentation. Any error messages must be accompanied with an AMCC waiver (approved Pre-Approval Request or PAR) and a description as to their intended resolution. [Page 6-A-1; 6-A-2]

Design Validation Review (required) A complete and comprehensive design validation review is required for all design submissions and is prompted for by AMCCSUBMIT. In cases where there is no software support for design rules, the designer must perform the validation checks manually and submit the results.

I/O List (required) The list of all signal I/O, added power and ground pads and fixed power and ground pads including signal I/O type (TTL standard, TTL open-collector, TTL 3-state, ECL 10K, ECL 100K, etc.) and clear identification of simultaneously switching outputs is generated by AMCCERC and called AMCCIO.LST. It must be included in the hardcopy and media documentation.

Annotation Level Space is provided on the submission checklist for annotation level, either FrontAnnotation or Back-Annotation. Back-Annotation submissions are currently handled as special cases.

Maximum Operating Frequency The specified maximum operating frequency is the frequency at which the At-Speed simulation must be run; specify it in MHz or GHz.

Power The total power in Watts is to be computed or estimated. This includes DC power and any AC power, following the directions in Volume I, Section 5 of the design manual specific to the AMCC array series. Specify any differences between the total power entered here and the power computed by AMCCERC. The difference may be the AC power computation, different termination loading or duty cycles.

Annotation and Output Loading (required) AMCCPKG.LST AMCCANN output.dly AMCCANN allows the package type, package pin capacitance and system loading to be specified for the circuit. Commentary information on frequency must be added for high-speed I/O (see Section 4). The list of all signals with pad placement (if known), package pin capacitance (Front-Annotation or Back-Annotation), and system load is called AMCCPKG.LST. It must be included in the hardcopy and media documentation. The output.dly data file generated by AMCCANN must be included on media. The output capacitive load delays are included in the annotation files and is reflected in the simulation results. The delay files used in the simulations must be submitted on media. For Front-Annotation these are: FNTxxx[x].yyy, where xxx[x] is the simulation type (mil, com, min, nom,c5mx, c5mn, etc.) and yyy is the extension denoting the system used (dsy, val, men, ver, lsr, etc.). Back-Annotation uses BCKxxx[x].yyy. Refer to Volume I, Section 3 for a detailed list of the files used with a particular array series.

Cross Reference (optional) The AMCC cross-reference file, AMCCXREF.LST can be submitted on media. It is currently not required.

Function Description of the Circuit (optional) AMCC prefers that a high-level functional description of the circuit on the array be included in the hardcopy documentation. This description should include the required performance of the circuit, any timing constraints, interface requirements, testing specifications and the operating environment.

Block Diagram of the Circuit ..(optional) Unless a hierarchical schematic capture has been performed, AMCC prefers that a toplevel block diagram of the circuit as configured for the array be included in the hardcopy documentation. If a hierarchical schematic capture has been performed, the top-level schematic may be sufficient.

Preplacement Requests (optional) Preplacement of macros for critical timing requirements can be submitted to AMCC if the designer feels it to be necessary. All preplacement requests will be evaluated by AMCC, and the designer will be notified if they can or cannot be met.

Pin-Out Requests (optional) I/O placement may be of concern in a design, and the designer may wish to specify a pin-out request to AMCC. The final pin-out is driven by layout considerations and restrictions. The pin-out requests will be evaluated by AMCC, and the designer will be notified if they can or cannot be met.

Critical Path and Timing Requirements (required) The maximum required frequency of operation for the circuit and the expected performance for the critical paths should be clearly stated in the hardcopy documentation following the procedure discussed in "Vector Submission Rules and Guidelines" in the AMCC design manual. Use the Timing Correlation report form for any path not covered by an AC Test.

Waivers - Approved PARS Attach any preapproval requests that have been approved to the design submission package and list them by number on page 6-A-2. These include custom macros, design rule variations, approved AMCCERC errors, approved timing check errors, and approved AMCCVRC errors.

Functional Simulation Submission (Required)

The functional simulation output vectors, consisting of all of the input and the expected output signals generated by the input stimulus file, are the actual vectors used by the AMCC test department to verify the correct functional operation of the part. The customer must supply all functional simulation vectors. AMCC uses functional simulation output vectors for fault grading and recommends 90% or better fault coverage of the final circuit. AMCC requires that functional simulations be performed once using the minimum library and once using the maximum worst-case library. Refer to Volume I, Section 3 for the specific series to determine which library is maximum and which minimum for the array. The minimum simulation should exactly match the maximum simulation. If not, a potential timing problem could exist. Resolve the problem or consult with AMCC and send in both the minimum and maximum functional simulations. The functional simulation should be performed following the procedures described in the design manual.

Functional Simulation Documentation

The documentation required for an AC Test simulation submission is prompted for by the AMCCSUBMIT program interface. Before running AMCCSUBMIT, simulation files for the paths in sampled format should exist. All AMCCSUBMIT errors should be resolved prior to submission.

Documentation included on disk or tape for each functional simulation file includes:

the sampled AMCCSIMFMT file name (file is UNEDITED); whether this was a MIN or a MAX simulation; PRODUCT_GRADE is prompted in the form header (identifies the annotation file used); the simulation control file name; the simulation input file name, if any; the simulation command file name which may be submit procedures, a transcript of system operation during simulation, including VIEW, RUN, START, LIST, WRITE, etc. statements as required for the specific system; the AMCCVRC.LST report file name (rename since several are included per submission); the signal analysis file used with AMCCVRC; the name of the text file version of the data or the control file which clearly describes the testing performed; the timing check report for the file (all simulations done for submission use timing checks active). the AMCCVRC.LST report commented for errors AMCC waivers.

At-Speed Simulation Submission (Required)

The submitted at-speed simulation is rerun after layout to verify the actual timing performance for the array. The Back-Annotation delay file, which provides the actual metal delays for the layout, is used in place of the Front-Annotation delay file. The circuit.pkg file provides package pin capacitance based on final placement to replace the estimates for package pin capacitance in the output.dly file. At-speed simulation results provide an evaluation of the timing performance and help identify timing violations and potential timing problems. The customer must supply all at-speed simulation vectors. AMCC requires that at-speed simulations be performed at the specified maximum operating frequency, and be performed using the minimum library and then again using the maximum worst-case library. Refer to Volume I, Section 3 for the specific series to determine which library is maximum and which minimum for the array. The at-speed simulation, if required, should be performed following the procedures described in the design manual.

At-Speed Simulation Documentation

The documentation required for at-speed simulation submission is prompted for by the AMCCSUBMIT program interface. Before running AMCCSUBMIT, simulation files for the paths, both in sampled and in print-on-change format should exist. All AMCCSUBMIT errors should be resolved prior to submission. Documentation included on disk or tape for the sampled at-speed simulation file includes:

the file number (1..n); no paging of at-speed files is required or necessary; the sampled AMCCSIMFMT file whether this was a MIN or MAX simulation; PRODUCT_GRADE is prompted on the form header (identifies the annotation file);

the simulation control file name; the simulation input file name, if any; the simulation command file name which may be submit procedures, a transcript of system operation during simulation, including VIEW, RUN, START, LIST, WRITE, etc. statements as required for the specific system; the name of the text file version of the data or the control file which clearly describes the testing performed; the timing check report for the file (all simulations done for submission use timing checks active).

Documentation included on disk or tape for the print on change at-speed simulation file includes:

everything included to document the sampled at-speed simulation except that the sampled AMCCSIMFMT file is replaced by the print on change AMCCSIMFMT file.

AC Tests Path Delay Vector Submission (Optional)

AC Testing is an automated testing methodology used to examine in close detail circuit performance measurements of propagation path delay. A separate set of vectors is required for each measurement, and each set must initialize and bias the path and provide the means by which the measurement can be made. If this testing option is desired, then these vectors must be supplied. They are in addition to functional simulation vectors. A maximum of 10 paths and 20 tests can be tested per array. Refer to the "Vector Submission Rules and Guidelines" concerning a concatenated set of vectors or the use of one set of vectors for multiple, individual tests. AMCC requires that AC Test simulations be performed using the minimum library and then again using the maximum worst-case library. Refer to Volume I, Section 3 for the specific series to determine which library is maximum and which minimum for the array. The minimum simulation should exactly match the maximum simulation. If not, a potential timing problem could exist. Resolve the problem or consult with AMCC and send in both the minimum and maximum AC Test simulations. The AC Test simulations should be performed following the procedures described in the design manual. Documentation of AC Test Simulation [AMCCSUBMIT] The documentation required for an AC Test simulation submission is prompted for by the AMCCSUBMIT program interface. Before running AMCCSUBMIT, simulation files for the paths, both in sampled and in print-on-change format should exist. The program is iterative, allowing test to be documented one at a time or a test to be partially documented in one run and completed in another. All AMCCSUBMIT errors should be resolved prior to submission.

Parametric Vectors (Required or Optional)

Parametric testing is optional, provided the SSO switching in the output vectors does not exceed the 16 (mixed mode) or 32 (100% TTL or 100% ECL) switching outputs per vector limit. If parametric vectors are required, the customer must supply all parametric simulation vectors. AMCC requires that Parametric simulations be performed using the minimum library and then again using the maximum worst-case library. The minimum simulation should exactly match the maximum simulation. If not, a potential timing problem could exist. Resolve the problem or consult with AMCC and send in both the minimum and maximum parametric simulations. The parametric simulation should be performed following the procedures described in the design manual. Parametric Simulation Documentation The documentation required for the parametric simulation submission is prompted for by the AMCCSUBMIT program interface. Before running AMCCSUBMIT, simulation files for the paths in sampled format should exist. All AMCCSUBMIT errors should be resolved prior to submission. Documentation included on disk or tape for each parametric simulation file includes:

the file number (1..n) when 4K pages are submitted or when the functional simulation is a set of simulation files (Volume II, Section 4); the sampled AMCCSIMFMT file name (file is UNEDITED); whether this was a MIN or a MAX simulation; PRODUCT_GRADE is prompted in the form header (identifies the annotation file used); the simulation control file name; the simulation input file name, if any; the simulation command file name which may be submit procedures, a transcript of system operation during simulation, including VIEW, RUN, START, LIST, WRITE, etc. statements as required for the specific system; the AMCCVRC.LST report file name (rename since several are included per submission); the name of the text file version of the data or the control file which clearly describes the testing performed;

Hardcopy documentation consists of:

The AMCCVRC.LST report commented for errors and AMCC waivers.

AMCC Simulation Forms - Vocabulary

The simulation submission forms require at least one functional simulation run at worstcase maximum. The items requested are:
File # Item number, 1,2,3... AMCCSIMFMT OUTPUT FILENAME The user-defined name assigned to the formatted simulation output file (the vectors being submitted). The input to AMCCSIMFMT is from a VALID tabular trace output, MENTOR LIST, DAZIX VLAIF output file, etc. MIN Check if this is a MINIMUM simulation. This assumes a MIN timing library and FNTMIN.ews or the equivalent annotation file. MAX Check if this is a maximum simulation. This assumes a maximum for the product_grade timing library and FNTMIL.ews, FNTCOM.ews or the equivalent Q20000 or Q24000 annotation delay file (COM5MAXmax - fntc5mx.ews, MIL5MAXmax fntm5mx.ews). SIMULATION CONTROL FILENAME The file required by the EWS to input stimulus, etc. that was used to perform the submitted simulation. It is called the SOM_MCF.SING file on DAZIX, the transcript file on MENTOR, the directives file on VALID, etc. SIMULATION INPUT FILENAME Any other required input file. Called the remote data VLAIF file on DAZIX, the stimulus input file on VALID. Mentor may have a data file called from the force file. The existence of this file depends on the method used to create the stimuli. SIMULATION COMMAND FILENAME The transcript or log of operations or submit process, i.e., what it would take for AMCC to duplicate the simulation. AMCCVRC REPORT FILENAME Always rename AMCCVRC.LST to a user-defined name since more than one is to be submitted. List the one that goes with the netlist and AMCCSIMFMT output file. AMCCVRC is not required for minimum simulations, for sampled at-speed simulations, or for print-on-change simulations. AMCCVRC SIGNAL ANALYSIS FILENAME The clock race-condition test requires a signal analysis file to specify clock-data relationships. A user-defined name. SIMULATION DESCRIPTION FILE The text file, may be a commented copy of the AMCCSIMFMT output file, which describes the testing being performed.