Return of the SystemVerilog Gotchas.bresticker

Just When You Thought It Was Safe to Start Coding Again... Return of the SystemVerilog Gotchas

Shalom Bresticker

Intel CorporationShalom.Bresticker@intel.com

ABSTRACT

All programming languages have gotchas: easy-to-make errors or misunderstandings that look OK, but don't work, don't behave as expected, or differ between tools. The canonical examplefrom C is writing "if (a=b)" instead of "if (a==b)". Knowing about SystemVerilog's gotchas helpsprevent making these mistakes, and eases detecting and debugging them when they do occur.Sutherland and Mills published a book of gotchas in 2007, but there are many more. This paperpresents a selection of additional gotchas that have bitten the author and his colleagues over theyears, some of them very nasty. The gotchas are divided into (1) gotchas that exist in Verilog (2)gotchas that are new in SystemVerilog (3) gotchas connected to how the RTL code issynthesized.This is a revision of a paper of the same name that was presented at Boston SNUG 2008.This work does not in any way constitute an Intel endorsement of a product or supplier.

SNUG Boston 2008 Return of the SystemVerilog Gotchas2

Table of Contents

1.0 Introduction ......................................................................................................................... 41.1 Abbreviations and terminology ........................................................................................... 41.2 Why are there gotchas? ....................................................................................................... 51.3 What types of gotchas are there? ........................................................................................ 61.4 Where do gotchas come from? ........................................................................................... 71.5 How to deal with gotchas .................................................................................................... 81.6 Previous work ..................................................................................................................... 91.7 What follows in the rest of the paper .................................................................................. 92.0 Verilog Gotchas ................................................................................................................ 102.1

always @*

oscillations (V2K1) .................................................................................... 102.2

always

procedures that are never executed .................................................................... 122.3 Misuse of logical AND and OR ........................................................................................ 132.4 Zero replication constants ................................................................................................. 142.5 Negative replication constants .......................................................................................... 162.6 Elaboration of unused illegal parameterized code ............................................................ 162.7 Incorrectly written indexed part-select (V2K1) ................................................................ 172.8 String size-extension ......................................................................................................... 182.9 Macro expressions need to be in parentheses ................................................................... 192.10 Macro call within string literal .......................................................................................... 202.11 Null ports .......................................................................................................................... 213.0 SystemVerilog Gotchas ..................................................................................................... 223.1 Types defined in different scopes ..................................................................................... 223.2 Arrays vs. queues .............................................................................................................. 233.3 Using `` for concatenation within an escaped identifier ................................................... 243.4 Use of special macro character sequences outside of macros ........................................... 253.5 Are spaces around macro arguments dropped? ................................................................. 263.6 String equality and compare functions have opposite return values ................................. 273.7 Glitches in

unique

/

priority

..................................................................................... 273.8 Glitches in immediate assertions ...................................................................................... 283.9 Assignments in expressions .............................................................................................. 293.10 Uneven coverage bin distribution ..................................................................................... 303.11

const

variables are not parameters ................................................................................. 313.12 The static initialization order fiasco .................................................................................. 324.0 Synthesis Gotchas ............................................................................................................. 334.1

always_comb

does not guarantee combinational logic ................................................ 334.2 My flip-flop is a latch! ...................................................................................................... 344.3 Myth:

default/full_case/unique/priority

prevent latches ........................ 364.4 Why is my combinational logic considered sequential? ................................................... 394.5 A synthesis engine is not as smart as a formal engine ...................................................... 394.6 Asynchronous reset loops in flip-flops ............................................................................. 415.0 Conclusions and Recommendations ................................................................................. 426.0 Acknowledgements ........................................................................................................... 437.0 References ......................................................................................................................... 43

SNUG Boston 2008 Return of the SystemVerilog Gotchas3

8.0 About the Author .............................................................................................................. 44

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