Modeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation
By Axel Jantsch
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About this ebook
This book directly addresses that need by developing organizing principles for understanding, assessing, and comparing the different models of computation necessary for system level modeling. Dr. Axel Jantsch identifies the representation of time as the essential feature for distinguishing these models. After developing this conceptual framework, he presents a single formalism for representing very different models, allowing them to be easily compared. As a result, designers, students, and researchers are able to identify the role and the features of the "right" model of computation for the task at hand.
*Offers a unique and significant contribution to the emerging field of models of computation
*Presents a systematic way of understanding and applying different Models of Computation to embedded systems and SoC design
*Offers insights and illustrative examples for practioners, researchers and students of complex electronic systems design.
Axel Jantsch
Axel Jantsch received a Dipl.Ing. in 1988 and a Dr. Tech. degree in 1992 from the Technical University of Vienna. Between 1993 and 1995 he received the Alfred Schrödinger scholarship from the Austrian Science Foundation as a guest researcher at the Royal Institute of Technology (KTH) in Stockholm. From 1995 through 1997 he was with Siemens Austria in Vienna as a system validation engineer. From 1997 to 2002 he was as Associate Professor at KTH, and since December 2002 he has served as Professor in Electronic System Design. Jantsch has published in the areas of VLSI design and synthesis, system level specification, modeling and validation, HW/SW codesign and cosynthesis, reconfigurable computing, processor design and networks-on-chip. For several years he has been a program committee member of FDL and DATE conferences. He has served as TPC chair of SSDL/FDL 2000 and is Subject Area Editor for the Journal of Systems Architecture. At KTH, Jantsch is heading a number of research projects in the areas of system level specification, design, synthesis, validation and network-on-chip architecture. From 1999 to 2002, he served as program manager of the Swedish research program Integrated Electronic Systems with a 4-year budget of 12 million Euro.
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Titles in the series (21)
Processor Description Languages Rating: 5 out of 5 stars5/5ESL Design and Verification: A Prescription for Electronic System Level Methodology Rating: 0 out of 5 stars0 ratingsReconfigurable Computing: The Theory and Practice of FPGA-Based Computation Rating: 0 out of 5 stars0 ratingsEmbedded DSP Processor Design: Application Specific Instruction Set Processors Rating: 0 out of 5 stars0 ratingsMultiprocessor Systems-on-Chips Rating: 0 out of 5 stars0 ratingsThe System Designer's Guide to VHDL-AMS: Analog, Mixed-Signal, and Mixed-Technology Modeling Rating: 5 out of 5 stars5/5ASIC and FPGA Verification: A Guide to Component Modeling Rating: 5 out of 5 stars5/5Designing SOCs with Configured Cores: Unleashing the Tensilica Xtensa and Diamond Cores Rating: 5 out of 5 stars5/5The Designer's Guide to VHDL Rating: 4 out of 5 stars4/5System Level Design with Rosetta Rating: 0 out of 5 stars0 ratingsReadings in Hardware/Software Co-Design Rating: 3 out of 5 stars3/5On-Chip Communication Architectures: System on Chip Interconnect Rating: 0 out of 5 stars0 ratingsModeling Embedded Systems and SoC's: Concurrency and Time in Models of Computation Rating: 0 out of 5 stars0 ratingsAspect-Oriented Programming with the e Verification Language: A Pragmatic Guide for Testbench Developers Rating: 0 out of 5 stars0 ratingsSystem-on-Chip Test Architectures: Nanometer Design for Testability Rating: 0 out of 5 stars0 ratingsVerification Techniques for System-Level Design Rating: 0 out of 5 stars0 ratingsElectronic Design Automation: Synthesis, Verification, and Test Rating: 0 out of 5 stars0 ratingsVHDL-2008: Just the New Stuff Rating: 5 out of 5 stars5/5Low-Power Design of Nanometer FPGAs: Architecture and EDA Rating: 0 out of 5 stars0 ratingsNetworks on Chips: Technology and Tools Rating: 5 out of 5 stars5/5Network Processors: Architecture, Programming, and Implementation Rating: 0 out of 5 stars0 ratings
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