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Published by: Paras Relan on Jul 15, 2012
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simplicity). DECstation 3100. Sun-4/110. RISC I. Intel i860. MIPS M/1000. Sun-4/260]/13 = 560 = DLX (Roman) Good architectural features (e. IBM 801.DLX DLX pronounced “ eluxe” D Has the features of many recent experimental and commercial machines [AMD 29K.g. SGI 4D/60. MIPS M/120A. SPARCstation-1. Motorola 88K. easy to understand . HP 850.

F2.DLX Architecture: Registers and Data Types Has 32 32-bit GPRs: R0.. .R31 Also. 16 double precision: F0. half-words.. words FP: single/double precision ...F31 Or... F30 Value of R0 is always ZERO! Data types: Integer: bytes. FP registers 32 single precision: F0.

big-endian mode Addressing modes: Only immediate and displacement.DLX Memory Addressing Uses 32-bit. with 16-bit fields Register deferred? Place zero in displacement field Absolute Use R0 for the register .

jump register. jump and link. conditional branch. trap and return .DLX Instruction Format Opcode (6) RS1 (5) RD (5) Immediate (16) I-type instruction: loads. stores. jump and link register Opcode (6) RS1 (5) RS2 (5) RD (5) Func (11) R-type instruction: register-register ALU operations Opcode (6) Offset relative to PC (26) J-type instruction: jump. all immediates.

ALU.DLX Operations Four classes: Load/store. reg-reg move Compares “ et”a register s Jump and link pushes next PC onto R31 FP operations in single/double precision FP compares set a bit in a special status reg FP unit also used for integer multiply/divide! . branch. FP ALU instructions are register-register R0 used to synthesize some operations: Examples: loading a constant.

5 2 1.DLX Performance: MIPS vs VAX Perf.5 MIPS/VAX ratio 3 2.5 1 0.5 0 Spice Matrix Nasa7 Fpppp Tom catv Doduc Espres so Eqntott Li SPEC89 benchmarks . ratio IC ratio CPI ratio 4 3.

Pipelining Its natural! Laundry example. (Randy Katz's slides) DLX has a simple architecture Easy to pipeline Pipelining speedup: Can be viewed as reduction in CPI Or... reduction in clock cycle Defining clock cycle as the amount of time between two successive instruction completions .

A Simple DLX Implementation Instruction Fetch (IF) cycle: IR <-..R[IR11..31) .10] B <-.R[IR6.15] Imm <-.M[PC] NPC <-.PC + 4 Instruction Decode (ID) cycle: Done in parallel with register read (fixed field decode) Register/Immediate read: A <-.sign-extend(IR16..

A func B Register-immediate ALU instruction: ALUOutput <-.NPC + Imm Cond <-.A Simple DLX Implementation (continued) Execution/effective address (EX) cycle: Memory reference: ALUOutput <-.A op 0 [op is one of == or !=] .A op Imm Branch: ALUOutput <-.A + Imm Register-register ALU instruction: ALUOutput <-.

15] <-...15] <-..ALUOutput Reg-imm ALU opn: R[IR11.20] <-.M[ALUOutput] Or. M[ALUOutput] <-.ALUOutput Load instruction: R[IR11.B Branch: PC = (cond) ? ALUOutput : NPC Write-back (WB) cycle: Reg-reg ALU opn: R[IR16.A Simple DLX Implementation (continued) Memory access/branch completion (MEM) cycle: Memory access: LMD <-.LMD .

IR mem m u x Sign ext. Imm . File B Zero? m u x Cond ALU m u x ALU o/p Data mem LMD Instrn.The DLX Data-path IF ID EX MEM m u x WB 4 Add NPC A PC Reg.

. Pipelining this data-path Pipelining issues .Further lectures..

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