MAHENDRA COLLEGE OF ENGINEERING

SALEM.

LAB MANUAL

Department of ECE

DIGITAL LABORATORY
( Common to IT/CSE)

Prepared by,

Name

: Er.D.Balaji. M.E

Designation: Assistant Professor

INDEX EX. NO PAGE NO

DATE

NAME OF THE EXPERIMENT

MARKS

SIGN

SIGNATURE OF THE STAFF:

TOTAL:

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force is selected and the values are given. 5. 7. 6. Give the input and observe the output in the Xilinx kit. 2. Then click assign package pin (run) from user constraints. 2. In the Xilinx. Select implementation constraint file and give the file name. Finally Add – wave is clicked view the result waveform. 9. After the program is typed. 3. After that it is simulated. 8. Then the program is compiled and errors are checked. Select VHDL module from XC3S400-4pq208. 3. Run the synthesis XST. Then in the edit option. open a new project and give the file name. To start the programs click the modelsim software.click the file option to create a new source in VHDL. SYNTHESIS PROCEDURE 1. implement design and generate program file sequentially.1. A) FPGA IMPLEMENTATION SIMPLE ALARM SYSTEM AIM To design and implement Simple Alarm System using FPGA. 8. 6. it is saved in a name with extension’ . 7. Then the program is viewed and the signal option is clicked from the view menu and input signals are given. TOOLS REQUIRED Simulation Synthesis : ModelSim : Xilinx 9. .vhd’ 4. The main page is opened. 5. Give the pin location and save the file. Select program and wait until it gets succeed. 4.2i SIMULATION PROCEDURE 1. Type the program and create new source.

ALL. begin ----. END IF. ELSIF (remote='1' AND flag='1') THEN nx_state <= disarmed. rst) BEGIN IF (rst='1') THEN flag <= '0'. END IF. remote. siren: OUT STD_LOGIC).STD_LOGIC_1164.PROGRAM: library IEEE. use IEEE.Upper section: ------------------PROCESS (pr_state. rst) BEGIN IF (rst='1') THEN pr_state <= disarmed. ATTRIBUTE enum_encoding OF alarm_state: TYPE IS "sequential". intrusion). flag. END PROCESS. SIGNAL pr_state. sensors) BEGIN CASE pr_state IS WHEN disarmed => siren <= '0'. ELSE . ELSE nx_state <= disarmed.ALL.Flag: ----------------------------PROCESS (remote.ALL. sensors: IN STD_LOGIC. ATTRIBUTE enum_encoding: STRING. armed. ELSIF (remote'EVENT AND remote='0') THEN flag <= NOT flag. use IEEE. remote. use IEEE.Lower section: -------------------PROCESS (clk.STD_LOGIC_ARITH. SIGNAL flag: STD_LOGIC.STD_LOGIC_UNSIGNED. ELSIF (clk'EVENT AND clk='1') THEN pr_state <= nx_state. END IF. IF (sensors='1') THEN nx_state <= intrusion. entity alarm is PORT (clk. ----. rst. nx_state: alarm_state. WHEN armed => siren <= '0'. end alarm. ----. IF (remote='1' AND flag='0') THEN nx_state <= armed. END PROCESS. architecture Behavioral of alarm is TYPE alarm_state is (disarmed.

END IF. ELSE nx_state <= intrusion.nx_state <= armed. IF (remote='1' AND flag='1') THEN nx_state <= disarmed. WHEN intrusion => siren <= '1'. . END Behavioral. END PROCESS. END CASE. RESULT Thus the “Simple Alarm System” was implemented in Spartan-3 Trainer and its working is demonstrated on interfacing board. END IF.

z. 8. elsif(x='0' and y='1' and z='0' and p='1')then . 6. 3. Type the program and create new source. 2. B) FPGA IMPLEMENTATION OF PARITY CHECKER AIM To design and implement parity checker using FPGA TOOLS REQUIRED Simulation Synthesis : ModelSim : Xilinx 9. end parity. 8. Then the program is compiled and errors are checked. Run the synthesis XST. elsif(x='0' and y='1' and z='0' and p='0')then c<='1'.y. 7. Then click assign package pin(run) from user constraints. Give the input and observe the output in the Xilinx kit. Give the pin location and save the file. Select program and wait until it gets succeed.vhd’ 4. 7. The main page is opened. elsif(x='0' and y='0' and z='1' and p='1')then c<='0'. PROGRAM library ieee. c:out std_logic).1.p) begin if(x='0' and y='0' and z='0' and p='0')then c<='0'.z. After the program is typed.std_logic_1164. elsif(x='0' and y='0' and z='0' and p='1')then c<='1'. open a new project and give the file name. 3. Finally Add – wave is clicked view the result waveform. elsif(x='0' and y='0' and z='1' and p='0')then c<='1'. 5. In the Xilinx. entity parity is port(x. it is saved in a name with extension’ . architecture tms of parity is begin process(x. Select implementation constraint file and give the file name.all. click the file option to create a new source in VHDL. 6. use ieee. 2. After that it is simulated. SYNTHESIS PROCEDURE 1.y. 5. 9. To start the programs click the modelsim software.p:in std_logic.2i SIMULATION PROCEDURE 1. implement design and generate program file sequentially. 4. Then the program is viewed and the signal option is clicked from the view menu and input signals are given. Select VHDL module from XC3S400-4pq208. force is selected and the values are given. Then in the edit option.

end if. elsif(x='1' and c<='0'. elsif(x='1' and c<='0'. else c<='x'. elsif(x='0' and c<='1'. elsif(x='1' and c<='1'.c<='0'. end tms. elsif(x='1' and c<='0'. elsif(x='1' and c<='1'. elsif(x='1' and c<='1'. y='1' and z='1' and p='0')then y='1' and z='1' and p='1')then y='0' and z='0' and p='0')then y='0' and z='0' and p='1')then y='0' and z='1' and p='0')then y='0' and z='1' and p='1')then y='1' and z='0' and p='0')then y='1' and z='0' and p='1')then y='1' and z='1' and p='0')then y='1' and z='1' and p='1')then . end process. elsif(x='0' and c<='0'. elsif(x='1' and c<='0'. elsif(x='1' and c<='1'.

BIT EVEN PARITY GENERATOR Truth Table Three bit message X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 Parity bit P 0 1 1 0 1 0 0 1 4 BIT EVEN PARITY CHECKER .3.

C) FPGA IMPLEMENTATION OF SCROLLING DISPLAY .Truth Table X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Four bits Received Y Z 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 P 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Parity Error Check C 0 1 1 0 1 0 0 1 1 0 0 1 0 1 1 0 RESULT Thus the “parity checker” was implemented in Spartan-3 Trainer and its working is demonstrated on interfacing board. 1.

use ieee.k:in std_logic. e<='0'. PROGRAM: library ieee. Run the synthesis XST. f<='1'. elsif(h='0' and i='0' and j='0' and k='1')then a<='0'. b<='1'. To start the programs click the modelsim software. 3.vhd’ 4. c<='1'.k) begin if(h='0' and i='0' and j='0' and k='0')then a<='1'. architecture display of led is begin process(h. 8. SYNTHESIS PROCEDURE 1. Give the pin location and save the file. 6. Select program and wait until it gets succeed.e.f. entity led is port(h. end led. In the Xilinx. g<='0'.j. The main page is opened. 3.c. 8. 7.j. e<='1'. 2.b.g:out std_logic).i.i. Finally Add – wave is clicked view the result waveform. implement design and generate program file sequentially. Then the program is compiled and errors are checked. open a new project and give the file name. Give the input and observe the output in the Xilinx kit. 2. c<='1'. After that it is simulated. it is saved in a name with extension’ . Type the program and create new source. Then the program is viewed and the signal option is clicked from the view menu and input signals are given.2i SIMULATION PROCEDURE 1.d. After the program is typed. 4. d<='0'. 9. . Then click assign package pin(run) from user constraints. 5. click the file option to create a new source in VHDL. a. Then in the edit option.std_logic_1164. d<='1'. b<='1'. Select VHDL module from XC3S400-4pq208.AIM To design and implement Scrolling display using FPGA TOOLS REQUIRED Simulation Synthesis : ModelSim : Xilinx 9. force is selected and the values are given. 7. 6.all. 5. Select implementation constraint file and give the file name.

d<='1'. c<='1'. e<='1'. f<='0'.f<='0'. c<='0'. c<='0'. d<='0'. f<='1'. elsif(h='0' a<='0'. f<='1'. d<='1'. d<='1'. d<='1'. b<='0'. c<='1'. and i='0' and j='1' and k='0')then and i='0' and j='1' and k='1')then and i='1' and j='0' and k='0')then and i='1' and j='0' and k='1')then and i='1' and j='1' and k='0')then and i='1' and j='1' and k='1')then and i='0' and j='0' and k='0')then . b<='1'. c<='1'. elsif(h='1' a<='1'. e<='0'. b<='1'. g<='1'. c<='1'. g<='0'. g<='1'. elsif(h='0' a<='1'. g<='0'. e<='0'. f<='1'. b<='0'. g<='0'. f<='1'. elsif(h='0' a<='1'. e<='0'. g<='1'. b<='1'. b<='1'. c<='1'. elsif(h='0' a<='1'. f<='0'. e<='1'. b<='1'. d<='1'. g<='0'. elsif(h='0' a<='1'. elsif(h='0' a<='1'. e<='1'.

elsif(h='1' and i='0' and j='0' and k='1')then a<='1'. 1. g<='1'. end display. f<='1'. g<='1'.d<='1'. c<='1'. end process. D) FPGA IMPLEMENTATION OF MULTIMODE CALCULATORS AIM: To design and implement multimode calculator using FPGA . d<='1'. f<='1'. e<='1'. e<='0'. end if. Truth table Number inputs to be h display 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 1 9 1 outputs a b 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 i 0 0 0 0 1 1 1 1 0 0 j 0 0 1 1 0 0 1 1 0 0 k 0 1 0 1 0 1 0 1 0 1 c 1 1 0 0 1 1 1 1 1 1 d 1 0 1 1 1 1 1 0 1 1 e 1 0 1 1 0 0 1 0 1 0 f 1 0 0 0 1 1 1 1 1 1 g 0 0 1 0 1 1 1 0 1 1 RESULT Thus the “Scrolling display” was implemented in Spartan-3 Trainer and its working is demonstrated on interfacing board. b<='1'.

. The main page is opened. Then click assign package pin (run) from user constraints.vhd’ 4. Select program and wait until it gets succeed. After the program is typed. To start the programs click the modelsim software.APPARATUS REQUIRED: Simulation : ModelSim Synthesis : Xilinx 9. 3. Give the input and observe the output in the Xilinx kit. implement design and generate program file sequentially. 4. 6. Then the program is viewed and the signal option is clicked from the view menu and input signals are given. Give the pin location and save the file. open a new project and give the file name. Select VHDL module from XC3S400-4pq208. Type the program and create new source. it is saved in a name with extension’ . Finally Add – wave is clicked view the result waveform. Then the program is compiled and errors are checked. 9. 8. 2. After that it is simulated. 7. SYNTHESIS PROCEDURE 1. In the Xilinx. 6. click the file option to create a new source in VHDL. 5. 7. 2. Select implementation constraint file and give the file name. 8. 3. Then in the edit option. 5. force is selected and the values are given. Run the synthesis XST.2i SIMULATION PROCEDURE 1.

entity cal is port (a. end case. end cal. . when"1001"=>result<=a+1. when"0101"=>result<=a or b. when"1010"=>result<=a-1. b. when others =>result<="00000000". when"1110"=>result<=not b. sel: in std_logic_vector (3 downto 0). when"0001"=>result<=a-b. b: in std_logic_vector (7 downto 0). when "0010"=>mulresult<=a*b. when"1100"=>result<=b-1.std_logic_unsigned. use ieee. architecture Behavioral of cal is begin process (a. when"0111"=>result<=a nor b.std_logic_1164. when"1000"=>result<=a nand b. when"1101"=>result<=not a. sel) begin case sel is when"0000"=>result<=a+b.all.all. mulresult: out std_logic_vector (15 downto 0)). end Behavioral. result: out std_logic_vector (7 downto 0). use ieee. when"1011"=>result<=b+1. when"0110"=>result<=a xor b.all. use ieee.PROGRAM: library ieee. when"0100"=>result<=a and b. end process.std_logic_arith.

OUTPUT: RESULT: Thus the “multimode calculator” was implemented in Spartan-3 Trainer and its working is demonstrated on interfacing board. .

13. Select layout tag (PCB Foot print) 4. Open Orcad release and open new project. Place the markers and run the PSPICE model. Desktop computer PROCEDURE: Simulation: 1. Browse the location to save the *. 3. Select the *.mnl file then click OK 5. then make routing between the components.2. Click new menu in file menu bar 7.1 2. 5. Go to auto menu-choose place board then click auto route board . Select components from PSPICE library. Save the content and create netlist. Select the create net list menu in the tools menu bar 3. 2.tch) then click open 8. 4. Select the obstacle tool from the tool bar 12. Draw space to cover all the footprints. Load the template file (default.tch) in the working directory(C:\Program files\orcad\layout\data\default. Rearrange the components as you like 11.max 10.mnl file then click open 9. Layout: 1. 7. Place components in appropriate locations on schematic page. Save the board file *. Load the text list source file where you have stored *. Open the layout application 6. Orcad 9.dsn file in the left panel 2. Open new simulation option in the PSICE tool and give run time details. 6. End of the process. PCB DESIGN USING CAD AIM: To design and implement 3 to 8 decoder SPICE TOOLS REQUIRED: 1. 8. Create a new folder at a particular path and select analog and mixed circuit wizard option.

3 TO 8 DECODER U 1 A 2 7 4 L S 0 4 U 1 2 1 3 7 0 3 4 5 U 3 S 1 7 U U 1 C 6 1 S 2 0 0 7 0 9 1 0 1 1 7 U 1 2 1 3 7 U 3 4 5 7 4 B 6 0 4 L S 1 1 V 2 A 1 2 1 4 L S 1 1 V A D S T M 1 V 1 D 0 S I N U 2 B 6 0 7 4 L S 1 1 V D 1 B D T M 2 V 1 B 4 7 4 L S 0 4 9 1 0 1 1 U 2 C S I N 8 0 4 L S 1 1 V D 2 3 A 1 2 0 7 4 L S 1 1 V 1 1 S 0 4 1 2 1 3 C D T M 3 V 5 7 D 3 4 L S I N 3 4 5 U 3 B 6 0 4 L S 1 1 V D 4 U 3 C 8 0 4 L S 1 1 V D 5 4 A 1 2 0 4 L S 1 1 V D 6 D 7 .

OUTPUT RESULT: Thus the given digital circuits were designed and layout was drawn using PSPICE .

MATLAB 7.3. DSK KIT (TMS 320 C 6711 Or TMS 320 C 6713 ) MODELLING AND PROTOTYPING WITH SIMULINK GENERAL PROCEDURE: Step 1: Start MATLAB Step 2: Click simulink icon in the MATLAB Command Window . MODELING AND PROTOTYPING WITH SIMULINK AND CODE COMPOSER STUDIO WITH DSK AIM To model and prototype the conversion of basic waveforms using differentiator and integrator in Simulink and to implement the basic examples in DSP Kit using Code composer studio APPARATUS REQUIRED SOFTWARES 1.5 2. CODE COMPOSER STUDIO HARDWARE: 1.

Select File > New > Model in the Simulink Library Browser. Step 3: Create a new model .Step 3: Create a new model . Join all the blocks.Select File > New > Model in the Simulink Library Browser. Step 5: Click Start simulation icon in the created new file and double click the scope Step 6: Display Screen “Scope” will be opened and the respective output can be viewed. Step 4: From the Simulink Library Browser click simulink. Click “Continuous” under simulink.. Select “Sine waveform” and track it to the new file created. Select the sources required and track it to the new file created. Select “Scope” and track it to the new file created. Step 7: Errors and warnings will be displayed in the Mat lab Command Window. Step 5: Connect the blocks. Conversion of Basic waveforms using differentiator and integrator PROCEDURE Conversion of Basic waveforms using differentiator Step 1: Start MATLAB Step 2: Click simulink icon in the MAT LAB Command Window. B. Click “Sources” under Simulink. Step 4: From the Simulink Library Browser click simulink. Select “derivative dw /dt” and track it to the new file created. Step 6: Click Start simulation icon in the created new file and double click the scope Step 7: Display Screen “Scope” will be opened and the output Cosine waveform is viewed. Conversion of Basic waveforms using Integrator . A. Click “Sources” under simulink.

It is also used to explore the behavior of a wide range of real-world dynamic systems such as electrical circuits. Step 4: From the Simulink Library Browser click simulink. Select “Scope” and track it to the new file created.Step 1: Start MATLAB Step 2: Click simulink icon in the MATLAB Command Window Step 3: Create a new model .elect “Integrator 1/s” and track it to the new file created. Click “Sources” under Simulink.Select File > New > Model in the Simulink Library Browser. Click “Continuous” under simulink. Step 6: Click Start simulation icon in the created new file and double click the scope Step 7: Display Screen “Scope” will be opened and the output “Triangular” waveform is Viewed. Click “Sources” under simulink. OUTPUT Conversion of Sine waveform into Cosine waveform using Differentiator OUTPUT DISPLAY . simulate and analyze the systems whose outputs change over time. mechanical. Theory Simulink is a software package which enables to model. braking systems and many other electrical. Step 5: Connect the blocks. These systems are referred to as dynamic systems. Select “Square generator” and track it to the new file created. and thermodynamic systems. shock absorbers.

Conversion of Square waveform into Spikes using Differentiator OUTPUT DISPLAY Conversion of Sine waveform into Cosine waveform using Integrator OUTPUT DISPLAY .

Step 5: In “dsk6711” folder select the “Bios” file.C” program will be compiled Step 7: Goto “FILE” select “Load Program”. Select “Swiltest. click the icon “PROJECT” and select “open”.C “ Screen will be opened. Step 2: Code composer studio software to be opened. Click “Swill test”. Step 4: Enter into TI Folder.pjt”. Step 6: Goto “PROJECT” select “Rebuild all”. “Swiltest. Select “C “Drive. 5 (A &B) DELTA MODULATION AND ADAPTIVE DELTA MODULATION . The output file is viewed as “Swiltest. Step 8: Goto “DEBUG” icon select “Run” RESULT Thus the conversion of basic waveforms using differentiator and integrator is modeled in simulink and the procedures to work with DSK Kit using Code Composer studio is learned.Conversion of Square waveform into Triangular waveform using Integrator OUTPUT DISPLAY CODE COMPOSER STUDIO WITH DSK KIT PROCEDURE: Step 1: Connect adapter and power supply card to the System. Step 3: In the screen.out”. “Swiltest. Click “Examples” and enter into “dsk6711”.

else d(k)=-1. n=length(a). xhat(k+1)=xtilde(k). % Linear Delta Modulation for k=1: n if (x(k)-xhat(k)) > 0 d(k)=1. dels=1. 1: 2: 3: 4: 5: Start the program Get the length of the sinusoidal signal Compute the step size Plot the output sequence Terminate the process : MATLAB 7.0 or higher version .AIM To simulate the delta and Adaptive delta modulation using Mat lab. end %if xtilde(k)=xhat(k)+d(k)*dels. xhat(1:n)=0. TOOLS REQUIRED: Simulation ALGORITHM: Step: Step: Step: Step: Step: PROGRAM: DELTA MODULATION: % function to generate Linear Delta Modulation for sin wave % generating sin wave t=[0:2*pi/100:2*pi]. a=10*sin(t). d(1:n)=0. x(1:n)=a.

hold on. plot(a) plot(xhat). plot(d-15).end %k %Prints figure(1). axis([0 100 -20 20]) OUTPUT: 2 0 1 5 1 0 5 0 -5 -10 -15 -20 0 10 2 0 3 0 40 50 60 70 80 90 10 0 .

else d(k)=-1. n=length(a).15*(xhat(k)-xhat(k-1)).5*(xhat(k)-xhat(k-1)). .5*(xhat(k)-xhat(k-1)).PROGRAM: ADAPTIVE DELTA MODULATION: % adaptive delta modulation for sin wave % generating sin wave t=[0:2*pi/100:2*pi]. % Adaptive Delta Modulation d(1:n)=1. elseif (d(k-1) == 1 &d(k) ==1) xhat(k+1)=xhat(k)+1. for k=2:n if ((x(k)-xhat(k-1)) > 0 ) d(k)=1. elseif (d(k-1) == 1 &d(k) ==-1) xhat(k+1)=xhat(k)-0. mindels=1. x(1:n)=a. xhat(1:n)=0. dels(1:n)=mindels. a=10*sin(t). end if ((xhat(k)-xhat(k-1)) > 0) if (d(k-1) == -1 &d(k) ==1) xhat(k+1)=xhat(k)+0. end %if if k==2 xhat(k)=d(k)*mindels+xhat(k-1).

elseif (d(k-1) == 1 &d(k) ==-1) xhat(k+1)=xhat(k)+0.15*(xhat(k)-xhat(k-1)). plot(a). elseif (d(k-1) == -1 &d(k) ==-1) xhat(k+1)=xhat(k)+1. plot(xhat). elseif (d(k-1) == 1 &d(k) ==1) xhat(k+1)=xhat(k)-1. end end end %Plots figure(1).hold on.15*(xhat(k)-xhat(k-1)).5*(xhat(k)-xhat(k-1)).elseif (d(k-1) == -1 &d(k) ==-1) xhat(k+1)=xhat(k)-1.15*(xhat(k)-xhat(k-1)). plot(d-15) . end else if (d(k-1) == -1 &d(k) ==1) xhat(k+1)=xhat(k)-0.5*(xhat(k)-xhat(k-1)).

OUTPUT: 15 10 5 0 -5 -10 -15 -20 0 20 40 60 80 100 120 Result: Thus the Mat lab program was simulated for delta and adaptive modulation the waveforms are plotted. .

grayencod = bitxor(0:M-1. numPlot = 10. randn('state'. seed = [12345 54321]. floor((0:M-1)/2)). seed(2)). Open a Matlab new file and enter the corresponding codings for the qpsk transmitter and receiver. 'dB'). BER for QPSK PROGARM: %%%%%%%%%%%%PROGRAM FOR QPSK COSTELLATION %%%%%%%%% nSamp = 8. []. SNR = 14.nSamp). 1. 2. M = 4. SNR. msg_orig = randsrc(numSymb. 0:M-1). Save and run the mat lab file. ylabel('Amplitude'). 3. Obtain the corresponding output for QPSK constellation. h2 = scatterplot(msg_rx). numSymb = 100. randn('state'. msg_tx = modulate(modem. seed(2)). msg_orig(1:numPlot).pskmod(M). msg_tx = rectpulse(msg_tx. 'bx'). . xlabel('Time'). msg_gr_orig = grayencod(msg_orig+1). 'measured'. msg_gr_orig). h1 = scatterplot(msg_tx). stem(0:numPlot-1. seed(1)).0 PROCEDURE: 1. rand('state'.5(C) QPSK CONSTELLATION AIM To simulate the QPSK transmitter and receiver circuit and to obtain the constellation using MAT LAB TOOLS REQUIRED: MATLAB 7. rand('state'. seed(1)). msg_rx = awgn(msg_tx.

2 0 -0 . 5 0 -5 0 .6 -0 .2 -0 .4 -0 . 0 I-h na Pe s 0 .8 0 . 1 -5 0 .OUTPUT: Seo c rlt ap t t 1 . -5 1 . 1 -5 1 .4 Quadrature 0 . 5 1 1 .8 -1 -1 -0 .5 1 . 5 S tte p t ca r lo 1 0 .6 0 .5 0 In h se -P a 0 . 5 1 Q a r tue u da r 0 .

5 1 0 .3 2 .5 0 0 1 2 3 4 T e im 5 6 7 8 9 RESULT: Thus the corresponding plot for the QPSK constellation and BER were obtained. .5 2 Amplitude 1 .

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