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VLSI IEEE 2012-13 Project Titles

VLSI IEEE 2012-13 Project Titles

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The File consists of IEEE 2012 Papers in the VLSI Domain . This file is uploaded for the beneficial for the Final year students of BE / ME Students by Ms.Pantech Proed Pvt Ltd , Chennai . Should you require any Abstracts or any Clarifications , please call 9566043555 / 9566133338 for more info. Alternatively you can also mail to chennai@pantechmail.com
The File consists of IEEE 2012 Papers in the VLSI Domain . This file is uploaded for the beneficial for the Final year students of BE / ME Students by Ms.Pantech Proed Pvt Ltd , Chennai . Should you require any Abstracts or any Clarifications , please call 9566043555 / 9566133338 for more info. Alternatively you can also mail to chennai@pantechmail.com

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Published by: Kumarasamy Ramasubramanian on Jul 23, 2012
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08/17/2013

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VLSI

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SI.No
PSVLS 1 PSVLS 2 PSVLS 3 PSVLS 4 PSVLS 5 PSVLS 6 PSVLS 7 PSVLS 8 PSVLS 9 PSVLS 10 PSVLS 11 PSVLS 12 PSVLS 13 PSVLS 14 PSVLS 15 PSVLS 16 PSVLS 17 PSVLS 18 PSVLS 19 PSVLS 20 PSVLS 21 PSVLS 22 PSVLS 23 PSVLS 24 PSVLS 25

Topics
Real Time Hardware Co-simulation of Edge Detection for Video Processing System BPSK System on Spartan 3E FPGA Implementation of PSK and QAM demodulators on FPGA Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation Platform-Independent Customizable UART Soft-Core VLSI Architecture of Arithmetic Coder Used in SPIHT Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design Single Phase Clocked Quasi Static Adiabatic Tree Adder Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Submicron Circuits Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks Design of Low Voltage Low Power Operational Amplifier Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits A Novel Architecture for VLSI Implementation of RSA Cryptosystem FPGA Hardware of the LSB Steganography Method A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL An efficient FPGA implementation of the Advanced Encryption Standard algorithm A Novel Data Embedding Method Using Adaptive Pixel Pair Matching VHDL Implementation of a Flexible and Synthesizable FFT Processor An FPGA-Based Hardware Implementation of Configurable Pixel-Level Color Image Fusion Medical Image Fusion Based on Redundancy DWT and Mamdani Type Min-sum Mean-ofmax Techniques with Quantitative Analysis Edge Detection of Angiogram Images Using the Classical Image Processing Techniques Input/Output Peripheral Devices Control through Serial Communication using Microblaze Processor Variable Scaling Factor based Invisible Image Watermarking using Hybrid DWT – SVD Compression - Decompression Technique A Level Set Based Deformable Model for Segmenting Tumors in Medical Images

Field
IEEE 2012 (System Generator & Signal Processing) IEEE 2012 (Soft Core Processor Design)
14

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IEEE 2012 (Cryptography & Communication)

IEEE 2012 (Low Power Design)

VLSI

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PSVLS 26 PSVLS 27 PSVLS 28 PSVLS 29 PSVLS 30 PSVLS 31 PSVLS 32 PSVLS 33 PSVLS 34 PSVLS 35 PSVLS 36 PSVLS 37 PSVLS 38 PSVLS 39 PSVLS 40 PSVLS 41 PSVLS 42 PSVLS 43 PSVLS 44 PSVLS 45 PSVLS 46 PSVLS 47 PSVLS 48 PSVLS 49 PSVLS 50 PSVLS 51 PSVLS 52

Adaptive Steganalysis of Least Significant Bit Replacement in Grayscale Natural Images Analysis of CT and MRI Image Fusion using Wavelet Transform Design of Modified Low Power Booth Multiplier An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications Applications Parallel Architecture for Hierarchical Optical Flow Estimation Based on FPGA A Novel Architecture for an Efficient Implementation of Image Compression Using 2D-DWT Background Subtraction Algorithm for Moving Object Detection in FPGA Design and Implementation of the Discrete Wavelet Transform on an FPGA Platform to Process Data Sets of up to Three Dimensions Gesture Recognition Using Field Programmable Gate Arrays Median Filter on FPGAs An Autoadaptive Edge-Detection Algorithm for Flame and Fire Image Processing An Efficient Denoising Architecture for Removal of Impulse Noise in Images Real Time Smart Car Lock Security System Using Face Detection and Recognition Implementation of a Home Automation System through a Central FPGA Controller Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE New Clock Generation Techniques for Synchronous Sampling of 16-QAM RF Signals QPSK Modulator on FPGA Implementation of a QPSK System on FPGA Models Simulation based on HDL-Simulink Platform Simulation and Implementation of a BPSK Modulator on FPGA An improved three-factor authentication scheme using smart card with biometric privacy protection The Ship Monitoring and Control Network System Design Autonomous Navigation for an Unmanned Mobile Robot in Urban Areas A Generic Framework for Three-Factor Authentication: Preserving Security and Privacy in Distributed Systems A Low-Cost GPS&INS Integrated System Based on a FPGA Platform An embedded high sensitivity navigation receiver for GPS IEEE 2012 IEEE 2011 (Wireless Communication)
15

IEEE 2012 (Soft Core Processor Design) (Security & System Generator)

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VLSI

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PSVLS 53 PSVLS 54 PSVLS 55 PSVLS 56 PSVLS 57 PSVLS 58 PSVLS 59 PSVLS 60 PSVLS 61 PSVLS 62 PSVLS 63 PSVLS 64 PSVLS 65 PSVLS 66 PSVLS 67 PSVLS 68 PSVLS 69 PSVLS 70 PSVLS 71 PSVLS 72 PSVLS 73 PSVLS 74 PSVLS 75 PSVLS 76 PSVLS 77 PSVLS 78 PSVLS 79 PSVLS 80

Hardware Efficiency Comparison of AES Implementations Efficient Design and Implementation of FFT Enhancing NBTI Recovery in SRAM Arrays Through Recovery Boosting Design of Sequential Elements for Low Power Clocking System Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits Parameterized FPGA-Based Architecture For Parallel 1-D Filtering Algorithms A 11-Transistor Nanoscale CMOS Memory Cell for Hardening to Soft Errors Low Power Single Bitline 6T SRAM Cell With High Read Stability Low Power Subthreshold D Flip Flop Low Leakage Power SRAM Cell for Embedded Memory A Novel Low-Leakage 8T Differential SRAM Cell Adiabatic Technique for Energy Efficient Logic Circuits Design A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design Performance Analysis of Power Gating designs in Low Power VLSI Circuits Low-Power and Area-Efficient Carry Select Adder Operation Improvement of Indoor Robot by Gesture Recognition Improving ATM Security Via Face Recognition Design of Vehicle Positioning System Based on FPGA A Novel Area-Throughput Optimized Architecture for the AES Algorithm Thwarting Control-Channel Jamming Attacks from Inside Jammers Image Processing in Dynamic Reconfigurable Platform Real-Time Object Tracking System on FPGAs Memory-Efficient High-Speed Convolution-based Generic Structure for Multilevel 2-D DWT A Universal Background Subtraction Algorithm for Video Sequences A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform Power Efficient Motion Estimation Algorithm and Architecture Based on Pixel Truncation Architectural Implementation of High Speed Optical Flow Computation Based on LucasKanade Algorithm
16

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IEEE 2011 (Image Processing)

IEEE 2011 (Security Based)

IEEE 2011 (Low Power Design)

VLSI

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PSVLS 81 PSVLS 82 PSVLS 83 PSVLS 84 PSVLS 85 PSVLS 86 PSVLS 87 PSVLS 88 PSVLS 89 PSVLS 90 PSVLS 91 PSVLS 92 PSVLS 93 PSVLS 94 PSVLS 95 PSVLS 96 PSVLS 97 PSVLS 98 PSVLS 99

Discrete Wavelet Transform-Based Satellite Image Resolution Enhancement An Efficient Denoising Architecture for Removal of Impulse Noise in Images Dynamic Hand Gesture Recognition for Human- Computer Interactions Dynamic Power Estimation for Motion Estimation Hardware Realization of a LSB Information Hiding algorithm Based on Lifting Wavelet Transform Image Blind Image Watermarking Using a Sample Projection Approach A Novel Power Reduction Technique for Block Matching Motion Estimation Hardware An improved method of image edge detection based on wavelet transform Mathematical Morphological Edge Detection For Remote Sensing Images A New Adaptive Weight Algorithm for Salt and Pepper Noise Removal FPGA Implementation of AES Algorithm Wireless Jamming Attacks under Dynamic Traffic Uncertainty Car Monitoring, Alerting and Tracking Model FPGA-Based GPS Application System Design An Embedded System and RFID Solution For Transport Related Issues Keyless Car Entry through Face Recognition Using FPGA Design ofA M Modulation Signal Generator Based on Matlab/DSP Builder Ground Bounce Noise Reduction of Low leakage 1-bit Nano-CMOS based Full Adder Cells for Mobile Applications CMOS Full-Adders for Energy-Efficient Arithmetic Applications IEEE 2010 (Wireless communication) (Power Analysis)
17

PSVLS 100 Variability Resilient Low-power 7T-SRAM Design for nano-Scaled Technologies PSVLS 101 A Wide-Range All-Digital Delay-Locked Loop in 65nm CMOS Technology IEEE 2010 PSVLS 102 Dual Stack Method: A Novel Approach to Low Leakage and Speed Power Product VLSI Design PSVLS 103 Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems PSVLS 104 Optimal Design For Ground Bounce Noise Reduction Using Sleep Transistor PSVLS 105 A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip–Flops With Embedded Logic PSVLS 106 Design of A Low Power Flip-Flop Using CMOS Deep Submicron Technology PSVLS 107 A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems

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IEEE 2011 (Image Processing)

VLSI

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PSVLS 108 Optimization of Processor Architecture for Image Edge Detection Filter PSVLS 109 Flexible Hardware Architecture of Hierarchical K-Means Clustering for Large Cluster Number PSVLS 110 Message Encoding in Images Using Lifting Schemes PSVLS 111 Medical Image Retrieval using Energy Efficient Wavelet Transform PSVLS 112 A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform PSVLS 113 Design of Pipelined FFT Processor Based on FPGA PSVLS 114 An FPGA-based Architecture for Linear and Morphological Image Filtering PSVLS 115 Motion human detection based on background subtraction PSVLS 116 GPS-GSM Integration for Enhancing Public Transportation Management Services PSVLS 117 A Color Image Segmentation algorithm Based on Region Growing PSVLS 118 Reconfigurable Hardware for Median Filtering for Image Processing Applications PSVLS 119 Adaptive 2-D Wavelet Transform Based on the Lifting Scheme with Preserved Vanishing Moments PSVLS 120 Performance Evaluation of DES and Blowfish Algorithms PSVLS 121 A new and efficient algorithm for the removal of high density salt and pepper noise in images and videos PSVLS 122 Ocean Wave Observation by GPS Signal PSVLS 123 Performance Comparison and Analysis of PSK and QAM

IEEE 2010 (Image Processing)

18

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