UNIVERSITY DEPARTMENTS

ANNA UNIVERSITY CHENNAI : : CHENNAI 600 025 REGULATIONS - 2009 CURRICULUM I TO IV SEMESTERS (FULL TIME)

M.E. VLSI DESIGN
SEMESTER I SL. COURSE NO CODE THEORY 1 MA9109 2 3 4 5 6 AP9112 AP9113 AP9114 VL9111

COURSE TITLE Applied Mathematics for Electronics Engineers Digital CMOS VLSI Design Analog Integrated Circuit Design Statistical Signal Processing CAD for VLSI Circuits Elective I VLSI Design Laboratory–I TOTAL SEMESTER II

L 3 3 3 3 3 3 0 18

T 1 0 0 0 0 0 0 1

P 0 0 0 0 0 0 4 4

C 4 3 3 3 3 3 2 21

E1 PRACTICAL 7 VL9115

SL. COURSE NO CODE THEORY 1 AP9122 2 AP9154 3 4 5 6 E2 E3 E4

COURSE TITLE Digital Image Processing Computer Architecture Elective II Elective III Elective IV Elective V VLSI Design Laboratory- II TOTAL

L 3 3 3 3 3 3 0 18

T 0 0 0 0 0 0 0 0

P 0 0 0 0 0 0 4 4

C 3 3 3 3 3 3 2 20

E5 PRACTICAL 7 VL9125

1

SEMESTER III SL. COURSE NO CODE THEORY 1 E6 2 E7 E8 PRACTICAL 4 VL9134 3

COURSE TITLE Elective VI Elective VII Elective VIII Project Work - Phase I TOTAL

L 3 3 3 0 9

T 0 0 0 0 0

P 0 0 0 12 12

C 3 3 3 6 15

SEMESTER IV SL. COURSE NO CODE PRACTICAL 1 VL9141

COURSE TITLE Project Work – Phase II TOTAL

L 0 0

T 0 0

P 24 24

C 12 12

2

E. COURSE NO CODE THEORY 1. MA9125 2. COURSE TITLE Statistical Signal Processing CAD for VLSI Circuits Elective III VLSI Design Laboratory –I TOTAL L 3 3 3 0 9 T 0 0 0 0 0 P 0 0 0 4 4 C 3 3 3 2 11 3 . E2 L 3 3 3 9 T 1 0 0 1 P 0 0 0 0 C 4 3 3 10 COURSE TITLE Computer Architecture Elective I Elective II TOTAL SEMESTER III L 3 3 3 9 T 0 0 0 0 P 0 0 0 0 C 3 3 3 9 SL.2009 CURRICULUM I TO VI SEMESTERS (PART TIME) M. COURSE NO CODE THEORY 1. VL9115 3. E1 3. AP9114 2. AP9112 AP9113 COURSE TITLE Applied Mathematics for Electronics Engineers Digital CMOS VLSI Design Analog IC Design TOTAL SEMESTER II SL. VL9111 E3 PRACTICAL 4. AP9154 2. COURSE NO CODE THEORY 1. VLSI DESIGN SEMESTER I SL. 3.UNIVERSITY DEPARTMENTS ANNA UNIVERSITY CHENNAI : : CHENNAI 600 025 REGULATIONS .

VL9134 3. VL9125 3. COURSE NO CODE THEORY 1. AP9122 2. COURSE NO CODE PRACTICAL 1. VL9141 COURSE TITLE Project Work – Phase II TOTAL L 0 0 T 0 0 P 24 24 C 12 12 4 .SEMESTER IV SL. COURSE TITLE Elective VI Elective VII Elective VIII Project Work – Phase I TOTAL L 3 3 3 0 9 T 0 0 0 0 0 P 0 0 0 12 12 C 3 3 3 6 15 SEMESTER VI SL. COURSE TITLE Digital Image Processing Elective IV Elective V VLSI Design Laboratory. E6 2.II TOTAL L 3 3 3 0 9 T 0 0 0 0 0 P 0 0 0 4 4 C 3 3 3 2 11 SEMESTER V SL. COURSE NO CODE THEORY 1. E7 E8 PRACTICAL 4. E4 E5 PRACTICAL 4.

LIST OF ELECTIVES SL. Testing of VLSI Circuits Selected Topics in IC Design Design of Semiconductor Memories VLSI Technology Optimization Techniques and their Applications in VLSI Design RF System design Signal integrity for high speed design Data Converters Solid State Devices Modeling and Simulation Embedded Systems Introduction to MEMS System Design VLSI For Wireless Communications COURSE TITLE L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 5 . NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COURSE CODE CP9162 AP9152 VL9151 VL9152 AP9157 VL9153 VL9154 VL9155 CU9122 AP9153 AP9161 VL9156 CP9163 AP9163 VL9157 ASIC Design Hardware Software Co-Design VLSI Signal Processing.

New Delhi. 7th edition. An introduction. Prentice Hall of India Pvt. 2nd edition. UNIT III ONE DIMENSIONAL RANDOM VARIABLES 9 Random variables . T. New Delhi (2007). L = 45: T=15. Prentice – Hall of India. Sterling. Theory and applications. 2000..C. 2. Ltd. 7th Edition..Probability and Statistics for Engineers. W. Fuzzy sets and fuzzy logic. 6 . Mathematical methods and algorithms for signal processing. Uniform. New York (1985).Probability function – moments – moment generating functions and their properties – Binomial. Geometric. Miller & Freund. John Wiley and Sons. Fundamentals of Queueing theory. 5. .Toeplitz matrices and some applications. George J. Pearson education editions.. B.MA9109 C APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS LTP 3 1 04 UNIT I FUZZY LOGIC Classical logic – Multivalued logics – Fuzzy propositions – Fuzzy quantifiers. 9 UNIT II MATRIX THEORY 9 Some important matrix factorizations – The Cholesky decomposition – QR factorization – Least squares method – Singular value decomposition . Private Ltd. Richard Johnson. Asia.. 2002. Donald Gross and Carl M. UNIT V QUEUEING MODELS 9 Poisson Process – Markovian queues – Single and Multi-server Models – Little’s formula Machine Interference Model – Steady State analysis – Self Service queue. UNIT IV DYNAMIC PROGRAMMING 9 Dynamic programming – Principle of optimality – Forward and backward recursion – Applications of dynamic programming – Problem of dimensionality. 4. Poisson.. Taha. 1997. Operations Research. TOTAL: 45 PERIODS REFERENCES: 1..A. Klir and Yuan. Harris. Moon. 3. H.K. Pearson Education. Gamma and Normal distributions – Function of a Random Variable. Exponential.

Dynamic Logic Gates. Anantha Chandrakasan. 2.J. FPGA interconnect routing procedures. B Nikolic. K. Pipelines. Electrical properties of CMOS circuits and Device modelling. Speed and Area Tradeoffs UNIT V IMPLEMENTATION STRATEGIES 9 Full Custom and Semicustom Design. “ Principles of CMOS VLSI Design”. Stick diagram. 2000. “ Digital Integrated Circuits: A Design Perspective”. UNIT II COMBINATIONAL LOGIC CIRCUITS 9 Propagation Delays. Synchronous and Asynchronous Design. Barrel Shifters.Fox. Case Studies. Architectures for Adders. MOS and CMOS. Accumulators. Power Dissipation. UNIT III SEQUENTIAL LOGIC CIRCUITS 9 Static and Dynamic Latches and Registers. M J Smith. Prentice Hall of India. 1993 Addision Wesley. Addisson Wesley. Examples of combinational logic design. and Memory control circuits. Jan Rabaey. Bowhill and F. Second Edition. Standard Cell design and cell libraries. Clocking strategies. Multipliers. TOTAL : 45 PERIODS REFERENCES 1. Scaling principles and fundamental limits. Benchmark Circuits. UNIT IV DESIGNING ARITHMETIC BUILDING BLOCKS 9 Datapath circuits. Memory Architectures. Elmore’s constant. 1997 4. N.Weste. Pass Transistor Logic. Anantha Chandrakasan. Low Power Design principles. CMOS Inverter Scaling CMOS circuits. “Design of High Performance Microprocessor Circuits”. Feb 2003. Layout diagrams. W. “Application Specific Integrated Circuits”. John Wiley.AP9112 DIGITAL CMOS VLSI DESIGN L T PC 3 0 0 3 UNIT I MOS TRANSISTOR PRINCIPLES 9 MOS Technology and VLSI. FPGA building block architectures. 7 . Process parameters and considerations for. Eshraghian. Timing Issues. Second Edition. 3.

Input range limitations. noise in Op Amps. Differential pair. UNIT IV STABILITY AND FREQUENCY COMPENSATION 9 General considerations. DouglasR. Effect of loading in feedback networks. “CMOS Analog Circuit Design”. Frequency Compensation.Allen. 3. John Wiley & sons. noise in differential amplifiers. Common gate stage. Gain boosting.AP9113 ANALOG INTEGRATED CIRCUIT DESIGN L T PC 3 0 0 3 UNIT I SINGLE STAGE AMPLIFIERS 9 Common source stage. TOTAL : 45 PERIODS REFERENCES: 1. supply independent biasing. Two-stage Op Amps. “Bipolar and MOS Analog Integrated circuit design”. operational amplifier performance parameters. Tata McGraw Hill. 2006.Holberg.Association of poles with nodes. slew rate. Phillip E. Grebene. active current mirrors. noise in single stage amplifiers. Single ended and differential operation. Differential pair with MOS loads UNIT II FREQUENCY RESPONSE AND NOISE ANALYSIS 9 Miller effect . Slewing in two stage Op Amps. Common gate stage. UNIT V BIASING CIRCUITS 9 Basic current mirrors.Phase Margin. UNIT III OPERATIONAL AMPLIFIERS 9 Concept of negative feedback. Oxford University Press. Behzad Razavi. 2002 8 . Constant-Gm Biasing. Source followers. “Analog design essentials”. Other compensation techniques. 4. Basic differential pair. 2001 2.C.. Second edition. Statistical characteristics of noise. Cascode stage. 2003. power supply rejection. Source follower. cascode current mirrors. “Design of Analog CMOS Integrated Circuits”. frequency response of common source stage. voltage references. temperature independent references. PTAT current generation. Cascode stage.Inc. One-stage Op Amps. Springer. Multipole systems. Sansen. Compensation of two stage Op Amps. Willey M.

2004 (For Wavelet Transform Topic) 9 . Wiener filter for filtering and prediction. ‘Statistical Digital Signal Processing and Modeling”. Spectral factorization. Adaptive echo cancellation. AR and MA model based spectral estimation. Discrete Kalman filter UNIT IV ADAPTIVE FILTERS 9 FIR adaptive filters – adaptive filter based on steepest descent method. Rafael C.Periodogram.Ensemble Averages.. Filtering Random Processes. FIR and IIR Wiener filters. Bias and Estimation. Power Spectral Density. Autocovariance. Welch and Blackman-Tukey methods. MA – Yule-Walker equations. Autocorrelation. Proakis. Special types of Random Processes – ARMA. Solution using Levinson-Durbin algorithm UNIT III LINEAR ESTIMATION AND PREDICTION 9 Linear prediction – Forward and Backward prediction. Dimitris G. UNIT II SPECTRAL ESTIMATION 9 Estimation of spectra from finite duration signals. Gonzalez.Second Edition. “ Digital Image Processing”. 2002 3. Bartlett. Application to subband coding – Wavelet transform TOTAL : 45 PERIODS REFERENCES 1. Stationary processes. Pearson Education. : Digital Signal Processing’. Adaptive noise cancellation.AP9114 STATISTICAL SIGNAL PROCESSING LTPC 3 0 0 3 UNIT I DISCRETE RANDOM SIGNAL PROCESSING 9 Discrete Random Processes. Woods. Multistage implementation of multirate system. White noise. Parametric methods – ARMA. Solution of Prony’s normal equations. Modified periodogram. Parseval’s theorem. Normalized LMS algorithm. Interpolation by an integer factor. Singapore.Widrow-Hopf LMS algorithm. AR. Polyphase filter structures. Decimation by an integer factor. Pearson Education Inc. Inc. Monson H. UNIT V MULTIRATE DIGITAL SIGNAL PROCESSING 9 Mathematical description of change of sampling rate – Interpolation and Decimation. Manolakis. Adaptive channel equalization. Richard E. Wiener-Khintchine relation. John J. Sampling rate conversion by a rational factor. RLS adaptive algorithm. Hayes. John Wiley and Sons. 2002 2. Least mean-squared error criterion. Nonparametric methods .

2002.Assignment problem .A.shape functions and floorplan sizing . 2002. Sherwani. 2. TOTAL : 45 PERIODS REFERENCES 1.Simple scheduling algorithm .Two Level Logic Synthesis.global routing .Hardware models . UNIT II DESIGN RULES Layout Compaction .placement and partitioning .High level transformations.Tractable and Intractable problems .problem formulation . S. "Algorithms for VLSI Design Automation".Allocation assignment and scheduling .Binary Decision Diagrams . UNIT V MODELLING AND SYNTHESIS 9 High level Synthesis .H. UNIT IV SIMULATION 9 Simulation .Types of local routing problems .Switch-level modeling and simulation Combinational Logic Synthesis .Placement algorithms partitioning UNIT III FLOOR PLANNING 9 Floor planning concepts . 9 10 .channel routing . Gerez.Algorithmic Graph Theory and Computational Complexity .Internal representation .Area routing .algorithms for constraint graph compaction .Design rules . N. "Algorithms for VLSI Physical Design Automation".Circuit representation . John Wiley & Sons.Gate-level modeling and simulation . Kluwer Academic Publishers.general purpose methods for combinatorial optimization.Review of Data structures and algorithms Review of VLSI Design automation tools .VL9111 CAD FOR VLSI CIRCUITS L T P C 3 0 0 3 UNIT I VLSI DESIGN METHODOLOGIES 9 Introduction to VLSI Design methodologies .algorithms for global routing.

SPICE simulations for small size standard cells. Two stage Operational Amplifiers. 3. Structural and behavioral descriptions. Real time application development. source follower. scalability analysis and approaches. 2.VL9115 VLSI DESIGN LAB I L TP C 0 0 4 2 1. Test vector generation.the state of computing. principles of operation and limitation of Examples of sequential and combinational logic design and simulation. speedup performance laws. AP9154 COMPUTER ARCHITECTURE LTPC 3 003 UNIT I THEORY OF PARALLELISM 9 Parallel computer models . UNIT II PARTITIONING AND SCHEDULING 9 Program partitioning and scheduling.Conditions of parallelism. Parallel processing applications. PRAM and VLSI models. interpretation synthesis scripts.performance matrices and measures. Program and network properties. Synthesis principles. Multiprocessors and Multicomputers and Multivectors andSIMD computers. 6. System interconnect architectures. 5. constraint introduction and library preparation and generation.Common source amplifier. I/O interfacing. Design Entry Using VHDL or Verilog examples for circuit descriptions using HDL languages sequential and concurrent statements. Program flow mechanisms. standard cell based design and synthesis. SPICE simulations for analog circuit modules . Architectural development tracks. HDL simulators. cascode amplifiers. FPGA programming. Differential amplifiers. Principles of scalable performance . Analog interfacing. UNIT III HARDWARE TECHNOLOGIES 9 . logical effort. 4.

virtual memory technology. 3.DFT. ”Advanced Computer architecture – A design Space Approach” . superscalar and vector processors. Two dimensional mathematical preliminaries. Dezso Sima. Image restoration . Macmillan Publishing Company. MACH and OSF/1 for parallel computers. Quinn. Unconstrained and Constrained restoration. M. KLT. Discrete Sine. Image sampling. Geometric transformations-spatial transformations. “Modern processor design . McGraw Hill International. Spatial averaging. Haar. Vidicon and Digital Camera working principles. Kai Hwang. TOTAL: 45 PERIODS REFERENCES: 1. DCT. SVD. Peter Kacsuk. memory hierarchy technology. cache memory organisations. Directional Smoothing.backplane bus systems. Design of 2D FIR filters. " Advanced Computer Architecture ". Kai Hwang. 6. 2D transforms . UNIT III IMAGE ENHANCEMENT AND RESTORATION 9 Histogram modification. Harmonic mean. Region growing. Inverse filtering-removal of blur caused by uniform linear motion.degradation model. Multivector and SIMD computers. Scalable. 1994. . UNIT V SOFTWARE AND PARALLEL PROGRAMMING 9 Parallel models. Pearson education .Patterns and pattern . saturation. UNIX. sequential and weak consistency models. 1993. 1990. Region splitting and Merging. Quantization. shared memory organisations. Hadamard. “Computer Organization and Architecture”. “Scalable parallel computing”.Edge detection. Dither. Tata McGraw Hill 1998. Median.Processor and memory hierarchy advanced processor technology. McGraw Hill International. UNIT II IMAGE TRANSFORMS 9 1D DFT. Parallel program development and environments. 2. Noise distributions. Multithreaded and data flow architectures. Wiener filtering. “Designing Efficient Algorithms for Parallel Computers”.Shen. William Stallings. Mach Band effect. Multiprocessor and Multicomputers.Fundamentals of super scalar processors”. UNIT IV PIPELINING AND SUPERSCLAR TECHNOLOGIES 9 Parallel and scalable architectures. 2003. Elements of visual perception. Tata McGraw Hill 2003. 5. UNIT IV IMAGE SEGMENTATION AND RECOGNITION 9 Image segmentation . brightness. Terence Fountain. hue. 4. Image Recognition . Slant. Languages and compilers.J. Walsh. John P. Edge linking and boundary detection. Geometric mean. contrast. Gray Level interpolation. bus cache and shared memory . Contraharmonic and Yp mean filters .. AP9122 DIGITAL IMAGE PROCESSING L TPC 3 0 0 3 UNIT I DIGITAL IMAGE FUNDAMENTALS 9 Elements of digital image processing systems. Wavelet transform.

Vikas Publishing House. 2004. Algorithms and Architectures”. Inc. “Image Processing. Dudgeon and R. EZW. 2002. 2.. 2004 2. Pratt.E. Brookes/Cole. Pearson Education. Second Edition. LVS. “Multidimensional Digital Signal Processing”.. Anil K. Richard E. 4. Shift codes. ASIC RTL realization. JPEG standard. Matching by minimum distance classifier. 3. New York. M. Formal verification – MAGMA/CADENCE 5. 4. Layout generation for analog circuit modules. Transform coding.MAGMA/CADENCE. 1995. Milan Sonka et al. 7. D. Steven Eddins. William K. McGrawHill. layout generation. “Fundamentals of Digital Image Processing”. UNIT V IMAGE COMPRESSION 9 Need for data compression. Back annotation. Scan chain insertion. Mersereau.A. 2002. 1999. “ Image Processing Theory. Neural network to recognize shapes.II LTPC 0 0 4 2 VLSI based experiments using MAGMA / CADENCE / TANNER / XILINX / ALTERA / ACTEL 1. Richard E. “ Digital Image Processing”. Gonzalez. Matching by correlation. optimization for area. Woods. Prentice Hall of India. Jain. power – MAGMA/CADENCE. 6. 3. Interpretation of standard cell library descriptions. Woods. Inc. Arithmetic coding. 5. Critical path considerations – MAGMA/CADENCE. Boolean optimization. 2nd edition.” Digital Image Processing using MATLAB”. Pearson Education. Run Length Encoding..CADENCE / TANNER .classes. Rafael C. Floor Planning Routing and Placement procedures and Back annotation. 1990. Neural networks-Backpropagation network and training. Block Truncation Coding. John Wiley. Analysis and Machine Vision”. Sid Ahmed. Prentice Hall Professional Technical Reference. JPEG 2000. Static Timing analyses procedures and constraints. SPIHT. alternatives. MPEG. Rafael C. “ Digital Image Processing”.M.CADENCE/TANNER LVS. TOTAL : 45 PERIODS REFERENCES 1. Huffman. 6.. Gonzalez. Vector Quantization. VL9125 VLSI DESIGN LABORATORY .

Specific Integrated Circuits ".Altera FLEX –Design systems .J.D. UNIT V ASIC CONSTRUCTION. J. Uranesic. 2.Altera MAX 9000 . Y. SIMULATION AND TESTING 9 Verilog and logic synthesis -VHDL and logic synthesis .Smith.Data path logic cell . Addison -Wesley Longman Inc. .J. Prentice Hall. CMOS LOGIC AND ASIC LIBRARY DESIGN 9 Types of ASICs .PLA tools -EDIF. T.physical design flow –global routing . PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY 9 Actel ACT -Xilinx LCA . M.CP9162 ASIC DESIGN LTPC 3003 UNIT I INTRODUCTION TO ASICS. PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC I/O CELLS 9 Anti fuse .Transistors as Resistors .Altera MAX 5000 and 7000 .CFI design representation. " Analog VLSI Signal and Information Processing ".automatic test pattern generation.special routing circuit extraction . H. Rox.Design flow . Kung. " Design of Analog . 1994. " VLSI Circuits and Systems in Silicon". R. Mc Graw Hill. Prentice Hall. Andrew Brown.Xilinx LCA –Altera FLEX . Kailath. UNIT IV LOGIC SYNTHESIS.fault simulation .floor planning placement . Francis.Half gate ASIC -Schematic entry .detailed routing . J. 1997.FPGA partitioning .static RAM .Low level design language . 1994. France.Altera MAX DC & AC inputs and outputs Clock & Power inputs . UNIT II PROGRAMMABLE ASICS..CMOS transistors CMOS Design rules Combinational Logic Cell – Sequential logic cell . Z.types of simulation -boundary scan test . FLOOR PLANNING.Transistor Parasitic Capacitance. TOTAL : 45 PERIODS REFERENCES 1. S. 4. S.Xilinx I/O blocks. 1985. 1991 3. UNIT III PROGRAMMABLE ASIC INTERCONNECT. " Application .Digital VLSI Circuits for Telecommunication and Signal Processing ". Brown.Logical effort –Library cell design Library architecture . McGraw Hill. Jose E. Whilo House.S .Logic Synthesis . Yannis Tsividis. 6. PLACEMENT AND ROUTING 9 System partition . “Field Programmable Gate Arrays” Kluwer Academic Publishers. " VLSI and Modern Signal Processing ". 1992. Mohammed Ismail and Terri Fiez.partitioning methods .EPROM and EEPROM technology . 5.DRC.Xilinx EPLD .G. Introduction to JTAG.PREP benchmarks Actel ACT .

Heterogeneous Specification and Multi-Language Cosimulation TOTAL : 45 PERIODS REFERENCES 1. Ralf Niemann .AP9152 HARDWARE / SOFTWARE CO-DESIGN L T P C 3 00 3 UNIT I SYSTEM SPECIFICATION AND MODELLING 9 Embedded Systems . Kluwer Academic Pub. State-Transition Graph.Architecture Specialization Techniques . Generation of the Partitioning Graph .Future Developments in Emulation and Prototyping . Architectures for Data-Dominated Systems . 3.Mixed Systems and Less Specialized Systems UNIT V DESIGN SPECIFICATION AND VERIFICATION 9 Concurrency. “Hardware/Software Co-Design for Data Flow Dominated Embedded Systems”.Target Architecture.”Hardware/Software Co-Design: Principles and Practice” .Requirements for Embedded System Specification . Verification .2001. Refinement and Controller Generation. .Design Representation for System Level Synthesis.Processor Synthesis . HW/SW Partitioning based on Heuristic Scheduling. HW/SW Partitioning based on Genetic Algorithms . Single-Processor Architectures with one ASIC . Rolf Ernst Morgon. Coordinating Concurrent Computations. 1998. System Level Specification Languages. Giovanni De Micheli . UNIT III HARDWARE/SOFTWARE CO-SYNTHESIS 9 The Co-Synthesis Problem. Hardware/Software Cost Estimation. CoDesign for Heterogeneous Implementation . Optimization . Co-Design for System Specification and Modelling .” Reading in Hardware/Software CoDesign “ Kaufmann Publishers. UNIT II HARDWARE/SOFTWARE PARTITIONING 9 The Hardware/Software Partitioning Problem. Co-Design for System Specification and Modeling . Prototyping and Emulation Techniques . Languages for System-Level Specification and Design System-Level Specification . Kluwer Academic Pub. Distributed System Co-Synthesis UNIT IV PROTOTYPING AND EMULATION 9 Introduction. Wayne Wolf .Prototyping and Emulation Environments . Comparison of Co-Design Approaches .System Communication Infrastructure. The Hardware/Software Partitioning Problem . Architectures for Control-Dominated Systems. Hardware/Software Co-Design . Target Architectures and Application System Classes. Formulation of the HW/SW Partitioning Problem . Interfacing Components. Jorgen Staunstrup . Single-Processor Architectures with many ASICs. Models of Computation .1997. 2. MultiProcessor Architectures .

CSD multiplication using Horner’s rule for precision improvement. modified Cook-Took algorithm. scaling and roundoff noise computation. Bit-Level Arithmetic Architectures. two-phase clocking. short-circuit current of an inverter. iterative matching. parallel architectures for rank-order filters. multiple constant multiplications. roundoff noise in pipelined first-order filters. combined pipelining and parallel processing of IIR filters. Algorithmic strength reduction in filters and transforms – 2-parallel FIR filter. clock skew in edge-triggered single-phase clocking. Look-Ahead pipelining with power-oftwo decomposition.Sort architecture. Low power Design – needs for low power VLSI chips. Pipelined and parallel recursive and adaptive filters – inefficient/efficient single channel interleaving. pipelined adaptive digital filters. roundoff noise.’ Kluwer Academic Publishers. pipelined LMS adaptive filter. Inter Science. relaxed look-ahead. loop bound and iteration bound. bit-serial FIR filter. UNIT IV BIT-LEVEL ARITHMETIC ARCHITECTURES 9 Scaling and roundoff noise. Longest path Matrix algorithm.VL9151 VLSI SIGNAL PROCESSING LTPC 3 0 0 3 UNIT I INTRODUCTION TO DSP SYSTEMS 9 Introduction To DSP Systems -Typical DSP algorithms. Clustered Look-Ahead pipelining.order IIR filters.synchronous pipelining and clocking styles. basic principles of low power design. UNIT V PROGRAMMING DIGITAL SIGNAL PROCESSORS 9 Numerical Strength Reduction – subexpression elimination. UNIT III FAST CONVOLUTION 9 Fast convolution – Cook-Toom algorithm. UNIT II RETIMING 9 Retiming . CMOS leakage current. asynchronous pipelining bundled data versus dual rail protocol. Wave and asynchronous pipelining. state variable description of digital filters. wave pipelining. Pipelining and parallel processing – Pipelining of FIR digital filters. Synchronous. parallel carry-ripple array multipliers. Design and implementation ".Ahead pipelining in first. " VLSI Digital Signal Processing systems. DCT algorithm architecture transformation. Unfolding – an algorithm for Unfolding.Even Merge. ‘Practical Low Power Digital VLSI Design.definitions and properties. parallel processing of IIR filters. charging and discharging capacitance. 2.scaling operation. TOTAL : 45 PERIODS REFERENCES 1. Wiley. parallel processing. Programming Digital Signal Processors – general architecture with important features. sample period reduction and parallel processing application. 2-parallel fast FIR filter. .parallel multipliers with sign extension. properties of unfolding. pipelining and parallel processing for low power. CSD representation. Iteration Bound – data flow graph representations. 1999. design of Lyon’s bit-serial multipliers using Horner’s rule. Look. 4x 4 bit Baugh-Wooley carry-save multiplication tabular form and implementation.Parhi. Odd. parallel carry-save multiplier. Keshab K. parallel rank-order filters. Linear transformations. Gary Yeap. 1998.

"Essentials of Electronic Testing for Digital. 1994.Test algorithms . P.Fault Diagnosis for Combinational Circuits . 4. UNIT III DESIGN FOR TESTABILITY 9 Design for Testability . Kailath. Jose E.Delay models . Mc Graw-Hill. Prentice Hall. M. 2002.Test pattern generation for BIST . S.Circular BIST . M. A.Types of simulation . 2002. H. Lala. "Digital Circuit Testing and Testability".Classical scan based design .J.Testable combinational logic circuit design . Prentice Hall.Fault location . TOTAL : 45 PERIODS REFERENCES: 1.BIST Architectures . White House.System Level Diagnosis.Modeling of faults .A. 1994. Prentice Hall International. Friedman. 4. " VLSI and Modern Signal Processing ".System level DFT approaches.Test generation for Embedded RAMs. VL9152 TESTING OF VLSI CIRCUITS L T PC 3 0 0 3 9 UNIT I BASICS OF TESTING AND FAULT MODELLING Introduction to Testing . 1985.Y. M. Abramovici.Fault dominance . 2002.Test generation for sequential circuits . UNIT II TEST GENERATION FOR COMBINATIONAL AND SEQUENTIAL CIRCUITS 9 Test generation for combinational logic circuits .Diagnosis by UUT reduction . Bushnell and V. . "Design Test for Digital IC's and Embedded Core Systems". Crouch.Fault detection . Academic Press. France. 2.Faults in digital circuits .L. Jaico Publishing House. T. Yannis Tsividis.Testable Memory Design .D.L. "Digital Systems and Testable Design".D. Breuer and A.Gate level Event-driven simulation. " Analog VLSI Signal and Information Processing ". " Design of Analog . Kluwer Academic Publishers.Digital VLSI Circuits for Telecommunication and Signal Processing ". Kung.K. UNIT V FAULT DIAGNOSIS 9 Logic Level Diagnosis . 5. UNIT IV SELF-TEST AND TEST ALGORITHMS 9 Built-In Self Test . 2002. 3. Mohammed Ismail and Terri Fiez. Memory and Mixed-Signal VLSI Circuits".Logic Simulation .Self-checking design .Logical Fault Models .3.Ad-hoc design . Agrawal.Generic scan based design .design of testable sequential circuits.

nonideal effects in PLLs. Dual-loop architecture with external reference. 2003. Arthur H. Behzad Razavi. Dual-VCO Architecture. Delay locked loops. Rincon-Mora. UNIT IV PHASE LOCK LOOPS 9 Basic PLL topology. M. Frequency multiplication and synthesis. Effect of resistors temperature coefficient on a reference. jitter in CDR circuits. voltage controlled oscillators. Voltage references. LC oscillators. skew reduction. speed Clock and Data Recovery. UNIT II PRECISION REFERENCE CIRCUITS 9 Error source. distributed oscillators. . Mc Graw Hill. Designing for power supply rejection and line regulation. Full rate referenceless architecture. Ring oscillators. "Voltage references from diode to precision higher order bandgap circuits”. state-of-the-Art Curvature-correction techniques. Quadrature oscillators. UNIT V CLOCK AND DATA RECOVERY 9 General considerations. The output stage. van Roermund. Inc 2002. UNIT III OSCILLATOR FUNDAMENTALS 9 General considerations. mathematical model of VCOs.independent current references. High-performance Amplifiers Power Management “ springer.A. Gabriel. Jitter reduction. CTAT current references.AP9157 SELECTED TOPICS IN IC DESIGN LTPC 3 0 03 UNIT I VOLTAGE AND CURRENT REFERENCES 9 PTAT current references. Temperature. TOTAL : 45 PERIODS REFERENCES 1. 4. Zero-order references. Herman Casier “Analog Circuit Design High3. first order references. Phase detectors for random data. frequency detectors for random data. 2. Second-order references. startup circuits and frequency compensation. PTAT current generators. monolithic varactors. “ Design of Integrated circuits for Optical Communications”. Michiel Steyaert . 2008. Charge-Pump PLLs.John wiley & Sons. monolithic inductors.

Specific DRAMs.Radiation Dosimetry-Water Level Radiation Testing and Test Structures. Tegze P. b. RAM Fault Modeling.VL9153 DESIGN OF SEMICONDUCTOR MEMORIES LTPC 3003 UNIT I RANDOM ACCESS MEMORY TECHNOLOGIES 9 Static Random Access Memories (SRAMs): SRAM Cell Structures-MOS SRAM Architecture-MOS SRAM Cell and Peripheral Circuit Operation-Bipolar SRAM Technologies-Silicon On Insulator (SOI) Technology-Advanced SRAM Architectures and Technologies-Application Specific SRAMs. Psuedo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and Testing-Application Specific Memory Testing. Betty Prince. Kluwer Academic publishers. Random Access Memories (MRAMs)-Experimental Memory Devices. Kluwer Academic publishers. TESTING. New Delhi. Ferroelectric Random Access Memories (FRAMs)-Gallium Arsenide (GaAs) FRAMs-Analog Memories-Magnetoresistive.Prentice-Hall of India Private Limited. “ Emerging Memories: Technologies and Trends”. Memory Hybrids and MCMs (2D)-Memory Stacks and MCMs (3D)-Memory MCM Testing and Reliability IssuesMemory Cards-High Density Memory Packaging Future Directions. " Semiconductor Memories Technology. 1997. UNIT V PACKAGING TECHNOLOGIES 9 Radiation Effects-Single Event Phenomenon (SEP)-Radiation Hardening TechniquesRadiation Hardening Process and Design Issues-Radiation Hardened Memory Characteristics-Radiation Hardness Assurance and Testing . Pseudo Random Testing-Megabit DRAM Testing-Nonvolatile Memory Modeling and Testing-IDDQ Fault Modeling and TestingApplication Specific Memory Testing UNIT IV RELIABILITY AND RADIATION EFFECTS 9 General Reliability Issues-RAM Failure Modes and Mechanism-Nonvolatile Memory Reliability-Reliability Modeling and Failure Rate Prediction-Design for ReliabilityReliability Test Structures-Reliability Screening and Qualification.Programmable Road-Only Memories (EPROMs)-Floating-GateEPROM Cell-One-Time Programmable (OTP) EPROMs-Electrically Erasable PROMs (EEPROMs)-EEPROM Technology And Arcitecture-Nonvolatile SRAM-Flash Memories (EPROMs or EEPROM)-Advanced Flash Memory Architecture. UNIT II NONVOLATILE MEMORIES 9 Masked Read-Only Memories (ROMs)-High Density ROMs-Programmable Read-Only Memories (PROMs)-BipolarPROMs-CMOS PROMs-Erasable (UV) . 2002. Ashok K.Haraszti. c. DRAMs-Soft Error Failures in DRAMs-Advanced DRAM Designs and Architecture-Application. AND MEMORY DESIGN FOR TESTABILITY AND FAULT TOLERANCE 9 RAM Fault Modeling. UNIT III MEMORY FAULT MODELING. Dynamic Random Access Memories (DRAMs): DRAM Technology Development-CMOS DRAMs-DRAMs Cell Theory and Advanced Cell Strucutures-BiCMOS. TOTAL:45 PERIODS REFERENCES a. “CMOS Memory Circuits”. 2001. .Sharma. Testing and Reliability ". Electrical Testing. Electrical Testing.

Growth Mechanism and kinetics. 2002. Amar Mukherjee. Thin Oxides.Wayne Wolf . Redistribution of Dopants at interface. Models of Diffusion in Solids.2000.Hill Second Edition. TOTAL : 45 PERIODS REFERENCES 1. processing consideration. Prentice Hall India 2003. Silicon on Insulators.VL9154 VLSI TECHNOLOGY LTPC 3 0 03 UNIT I CRYSTAL GROWTH. Prentice Hall India.Chemical methods – Package types – banking design consideration – VLSI assembly technology – Package fabrication technology.NMOS IC Technology – CMOS IC Technology – MOS Memory IC technology . Molecular Beam Epitaxy. UNIT II LITHOGRAPHY AND RELATIVE PLASMA ETCHING 9 Optical Lithography. “VLSI Technology”. Electron Lithography. 2. Plasma properties. Silicon Shaping. Czochralski crystal growing. Pucknell and Kamran Eshraghian. plasma assisted Deposition. EPITAXY AND OXIDATION 9 Electronic Grade Silicon. relative Plasma Etching techniques and Equipments. ION IMPLEMENTATION AND METALISATION 9 Deposition process. . “Introduction to NMOS and CMOS VLSI System design Prentice Hall India. 4.Implant equipment. UNIT III DEPOSITION.Bipolar IC Technology – IC Fabrication. DIFFUSION.M.Sze. Mc. Ion Lithography. Oxidation of Poly Silicon. 3. Oxidation induced Defects. Feature Size control and Anisotropic Etch mechanism.”Modern VLSI Design”. S. Annealing Shallow junction – High energy implantation – Physical vapour deposition – Patterning. Douglas A. UNIT IV PROCESS SIMULATION AND VLSI PROCESS INTEGRATION 9 Ion implantation – Diffusion and oxidation – Epitaxy – Lithography – Etching and Deposition.Range theory. Vapor phase Epitaxy. UNIT V ASSEMBLY TECHNIQUES AND PACKAGING OF VLSI DEVICES 9 Analytical Beams – Beams Specimen interactions . Polysilicon. “ Basic VLSI Design”. Epitaxial Evaluation. WAFER PREPARATION. X-Ray Lithography.Graw. 4. Flick’s one dimensional Diffusion Equation – Atomic Diffusion Mechanism – Measurement techniques .1998. Oxide properties. Oxidation Techniques and Systems.

interconnect delay models UNIT II STATISTICAL PERFORMANCE. convex functions. dynamic power. 2.Monomial fitting. Cambridge University Press. High level yield estimation and gate level yield estimation UNIT III CONVEX OPTIMIZATION 9 Convex sets. Floor planning. Lieven Vandenberghe “ Convex Optimization”. TOTAL : 45 PERIODS REFERENCES 1. Posynomial fitting. Monte Carlo techniques. E. wire sizing.fitness function-GA vs Conventional algorithm. parameter space techniques. leakage power.monomial fitting. POWER AND YIELD ANALYSIS 9 Statistical timing analysis. 3. David Blaauw “Statistical Analysis and Optimization for VLSI:Timing and Power” . Springer. Max.Mrudnick.1998. Prentice Hall. Stephen Boyd. temperature and power supply variations. Generalized geometric programming. Approximation and fitting. Layout and Test automation. Process variation modelingPelgrom’s model. “Genetic Algorithm for VLSI Design.Automatic test generation. UNIT IV GENETIC ALGORITHM 9 Introduction. trade-off and sensitivity analysis. Principal component based modeling.Power estimation-application of GA-Standard cell placement-GA for ATG-problem encoding. Ashish Srivastava. High level statistical analysis. 2004.Layout and test Automation”. GA Technology-Steady State Algorithm-Fitness Scaling-Inversion GA for VLSI Design. geometric programming. Bayesian networks Leakage models. delay modeling.routing technology. . Quad tree based modeling. geometric programming applied to digital circuit gate sizing.Mapping for FPGA. UNIT V GA ROUTING PROCEDURES AND POWER ESTIMATION 9 Global routing-FPGA technology mapping-circuit generation-test generation in a GA frame work-test generation procedures. Performance modeling-Response surface methodology. Gate level statistical analysis. Dennis Sylvester.Partitioning algorithm Taxonomy-Multiway Partitioning Hybrid genetic-encoding-local improvement-WDFRComparison of Cas-Standard cell placement-GASP algorithm-unified algorithm.partitioning-automatic placement. Pinaki Mazumder. 2005.VL9155 OPTIMIZATION TECHNIQUES AND THEIR APPLICATIONS IN VLSI DESIGN LTPC 3 00 3 UNIT I STATISTICAL MODELING 9 Modeling sources of variations.

Phase noise Specification distribution over a communication link. Multiplier based mixers. subsampling mixers. IP2. Quadratic mixers. 3. Impedance matching networks. Passive IC components. Common Source Amplifiers. Compensation. Noise Figure. Power amplifier Linearisation Techniques. Noise properties. Noise: Thermal. Jan Crols. Time and Frequency domain considerations . Power match and Noise match. 2. 2001. Homodyne Receiver. Two port Noise theory. TRANSCEIVER SPECIFICATIONS AND ARCHITECTURES 9 Introduction to MOSFET Physics. popcorn noise. Direct Digital Frequency synthesizers UNIT V MIXERS AND OSCILLATORS 9 Mixer characteristics. OC Time constants in bandwidth estimation and enhancement. Image reject. Cambridge. THD.Lee. E and F amplifiers. T. Low IF Receiver Architectures Direct upconversion Transmitter. Phase noise. “Design of Analog CMOS Integrated Circuits”. C. Loop filters and Charge pumps. flicker. Efficiency boosting techniques.Razavi. ACPR metric. AB.Razavi. High frequency amplifier design. Resonators. Kluwer Academic Publishers. Two step upconversion Transmitter UNIT II IMPEDANCE MATCHING AND AMPLIFIERS 9 S-parameters with Smith chart. TOTAL : 45 PERIODS TEXT BOOKS 1. Oscillators describing Functions. Root-locus techniques. “Design of CMOS RF Integrated Circuits”. B. Single ended and Differential LNAs. Phase detectors. 2004. . Non-linear based mixers. Terminated with Resistors and Source Degeneration LNAs. shot. “RF Microelectronics”. Tuned Oscillators. 4. Colpitts oscillators. 1997. Sensitivity. McGraw Hill. Pearson Education. 1997. General model – Class A. Michiel Steyaert. D. Heterodyne Receiver. Design considerations UNIT IV PLL AND FREQUENCY SYNTHESIZERS 9 Linearised Model. UNIT III FEEDBACK SYSTEMS AND POWER AMPLIFIERS 9 Stability of feedback systems: Gain and phase margin. Negative resistance oscillators. B. B. Common Gate. IP3.CU9122 RF SYSTEM DESIGN L T P C 3 0 0 3 UNIT I CMOS PHYSICS. Single balanced and double balanced mixers. “CMOS Wireless Transceiver Design”. SFDR. Integer-N frequency synthesizers.

html 2. Hall. via transitions . C . per unit length parameters. Prentice Hall. termination. dispersion UNIT II MULTI-CONDUCTOR TRANSMISSION LINES AND CROSS-TALK 9 Multi-conductor transmission-lines.SPICE. Signal Integrity – Simplified .Near and far-end cross-talk..AP9153 SIGNAL INTEGRITY FOR HIGH SPEED DESIGN L T P C 3 0 0 3 UNIT I SIGNAL PROPAGATION ON TRANSMISSION LINES 9 Transmission line equations. Graham.com . reflection coefficient. PCB layer stackups and layer/Cu thicknesses. Clock slew. SPECCTRAQUEST from Cadence. G. Transmission line losses – Rs.com/products/ mixedsignal/hspice/hspice. High-Speed Digital Design: A Handbook of Black Magic. per unit length parameters . routing parasitic. Zo and Td equations for microstrip and stripline Reflection and terminations for logic gates. differential-mode current . static field maps of micro strip and strip line cross-sections. reflection. IBIS models . McCall. Wiley-Interscience.Timing analysis UNIT V CLOCK DISTRIBUTION AND CLOCK OSCILLATORS 9 Timing margin. 2003. Eye diagrams .http://www-cad.Bit streams. www.eecs. Prentice Hall PTR . 2003. Logic families and speed Package types and parasitic . canceling parasitic capacitance. cross-sectional analysis tools.synopsys. S. wave propagation. inter-symbol interference Bit-error rate . wave solution. jitter . http://www. TOTAL =45 PERIODS REFERENCES 1. High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices. delay time. tanδ . and bounce diagrams Reactive terminations – L. wave vs. Lossy and Lossles models UNIT III NON-IDEAL EFFECTS 9 Non-ideal signal return paths – gaps. balanced circuits . Hall. source . power consumption. terminations.specctraquest. Logic families.S-parameters. Eric Bogatin . TOOLS REQUIRED 1. fan-out. SPICE. logic switching . 1993.html 3. BGA fields. and J. 2000. PRBS and filtering functions of link-path components . Johnson and M. DC power bus design . W.berkeley. H. skin-effect. 4. Parasitic inductance and capacitance . Signal Integrity Issues and Printed Circuit Board Design.edu/Software/software. and system power delivery . initial wave. Delay Adjustments. coupling physics. minimizing cross-talk (stipline and microstrip) Differential signalling. layer stack up. SMT decoupling . Characteristic impedance . 2. circuits.Common-mode current. 3. Prentice Hall PTR. Connectors UNIT IV POWER CONSIDERATIONS AND SYSTEM DESIGN 9 SSN/SSO . Douglas Brooks. input impedance into a transmission-line section. Clock jitter. low impedance drivers. HSPICE from synopsis.

Op Amp offset cancellation. 1995. Single stage amplifier as comparator. Rudy van de Plassche. Successive approximation architecture. “Data Converters”. Time interleaved architecture. range overlap and digital correction. switched capacitor integrator. Springer. 2. Flash architecture. Converters” Behzad Razavi. current steering DAC architecture. “Principles of data conversion system design”. Open loop architecture with miller compensation. switched capacitor common mode feedback. Pipelined Architecture. Franco Maloberti. reference multiplication and division. latched comparators. Resistor ladder DAC architecture. Conventional open loop and closed loop sample and hold architecture. multiplexed input architectures. TOTAL=45 PERIODS REFERENCES 1. 2003. . 2007.AP9161 DATA CONVERTERS L T P C 3 0 0 3 UNIT I SAMPLE AND HOLD CIRCUITS 9 Sampling switches. UNIT IV ANALOG TO DIGITAL CONVERSION 9 Performance metric. recycling architecture switched capacitor architecture. Boston. UNIT V PRECISION TECHNIQUES 9 Comparator offset cancellation. switching and logic functions in DAC. “CMOS Integrated Analog-to-Digital and Digital-to-Analog Kluwer Acedamic Publishers. UNIT II SWITCH CAPACITOR CIRCUITS AND COMPARATORS 9 Switched-capacitor amplifiers. UNIT III DIGITAL TO ANALOG CONVERSION 9 Performance metrics. Calibration techniques. cascaded amplifier stages as comparator. IEEE press. 3.

RF model. High frequency behavior of MOS transistor and A. Thermal noise modeling. Enz. modeling parasitic BJT. modeling of device mismatch for Analog/RF Applications. 2003.Advanced MOSFET modeling. Threshold voltage model. Capacitors. Tor A. noise model temperature effects. Yuhua Cheng . I-V model. 2.VL9156 SOLID STATE DEVICE MODELING AND SIMULATION LTPC 3 0 0 3 UNIT I MOSFET DEVICE PHYSICS 9 MOSFET capacitor. Eric A. long channel drain current model. modeling second order effects of the drain current. Non-quasi-static modeling.C small signal modeling. MOSAI model) UNIT V MODELLING OF PROCESS VARIATION AND QUALITY ASSURANCE 9 Influence of process variation. calculation of distortion in analog CMOS circuits UNIT III BSIMV4 MOSFET MODELING 9 Gate dielectric model. noise model. “Charge-based MOS Transistor Modeling The EKV model for low-power and RF IC design”. Equivalent circuit representation of MOS transistor. Basic modeling. High speed model. 2006. Resistors. MOS model 9. UNIT IV OTHER MOSFET MODELS 9 The EKV model. RF modeling of MOS transistors. John Wiley & Sons. Capacitance models. . Flicker noise modeling. model for accurate distortion analysis. Vittoz. John Wiley & Sons Ltd. Benchmark circuits for quality assurance. Source/drain resistance model. junction diode models. model parameter extraction. Channel charge model. Ltd. Fjeldly and Wayne Wolf. modeling of charge storage effects. nonlinearities in CMOS devices and modeling. UNIT II NOISE MODELING 9 Noise sources in MOSFET. Inductors. gate tunneling current model. substrate current models. model features. Enhanced model for effective DC and AC channel length and width. Basic operation. Layout-dependent parasitics model. mobility model. “Device Modeling for Analog and RF CMOS Circuit Design”. Christian C. Automation of the tests TOTAL:45 PERIODS REFERENCES 1. Trond Ytterdal.

John Wiley & Sons. Network-Based design. Hardware platform design. Design Example: Elevator Controller. CPU Bus configuration. UNIT II EMBEDDED PROCESSOR AND COMPUTING PLATFORM 9 Data operations. System Integration. ARM Bus. parallelism with instructions. Myrinet. TOTAL : 45 PERIODS REFERENCES 1. 2. Internet. Architectural Design. Behavioural Description. G.W. Allocation and scheduling. Formalism for System Design. designing with microprocessor development and debugging. UNIT V SYSTEM DESIGN TECHNIQUES 9 Design Methodologies. Set-top Boxes. Specification. system performance Analysis. Liu.Memory organization. McGraw-Hill. Hybrid Architecture UNIT III NETWORKS 9 Distributed Embedded Architecture. Ink jet printer. M. SHARC Bus. Design Example: Model Train Controller.Communication Analysis. Jane. Requirement Analysis.Hardware Design and Software Design. Flow of Control. Quality Assurance. Frank Vahid and Tony Givargis. Product literature . “Computers as Components: Principles of Embedded Computing System Design”. “Embedded System Design: A Unified Hardware/Software Introduction” . CAN Bus. Priority driven Approach. 5. Design Example: Telephone PBX. Morgan Kaufman Publishers. ARM processorprocessor and memory organization. weighted round robin Approach.Structural Description. Component interfacing. Ethernet. System Analysis and Architecture Design.I2C. effective release times and deadlines.Hardware and Software Architectures. UNIT IV REAL-TIME CHARACTERISTICS 9 Clock driven Approach. Optimality of the Earliest deadline first (EDF) algorithm. Specification. “Real-Time systems”. Challenges in Embedded Computing system design. Data operations. Input/output devices. Networks for embedded systems. Personal Digital Assistants. Off-line Versus On-line scheduling. Design Example : Alarm Clock. Krishna and K. challenges in validating timing constraints in priority driven systems. Embedded system design processRequirements. SHARC processor. Flow of Control. Dynamic Versus Static systems. C. Designing Hardware and Software Components. 3. Shin. 1997 4. Wayne Wolf.System Architecture. “Real-Time Systems” . Memory devices. Characteristics of Embedded Computing Applications. SHARC link supports.S. Pearson Education Asia.CP9163 C EMBEDDED SYSTEMS L T P 3 0 0 3 UNIT I EMBEDDED PROCESSORS 9 Embedded Computers.

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Spring configurations. 2002. Microaccelorometers and Micro fluidics. Digital Micro mirror devices.Mohamed Gad-el-Hak.2000. CRC press Baco Raton. Artech House. TOTAL : 45 PERIODS TEXT BOOK 1. Circuit and system issues. resolution. Micro fabrication UNIT II MECHANICS FOR MEMS DESIGN 9 Elasticity. rotary motors. UNIT III ELECTRO STATIC DESIGN 9 Electrostatics: basic theory. 2000. Bending of thin plates. force and response time. inch worms. matrix operations.Tai Ran Hsu. Case studies – Capacitive accelerometer. Micro sensors. strain and material properties. .Stephen Santuria. REFERENCES 1. gap closers. . Case studies. Surface tension. Noise .AP9163 INTRODUCTION TO MEMS SYSTEM DESIGN LTPC 3 0 03 UNIT I INTRODUCTION TO MEMS 9 MEMS and Microsystems.System design basics – Gaussian optics. Mechanical vibration. gap and finger pull up. MEMS with micro actuators. 2. UNIT V INTRODUCTION TO OPTICAL AND RF MEMS 9 Optical MEMS. Typical products. MEMS scanners and retinal scanning display. Fracture and thin film mechanics. 3. performance issues. Electro static actuators. Thermo mechanics – actuators. 1.” Microsystems Design”. bistable actuators. Miniaturization. Electromagnetic actuators. torsional deflection. UNIT IV CIRCUIT AND SYSTEM ISSUES 9 Electronic Interfaces. Modelling of MEMS systems. Stress. Peizo electric pressure sensor. Resonance. MEMS materials. CAD for MEMS.Nadim Maluf. 3. Comb generators. New Delhi. RF Memes – design basics. Kluwer publishers. editor. Micro actuation.” The MEMS Handbook”. 1. 2000 2. Feed back systems. electro static instability.” An introduction to Micro electro mechanical system design”. case study – Capacitive RF MEMS switch.” MEMS & Micro systems Design and Manufacture” Tata McGraw Hill.

codesign of filtering and timing synchronization. 2007. Mohamed I.Receiver design. Zero IF receiver. viterbi algorithm. soft output decoding. Image rejection. UNIT IV OFDM SYSYTEM 9 Principle.principle. Algorithms. 3. Effect of frequency errors on OFDM systems. “Wireless Transceiver Systems Design”. Jurgen Freudenberger. Automatic gain control and DC offset compensation. quantization. Transceiever architectures for modern wireless systems. Space-Time codes. Elmasry. Effect of phase noise on OFDM systems. DC offsets. Superheterodyne receiver. Kluwer Academic Publishers. Receiver interferers and intermodulation distortion. OFDM baseband signal processing.Springer. springer. Direct up transmitter. Quadrature balance and relation to Image rejection.” Coding theory. TOTAL :45 PERIODS REFERENCES 1. Emad N. Wolfgang Eberle. Rui Paulo Martins. 2. Farag. Turbo codes. “Analog-baseband architectures and Circuits for multistandard and low voltageWireless transceivers”. John Wiley & Sons. Pui-In Mak. UNIT II CODING THEORY ALGORITHMS AND ARCHITECTURE 9 Convolution codes. 4. Low IF receiver. 2008. performance measure.-Hartley and Weaver. concatenated convolution codes. UNIT V ANALOG IMPAIRMENT AND ISSUES 9 Receiver sensitivity and noise figure. LO leakage. Peak to average power ratio . mathematical model. “Mixed signal VLSI Wireless design Circuits and systems”. UNIT III TRANSCIEVER ARCHITECTURE AND ISSUES 9 Receiver Architectures. Local oscillator pulling in PLL. Transmit chain setup. Sigma Delta Analog-to-digital converters. sampling. Types of Analog-to-digital converters.2007. LDPC coding. Volker Kuhn. Two-step-up transmitter. spatial multiplexing. propagation characteristics. trellis diagram. 2002. Superheterodyne transmitter. spatial channels. Seng-Pan U. Image rejection receiver. .VL9157 VLSI FOR WIRELESS COMMUNICATION LTPC 300 3 UNIT I ANALOG TO DIGITAL CONVERSION 9 Performance metrics for Analog-to-digital converters. Orthogonal space-time block codes. band-pass sampling. soft input decoding. Transmitter architecture. Case study. effect of phase noise in PLL. weight distribution. Architectures and Applications”. relation to EVM. codesign of Automatic gain control and timing synchronization. Andre Neubauer.

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