# B T L INSTITUTE OF TECHNOLOGY & MANAGEMENT

No.259/B, Hosur Road, Boomasandhra, Bangalore- 560 099

A LAB MANUAL ON

LOGIC DESIGN
Subject Code: 10ESL38
(As per VTU Syllabus)

PREPARED BY

Staff Members - Dept. of ECE

Logic Design Lab

10ESL38

IC Pin Configurations 1. 2. 3. Boolean Expression realization using Logic gates Half/Full Adder and Subtractor a. Parallel Adder/ Subtractor b. BCD to Excess-3 and Vice-versa 4. 5. 6. 7. 8. 9. Binary to Gray Conversion and vice versa MUX/DEMUX for arithmetic circuits Comparators Decoder Chip for LED Display Priority Encoder Flip-Flop verification

Page No.
2 4 7 10 14 16 21 27 31 33 35 38 50 55 57 59 60

10. Counters 11. Shift Registers 12. Ring Counter/ Johnson Counter 13. Sequence Generator Logic Design Lab Syllabus – 10ESL38 Possible Viva Questions

Dept. of ECE

1

BTLInstitute of Technology & Management M

Logic Design Lab

10ESL38

IC Pin configurations
Inverter (NOT Gate) - 7404LS 2-Input AND Gate - 7408LS

2-Input OR Gate - 7432LS

2-Input NAND Gate - 7400LS

2-Input NOR Gate - 7402LS

2-Input EX-OR Gate - 7486LS

3-Input NAND Gate - 7410LS

4-bit Binary Full Adder74LS83

Dept. of ECE

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7420LS Dual 4-input Multiplexer74153 4-Bit Magnitude Comparator .7495 Synchronous Up/Down Counter– 74192 Decimal scalar .7490 DualJK Flip-flop– 7476 Dept of ECE 3 BTLInstitute of Technology & Management M .Logic Design Lab 10ESL38 Dual 4-Input NAND Gate .7485 Decoders/Demultiplexer 74139 Shift Register .

Convert the AND-OR logic into NAND-NAND and NOR-NOR logic. apply inputs according to the truth table and verify the results. B. Verify that the results are correct. 10. and then using only NOR gates. 1 BOOLEAN EXPRESSION REALIZATION USING LOGIC GATES Aim: – To Simplify and Realize Boolean expressions using logic gates/Universal gates. 6. Dept of ECE 4 BTLInstitute of Technology & Management . Simplify the given Boolean expression manually using the Karnaugh Map. Apply the different combinations of input according to the truth tables. IC 7402 (NOR). Connect VCC and ground as shown in the pin diagram. Realize the simplified expression using logic gates. Connect the circuits according to the circuit diagrams. A: Implementation Using Logic Gates 5.IC 7400 (NAND).IC 7486 (EX-OR) Procedure – 1. check them against the truth tables. IC 7404 (NOT). Implementation Using Universal Gates 11. 12.Logic Design Lab 10ESL38 Experiment No. 4. 7. 2. Components Required: IC 7408 (AND). Check the output readings for the given circuits. 3. 8. Implement the simplified Boolean expressions using only NAND gates. Make connections as per the logic gate diagram. Draw a Karnaugh Map corresponding to the given truth table. IC 7432 (OR). 9. 13. Construct a truth table for the given problem. Verify that the gates are working.

C.D)=BC+BD POS form Y=f(A.B.B.C.D)=B(C+D) Dept of ECE 5 BTLInstitute of Technology & Management .Logic Design Lab 10ESL38 Given Problem: Truth Table: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Y 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 Switching Expression: ∑ π Karnaugh Map Simplification: K-Map for SOP CD AB 00 01 11 10 BD 00 01 1 1 1 11 1 1 10 1 1 AB 00 01 11 10 C+D CD 00 0 0 0 0 01 0 11 0 10 0 B 0 0 0 K-Map for POS BC Simplified Boolean Expression: SOP form Y=f(A.

Logic Design Lab

10ESL38

Dept of ECE

6

BTLInstitute of Technology & Management

Expression Realization using Basic Gates:
C B D
1 7408 2 4 7408 5 6 3 1 7432 2 3

Y=BC+BD

B C D

1 1 7432 2 7408 3 2

3

Y=B (C+D)

Realization using only NAND gates:

Realization using only NOR gates:

C B D

1 7400 2 4 7400 5

3 9 7400 10 6 8

B

2 7402 3

1

5 7402 6

4

Y =B +D) (C

Y =B BD C+
C D

8 7402 9 10

Realization using only NOR gates:
C B D
2 7402 3 5 7402 6 8 7402 9 10 4 2 7402' 3 1 1 11 7402 12 13 5 7402' 6 4 8 7402' 9

10

Y=B C+BD

Realization using only NAND gates:
B C D
1 7400 2 4 7400 5 6 3 9 7400 10 8 11 7400 12 13 1 7400' 2 3

Y = B +D) (C

Experiment No. 2

HALF/FULL ADDER AND HALF/FULL SUBTRACTOR
Aim: – To realize half/full adder and half/full subtractor using Logic gates Components Required: Procedure: 1. Verify that the gates are working. 2. Make the connections as per the circuit diagram for the half adder circuit, on the trainer kit. 3. Switch on the VCC power supply and apply the various combinations of the inputs according to the respective truth tables. 4. Note down the output readings for the half adder circuit for the corresponding combination of inputs. 5. Verify that the outputs are according to the expected results. 6. Repeat the procedure for the full adder circuit, the half subtractor and full subtractor circuits. 7. Verify that the sum/difference and carry/borrow bits are according to the expected values. IC 7408, IC 7432, IC 7486, IC 7404, etc.

A. Half Adder using Logic Gates: Half Adder Using Basic Gates A B 1 7486 2 1 7408 2 A 3 B 0 1 0 1 S 0 1 1 0 C 0 0 0 1 0 3 0 1 1 B. Full Adder Using Logic Gates Full Adder Using Basic Gates A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cn-1 0 1 0 1 0 1 0 1 S 0 1 1 0 1 0 0 1 C 0 0 0 1 0 1 1 1 .

Full Subtractor Using Logic Gates Full Subtractor Using Basic Gates A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cn-1 0 1 0 1 0 1 0 1 D 0 1 1 0 1 0 0 1 B 0 1 1 1 0 0 0 1 . Half Subtractor Using Logic Gates Half Subtractor Using Basic Gates A 0 0 1 C B 0 1 0 1 D 0 1 1 0 B 0 1 0 0 1 D.C.

Verify that the outputs match with the expected results. Apply the B input through XOR gates (essentially taking complement of B). In order to Perform Addition take S=0. 7483 Dept of ECE . Check the outputs and note them down in the table for the corresponding inputs. Take S=1. 2. 3. 4. Short S. IC 7483 Pin Diagram IC 7483. Apply the inputs to the adder/ subtractor circuits as shown in the truth tables. In order to implement the IC 7483 as a subtractor. 7. 5. IC 7486.Connect the pins from S1 to S4 to output terminals. 6. on the IC 7483.Experiment No. 10 10 BTLInstitute of Technology & Management M . 3 PARALLEL ADDER AND SUBTRACTOR USING 7483 Aim: –i.C0 to XOR gate 1 input and other input take from C4 and obtain the Output Carry Cout (Output Borrow Bout). To realize Parallel Adder and Subtractor Circuits using IC 7483 ii. Connect one set of inputs from A1 to A4 pins and the other set from B1 to B4. 8. etc. BCD to Excess-3 Code conversion and Vice Versa using IC7483 Components Required: Procedure: 1.

A. IC 7483 as a Parallel Adder Circuit Diagram: VCC A4 A3 1 3 8 10 16 5 14 C4 2 1 Output Carry 7486' 3 Cout Input Data A A2 A1 1 15 2 6 9 S4 S3 S2 S1 B4 7486 2 4 3 Data Output 7486 5 6 4 7483 Input Data B B3 9 7486 10 12 8 7 11 B2 7486 13 11 B1 1 13 12 GND S= 0 C0 Truth Table:- 4-BITParallel Adder Using 7483 where S=0 Input Data A A4 1 1 0 0 1 0 1 1 A3 0 0 0 0 0 1 1 0 A2 0 0 1 0 1 1 1 1 A1 0 0 0 1 0 0 0 0 B4 0 1 1 0 1 0 1 1 Input Data B B3 0 0 0 1 0 0 1 1 B2 1 0 0 1 1 1 1 0 B1 0 0 0 1 1 1 1 1 Cout 0 1 0 0 1 0 1 1 S4 1 0 1 1 0 1 1 0 Addition S3 0 0 0 0 1 0 1 1 S2 1 0 1 0 0 0 0 1 S1 0 0 0 0 1 1 1 1 Dept of ECE . 11 11 BTLInstitute of Technology & Management .

IC 7483 as a Parallel Subtractor Circuit Diagram: A4 A3 1 3 8 10 16 VCC 5 14 C4 2 1 Output Carry 7486' 3 Bout Input Data A A2 A1 1 15 2 6 9 S4 S3 S2 S1 B4 7486 7486 3 Data Output 2 4 6 4 7483 Input Data B B3 B2 B1 5 9 7486 10 12 8 7 11 13 C0 12 GND 7486 13 1 11 S= 1 4-BITParallel Subtractor Using 7483 Where S=1 Truth Table: .B.

Subtraction Input Data A A4 A3 A2 A1 B4 Input Data B B3 B2 B1 Bout S4 S3 S2 S1 Note: Bout = 1 for A<B. 1 0 0 0 1 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 Bout = 0 for A>B. 0 0 1 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 .

S4 S3 S2 S1 =1111 and C0 C4 = Cout. _A4 A_3 A_2 A_1= B4 B3 B2 B1= 1001 1100 → (1's complement) of +3 = 0011 + 1 ← C0=1(S&C0 shorted) 2‟ sComp leme n t of B input = -B The end around carry is disregarded 1 0110 +6 C0 C4 = Bout = 0 4 bit subtraction operation using 7483 for A<B here S=1 _A4 A_3 A_2 A_1= 1110 B4 B3 B2 B1= The end around carry is disregarded 0000 → (1's complement) of +15 = 1111 +1 ← C0=1(S&C0 shorted) 0 1111 → (2's complement) of +1 = 0001 2‟ sComp leme n t of B input = -B C0 C4 = Bout = 1 -1 . Consider the above Example A4 A_3 A2_A_1= 1_001 and B4 B3 B2 B1= 0011 1‟s C omp lemen t o f B4 B3 B2 B1 is B4 B3 B2 B1= 1100 A4 A3 A2 A1=1100 B4 B3 B2 B1=0011 . if S=1(i. 4 bit subtraction operation using 7483 for A>B here S=1 A4 A3 A2 A1= 1001 B4 B3 B2 B1= 1101 (2's complement) of +3=0011 1 0110 The end around carry is disregarded C0 C4 = Bout = 0 Difference. S4 S3 S2 S1 = 0110 2's complement method of subtraction can be performed.addition can be performed Ex: If ↓C0=0 then Sum.Example 4bit adder operation using 7483 if control input S=0.e. C0=1).

.

BCD To Excess-3 And Vice-Versa Conversion Using 7483 Chip I. Circuit Diagram: Input Data A A1 A0 1 15 2 6 9 B3 = 0 7486 2 3 Data Output Input Data B 4 B2 = 0 7486 5 9 6 4 7483 7486 B1 = 1 10 12 8 7 11 13 12 C0 GND 7486 13 1 11 B0 = 1 S= 0 Truth Table : BC Dto X C S3using 7483 Consider Constant Value for B3B2B1B0 = 0011 and S=0 BCD Inputs A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 E3 0 0 0 0 0 1 1 1 1 1 X X X X X Excess – 3 Outputs E2 0 1 1 1 1 0 0 0 0 1 X X X X X E1 1 0 0 1 1 0 0 1 1 0 X X X X X E0 1 0 1 0 1 0 1 0 1 0 X X X X X .B0 = 0011 vary the BCD input at A3. BCD TO EXCESS-3 CONVERTER VCC A3 A2 1 3 8 10 16 5 14 C4 E3 E2 E1 E0 X NC Note: S = 0 and B3.A1.A0.A2.C.B2.B1.

1 1 1 1 X X X X .

B0 = 0011 vary the Excess-3 input at A3(E3).II.B2.A2(E2). Circuit Diagram: A3 A2 VCC 1 3 8 10 16 5 14 C4 D C B A X NC Input Data A A1 A0 1 15 2 6 9 B3 = 0 7486 7486 3 Data Output Input Data B B2 = 0 2 4 6 4 7483 5 9 B1 = 1 7486 10 12 8 7 11 13 C0 12 GND B0 = 1 7486 13 11 S=1 Truth Table : X CS3to BCDusing 7483 Consider Constant Value for B3B2B1B0 = 0011 and S=1 Excess-3 Inputs E3 0 0 0 0 0 1 1 1 1 E2 0 1 1 1 1 0 0 0 0 E1 1 0 0 1 1 0 0 1 1 E0 1 0 1 0 1 0 1 0 1 A 0 0 0 0 0 0 0 0 1 BCD Outputs B 0 0 0 0 1 1 1 1 0 C 0 0 1 1 0 0 1 1 0 D 0 1 0 1 0 1 0 1 0 .A1(E1).A0(E0). EXCESS-3 to BCD CONVERTER Note: S=1 and B3.B1.

1 1 0 0 1 0 0 1 .

Gray to Binary Converter using logic gates. 3. 7. IC 7486. 6. Draw Karnaugh maps for each bit of output. 5. Apply the Binary inputs at B3-B0 pins. Check the outputs at the G3-G0 pins and note them down in the table for the corresponding inputs. Verify that the outputs match with the expected results. test and verify the working of a Grey to Binary Converter.Verify that the gates are working properly. ii. Components Required: Procedure: 1. 4 BINARY TO GRAY CONVERTER AND VICE VERSA Aim: – To realize:. 4. 8. i. etc. Write the proper truth table for the given Binary to Gray converter. Simplify the Karnaugh maps to get simplified Boolean Expressions. . Make connections on the trainer kit as shown in the circuit diagram for the Binary to Gray converter. Repeat the procedure to design. Binary to Gray Converter using logic gates.Experiment No. according to the truth table. 2.

Binary to Gray Converter.A. Truth Table: Binary Input B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Karnaugh Maps: For G3: For G2: B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Gray Code Output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 G3 = B 3 .

For G1: For G0: Circuit: .

Gray to Binary Converter Truth Table Gray Code Input G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary Output B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Karnaugh Maps: For B3: For B2: B3 = G3 .B.

For B1: For B0: Circuit: .

10. and thus the truth table is verified. A and B (S1 and S0) are ch an ged as per table and the output is taken at Za as sum and Zb as carry. Based on the selection lines one of the inputs wi ll be selected at the output.If MUX ‘A ’ has to b e initialized. 5 MUX/DEMUX FOR ARITHMETIC CIRCUITS Aim: – To study IC 74153 and 74139 and to implement arithmetic circuits with them. e) 9. The corresponding outputs are taken at Sn (pin Za) and Cn (pin Zb) and are verified according to the truth table. IC 7404. EB is m adelow. I1a. 6. the inputs are applied at Cn-1. 8. I3a)and (I0b. The corresponding outputs are taken at pin Za(Difference and pin Zb(Borrow) and are verifi d ) e IC 74153.In this case. connections are m ade accrding to the circuit. Making Ea and Eb zero andthe output is taken at Za. 7.In case of half adder using MUX. 5. IC 74139.The Pin [16] is connectedto + V cc and Pin [8] is co n nectedto ground. I2b and I3b) as shown.In full adder using MUX. I1b. An and Bn acco rding to the truth table. 3. apply constant inputs at (I0a. EA is m adelow and if MUX ‘B’ has to b e initialized. Veri fy outputs. I2a.Experiment No. table. . and outputs are taken at Za (Differe n c and Zb (Borrow).In caseof Half Subtractor. An and e Bn acco rding to the truth according to the truth table. IC 7420. Components Required: Procedure – A. o Inputs are applied at A and B as shown. IC 7400. the inputs A and B are varied. and Zb. The inputs are a pp lied either to ‘A ’ input or ‘B’ input.The corresponding values of select input lines. For MUX IC 74153 1. the inputs are appli d at Cn-1. In full subtractor using MUX. 4.etc. 2.

Half Adder Using 74153 Half Subtractor using 74153 Truth Table: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0 Full Adder Using 74153 Full Subtractor using 74153 .

In ca se of Half Subtractor. An and Bn acco rding to the truth table. 7. The corresponding outputs are taken at Differenc e and Borrow as shown. and are verified a ccording to the truth table. Based on the selection lines one of the inputs will be sel cted at the e set of outputs. 6. Inputs are applied at A and B as shown. the inputs are applied at Cn-1. 5. In full subtractor using DEMUX. The corresponding outputs are taken at Sum and Carry. If DEMUX ‘A ’ has to b e initialized. EA is m ade low and if DEMUX ‘B’ has to b e initialized. 2. The Pin [16] is co nnectedto + Vcc and Pin [8] is connectedto ground. An and Bn acco rding to the truth table. Verify outputs. A and B (S1a and S0a) are changed as per table andthe output is taken at Sum and Carry. 8. Verify outputs. In ca se of half adder using DEMUX . the inputs are applied at Cn-1. For DEMUX IC 74139 1.Ea is set to 0. In full adder using DEMUX. d . the corresponding values of select input lines. The inputs are appli d either to ‘A’ input or ‘B’ input. connections are m ade accor ing to the d circuit. e 3.Truth Tables for Full Adder/Subtractor using 74153 Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1 Procedure – B. and are verified accor ing to the truth table. and outputs are taken at Differencea n dBorrow. and thus the truth table is verified. EB is m adelow. 4.

Half Adder Using 74139 Half Subtractor Using 74139 Truth Tables: Inputs A 0 0 1 1 B 0 1 0 1 Half Adder Outputs Sum 0 1 1 0 Carry 0 0 0 1 Half Subtractor Outputs Diff 0 1 1 0 Borrow 0 1 0 0 .

Full Adder Using 74139 Full Subtractor Using 74139 .

Truth Tables: Inputs A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Cin/Bin 0 1 0 1 0 1 0 1 Full Adder Outputs S 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1 Full Subtractor Outputs D 0 1 1 0 1 0 0 1 Bout 0 1 1 1 0 0 0 1 .

3. 4.Apply the two inputs as shown. One-Bit Comparator: Circuit : Truth Table: 1bit Comparator Inputs A 0 0 1 1 B. 4. 2. 3. pin 4 (A>B). making sure that the MSB and LSB is correctly connected.Check the outputs and verify that they are according to the truth tables.Switch on Vcc. . IC 7408. Components Required: Procedure – A.Experiment No. IC 7486. Study of IC 7485: 1.Apply the inputs as per the truth tables.Write the truth table for an4-bit comparator.Make the connections as per the respective circuit diagrams. Two-Bit Comparator: B 0 1 0 1 A>B 0 0 1 0 Outputs A=B 1 0 0 1 A<B 0 1 0 0 IC 7404. 6 ONE/TWO BITCOMPARATOR AND IC 7485 Aim: – To verify the truth tables for one bit and two bit comparators after constructing them with basic logic gates. pin 3 (A=B) pins and are verified as being according to the truth table.Verify the working of the logic gates. A. IC 7485. Outputs are recorded at pin 2 (A<B). 5. 2. IC 7432. B. Connect pin 16 to Vcc and pin 8 to GND for the ICs. etc. and to study the working of IC 7485. Comparators Using Logic Gates: 1.

Truth Table : 2bit Comparator A1 A0 B1 B0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0 Karnaugh Maps: For A>B: For A<B For A=B .

4-Bit comparator using IC 7485 Pin Diagram: .Circuit: C.

Truth Table: 4bit Comparator Input A A3 0 0 1 0 0 1 0 1 A2 0 1 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 B3 0 0 1 0 1 1 0 1 Input B B2 0 0 0 1 0 0 1 1 B1 0 1 1 1 0 1 1 1 B0 1 1 0 0 0 1 0 0 A>B 0 1 0 0 0 1 0 1 Output A<B 1 0 0 1 1 0 0 0 A=B 0 0 1 0 0 0 1 0 .

7-segment LED Display. and observe the Decimal outputs displayed on the 7-segment LCD Display. 4. Connect Pin 16 to Vcc and Pin 8 to GND. 6. etc. IC 7447. Make the circuit connections as shown in the circuit diagram. IC 7447 Pin Diagram .Experiment No. 5. Give the different BCD inputs according to the truth table. Components required: Procedure: 1. Test and verify that all the segments of the LED Display are working. Verify that the outputs match the expected results in the truth tables. Connect the input pinsof the 7-segment LED Display to the respective pins (A3-A0) of the 7447 BCD to 7-Segment decoder driver chip. 7 DECODER CHIP FOR LED DISPLAY Aim: – Tostudy the use of a Decoder Chip (IC 7447) to drive a LED Display. 3. 2.

Circuit Diagram: Output Table: BCD inputs segment outputs display D C B A a b c d e f g 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 7-segment LED Display Schematic .

Connect the pins designated Inputs 1 through 9. etc. and note down the results for the respective inputs. D to the LED indicators of the trainer kit. Observe the outputs on the LED indicators. 6. to the input switches of the trainer kit.Experiment No. 7. IC 74147. Provide the inputs to the encoder chip as shown in the truth table. C. 4. Connect the Output pins designated A. IC 74147 Pin Diagram . Make the connections as shown in the circuit diagram. B. Connect Pin 16 of the IC to Vcc and Pin 8 to GND. 3. 5. Verify that the outputs are as shown in the truth table. 2. Components Required: Procedure: 1. 8 PRIORITY ENCODER Aim: – Tostudy the use of a 10-line-to-4-Line Priority Encoder Chip (IC 74147).

Truth Table: 1 1 0 X X X X X X X X 2 1 1 0 X X X X X X X 3 1 1 1 0 X X X X X X Decimal Input 4 5 6 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 X 0 1 X X 0 X X X X X X X X X 7 1 1 1 1 1 1 1 0 X X 8 1 1 1 1 1 1 1 1 0 X 9 1 1 1 1 1 1 1 1 1 0 BCD Output D C B A 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 1 0 Decimal Value 0 1 2 3 4 5 6 7 8 9 .

verify that they match that of the respective truth tables. 3. Truth Table : Preset 0 1 1 1 1 1 Clear 1 0 1 1 1 1 J X X 0 0 1 1 K X X 0 1 0 1 Clock X X 1 0 0 1 Status Set Reset No Change 0 1 1 0 Reset Set Toggle . etc. Check the outputs of the circuits. Components Required: Procedure: 1.Experiment No. for each of the flip-flop circuits. A. Make the connections as shown in the respective circuit diagrams. IC 7400. T-type and DType Flip-Flops. 2. Apply inputs as shown in the respective truth tables. 9 STUDY OF FLIP-FLOPS Aim: – To study and verify the truth tables for J-K Master Slave Flip Flop. J-K Master-Slave Flip-Flop Circuit: IC 7410.

B. T-Type Flip-Flop Circuit: Truth Table : Preset 1 1 Clear 1 1 T 0 1 Clock .

D-Type Flip-Flop Circuit: Truth Table: Preset 1 1 Clear 1 1 D 0 1 Clock 0 1 1 0 .C.

Clock inputs are applied one by one at the clock I/P. B. Starting value can be any number between 0 and 9. . B. IC 74192 and IC 74193 have the same pin configurations. 7. the data (1100) =12 (for 12 to 5 counter) is applied at A. 10 STUDY OF COUNTERS Aim: – Realization of 3-bit counters as a sequential circuit and Mod-N counter Design (7476. and the outputs are observed at QA. Now. 5. 7490. except for the connection from the output of the NAND gate to the load input. IC 74192. IC 7408. IC 7432. Make the connections as shown in the respective circuit diagrams. Next. Procedure: A. IC 7416. IC 74193. B. Study of Counters IC 74192. C and D respectively. Counter Circuits using IC 7476 1. the output of the NAND gate is connected to the Load input pin. 74192.a n dtru thta b leis ve rifie d es to for that condition. 74192 can be configured to count between 0 and 9 in either direction. Connections are made as shown in the respective circuit diagrams. 4. The data (0011) = 3 is made available at the data input pins designated A. QB and QA respectively. 3. C lo ck p u ls are a p p lied th e “Coun t Up” p in . is performed. 6. The Load pin is made LOW so that the data 0011 appears at QD. etc. Verify that the circuit outputs match those indicated by the truth tables. QB and QC pins of the 7476 ICs. C and D and the same procedure as explained above. 74193) Components Required: IC 7476. IC 74193 1. IC 7490. 2. QC. 3. 2. IC 7400.Experiment No.

A. 3-bit Asynchronous Up Counter Circuit Diagram: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 .

B. Of ECE. 3-bit Asynchronous Down Counter Circuit Diagram: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 Dept. QC 1 1 1 1 0 0 0 0 1 1 40 QB 1 1 0 0 1 1 0 0 1 1 QA 1 0 1 0 1 0 1 0 1 0 BTLInstitute of Technology & Management .

Of ECE.C. Mod-5 Asynchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 QC 0 0 0 0 1 0 QB 0 0 1 1 0 0 QA 0 1 0 1 0 0 Dept. 41 BTLInstitute of Technology & Management .

42 BTLInstitute of Technology & Management . Mod-3 Asynchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 QC 0 0 0 0 0 0 QB 0 0 1 0 0 1 QA 0 1 0 0 1 0 Dept.D. Of ECE.

3-bit Synchronous Counter Circuit: Timing Diagram: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 Dept.E. Of ECE. QC 0 0 0 0 1 1 1 1 0 0 43 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 BTLInstitute of Technology & Management .

QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 44 QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BTLInstitute of Technology & Management .F. 4-bit Ripple Counter Circuit: Truth Table: CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Dept. Of ECE.

Mod-10 Ripple Counter Circuit: Truth Table QD 0 0 0 0 0 0 0 0 1 1 0 CLK 0 1 2 3 4 5 6 7 8 9 10 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 Dept. Of ECE.G. 45 BTLInstitute of Technology & Management .

Of ECE. 46 BTLInstitute of Technology & Management .H. Decade Counter (using IC 7490) Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 10 QD 0 0 0 0 0 0 0 0 1 1 0 QC 0 0 0 0 1 1 1 1 0 0 0 QB 0 0 1 1 0 0 1 1 0 0 0 QA 0 1 0 1 0 1 0 1 0 1 0 Dept.

I. 47 BTLInstitute of Technology & Management . Mod-8 Counter (Using IC 7490) Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 0 0 0 0 0 0 0 QC 0 0 0 0 1 1 1 1 0 0 QB 0 0 1 1 0 0 1 1 0 0 QA 0 1 0 1 0 1 0 1 0 1 Dept. Of ECE.

Presettable counter using IC 74192/IC 74193 to count up from 3 to 8 Circuit: Truth Table: Clock 0 1 2 3 4 5 6 7 QD 0 0 0 0 0 1 0 0 QC 0 1 1 1 1 0 0 1 QB 1 0 0 1 1 0 1 0 QA 1 0 1 0 1 0 1 0 Decimal 3 4 5 6 7 8 3 4 Dept. Of ECE.J. 48 BTLInstitute of Technology & Management .

Of ECE.K. Presettable counter using IC 74192/74193 to count down from 5 to 12 Circuit: Implementation of 4-Input OR gate: Truth Table: Clock 0 1 2 3 4 5 6 7 8 9 QD 0 0 0 1 1 1 1 1 0 0 QC 1 1 1 0 0 0 0 1 1 1 QB 0 1 1 0 0 1 1 0 0 1 QA 1 0 1 0 1 0 1 0 1 0 Decimal 5 6 7 8 9 10 11 12 5 6 Dept. 49 BTLInstitute of Technology & Management .

Apply a clock pulse. At the end of the 4 clock pulse. Make sure the 7495 is operating in Parallel mode by ensuring Pin 6 (Mode M) is set to HIGH. and connect clock input to Pin 8 (Clk 2). SIPO. Serial In-Parallel Out (Left Shift): 1. 3. Dept. Enter more bits to see there is a left shifting of bits with each succeeding clock pulse. 5. Now. we notice that all 4 bits are available at the parallel output pins QA through QD. Shift right. Apply the first data at pin 5 (D) and apply one clock pulse. 2. QD (LSB). QC. 6. 3. 4. Make the connections as shown in the respective circuit diagram. 5. 7. 2. Apply a clock pulse. SISO. etc. Now. Apply the first data at pin 1 (SD1) and apply one clock pulse. 6. Enter more bits to see there is a right shifting of bits with each succeeding clock pulse. apply the second data at SD1. B.Experiment No. Of ECE. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode M) is set to LOW. We now observe that the earlier data is shifted from QA to QB. we notice that all 4 bits are available at the parallel output pins QA (MSB). Make the connections as shown in the respective circuit diagram. PIPO operations using the same. 50 BTLInstitute of Technology & Management th th IC 7495. Components Required: Procedure: A. apply the second data at D. We observe that this data appears at pin 13 (QA). until all bits are entered one by one. 11 STUDY OF SHIFT REGISTERS Aim: – To study IC 74S95. 7. and connect clock input to Pin 9 (Clk 1). and the realization of Shift left. Repeat the earlier step to enter data. We observe that this data appears at pin 10 (QD). and the new data appears at QA. At the end of the 4 clock pulse. and the new data appears at QD. PISO. Repeat the earlier step to enter data. until all bits are entered one by one. QB. 4. We now observe that the earlier data is shifted from QD to QC. . Serial In-Parallel Out (Right Shift): 1.

5. C. Keeping the mode control M on HIGH. D appears at the parallel output pins QA. B. 4. Apply one clock pulse at Clk 2 (Pin 8). QC. and apply clock pulses one by one. Of ECE. 2. Now set the Mode Control M to LOW. The 4 bits are applied at the Serial Input pin (Pin 1). D. Apply the 4 data bits as input to pins A. Applying yet ‟ a n o th ec lock p u lseg e tsth ethird data b it „ d 2 a t QD. th efirstd a tabit. QD. Serial In-Serial Out Mode: 1. Connections are made as shown in the PIPO mode circuit diagram. with serially applied inputs appearing as serial outputs. QB. 4. QDrespectively. 3. QDrespectively. A p p ly a n o he r c lock p ulse . apply one clock pulse. Connections are made as shown in the SISO circuit diagram. Parallel In-Serial Out Mode: 1. D (pins 2 through 5). Parallel In-Parallel Out Mode: 1. Now apply the 4-bit data at the parallel input pins A. Connections are made as shown in the PISO circuit diagram. 2. Make sure the 7495 is operating in SIPO mode by ensuring Pin 6 (Mode) is set to LOW. Note that the 4 bit data at parallel inputs A. C. 5. QC. C. B. one by one. r ‟ 6. Observe the data coming out in a serial mode at QD.C. Set Mode Control M to HIGH to enable Parallel transfer. „ d 0 a p p e rs a t th eoutpu t pin e ‟ a 5. Thus we see the IC 7495 operating in SISO mode. QB. to get the se c on d t data b it „d 1 at QD. th 4. B. 3. B. and connect clock input to Clk 1(Pin 9). C. and so on. D will appear at the parallel output pins QA. The data applied at the parallel input pins A. At the end of the 4 clock p u ls . 2. We observe now that the IC operates in PISO mode with parallel inputs being transferred to the output side serially. 3. E. with a clock pulse in between each pair of inputs to load the bits into the IC. Dept. 51 BTLInstitute of Technology & Management . D.

IC 7495 Pin Diagram: A. SIPO MODE (Right Shift) Circuit: Truth Table: Clock 1 2 3 4 Serial I/P 1 0 1 1 QA 1 0 1 1 QB X 1 0 1 QC X X 1 0 QD X X X 1 Dept. 52 BTLInstitute of Technology & Management . Of ECE. SIPO Mode (Left Shift) Circuit: Truth Table: Serial I/P 1 0 1 1 Clock 1 1 QA X X X 1 QB X X 1 0 QC X 1 0 1 QD 1 0 1 1 2 3 4 B.

SISO Mode Circuit: Truth Table: Serial I/P d0=0 d1=1 d2=1 d3=1 X X X Clock 1 2 3 4 5 6 7 QA QB QC 0 1 1 1 X X X X 0 1 1 1 X X X X 0 1 1 1 X QD X X X 0=d0 1=d1 1=d2 1=d3 D.C. Of ECE. PISO Mode Circuit: Truth Table: Mode Clk Parallel I/P A Parallel O/P B C D QA QB QC QD 0 1 1 1 X X X 0 1 X X 1 0 1 X 1 1 0 1 1 0 0 0 1 2 3 4 1 X X X X X X X X X X X X Dept. 53 BTLInstitute of Technology & Management .

54 BTLInstitute of Technology & Management . Of ECE.E. PIPO Mode Circuit: Truth Table: Clk Parallel I/P Parallel O/P A B C D QA QB QC QD 1 1 0 1 1 1 0 1 1 Dept.

record the observations and verify that they match the expected outputs from the truth table. 55 BTLInstitute of Technology & Management . 4. 2. Apply an initial input (1000) at the A. B. Ring Counter Circuit: Truth Table: Mode Clock QA QB QC QD 1 0 0 0 0 0 1 2 3 4 5 6 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 IC 7495. etc.Experiment No. C. Components Required: Procedure: 1. D pins respectively. IC 7404. Observe the output after each clock pulse. 5. 6. Next. 12 RING COUNTER /JOHNSON COUNTER Aim: – To design and study the operation of a ring counter and a Johnson Counter. Make the connections as shown in the respective circuit diagram for the Ring Counter. A. Keep Select Mode = HIGH (1) and apply one clock pulse. 3. Select Mode = LOW (0) to switch to serial mode and apply clock pulses. Of ECE. Dept. Repeat the same procedure as above for the Johnson Counter circuit and verify its operation.

Johnson Counter Circuit: Truth Table: Mode Clock QA QB QC QD 1 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 Dept.B. 56 BTLInstitute of Technology & Management . Of ECE.

13 SEQUENCE GENERATOR Aim: – To design and study the operation of a Sequence Generator. 4. 5. 57 BTLInstitute of Technology & Management . Components Required: Theory: In ord e rto gen e rate a s eq u e n co f len g th„S‟ . IC 7486. 3. 2. it is n ec e sary to u s eat least„N‟ n umb e rof e s Flip-flops. Dept. and checked against the expected values from the truth table. Clock pulses are applied at CLK 1 and the output values are noted. Of ECE. Mode M is set to LOW (0). we need to use 5 flip-flops. If the sequence is not realizable by 4 flip-flops. and clock pulses are fed through Clk 1 (pin 9). Procedure:1. Connections are made as shown in the circuit diagram. Truth table is constructed for the given sequence.Experiment No. and so on. and Karnaugh maps are drawn in order to obtain a simplified Boolean expression for the circuit. etc. in order to satisfy the condition . The functioning of the circuit as a sequence generator is verified. N = 4 Note: There is no guarantee that the given sequence can be generated by 4 flip-flops. Circuit: IC 7495. The given sequence length S = 15 Therefore.

Of ECE.Truth Table: Karnaugh Map: Map Value 15 7 3 1 8 4 2 9 12 6 11 5 10 13 14 O/p Clock QA QB QC QD D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 Dept. 58 BTLInstitute of Technology & Management .

SIPO. (i)Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versausing 7483 chip.scribd. 7. 13. realization of Boolean expressions using logic gates/Universal gates. 11. Shift right. PISO. Realization of Half/Full adder and Half/Full Subtractors using logic gates. Wiring and testing of Sequence generator. Realization of One/Two bit comparator and study of 7485 magnitude comparator.74193). Use of Decoder chip to drive LED display.Syllabus LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code :10ESL38 Hrs/ Week : 03 Total Hrs. 8. Truth table verification of Flip-Flops: (i) (ii) (iii) JK Master slave T type D type.: IA Marks : 25 Exam Hours : 03 Exam Marks : 50 NOTE: Use discrete components to test and verify the logic gates. MUX/DEMUX – use of 74153. LabView can be used for designing the gates along with the above. http://www.com/doc/62491691/Logic-Design-Lab-Manual-10ESL38-3rd-sem-2011 Dept. Shift left. Of ECE. 6. 7490. Realization of Binary to Gray code conversion and vice versa 5. SISO. Simplification. 59 BTLInstitute of Technology & Management . 9. 4. 10. 2. 1. Wiring and testing Ring counter/Johnson counter. Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476. 12. 3. 74139 for arithmetic circuits and code converter. Use of IC 74147 as Priority encoder. PIPO operations using 74S95. 74192.

Define multiplexer/ data selector 28. What is an excitation table/functional table 20. What are counters? Give their applications 36. Compare mux and encoder 32. Define flip flop 19. 45. in 74LS00? 48. What is minterm and maxterm? 26. What is race around condition? 22. List the applications of EX-OR and EX~NOR gates 11. Give the applications of combinational and sequential circuits 17. What is a Demultiplexer? 29. Explain AND and OR gate using diodes 8. SSI 10. Differentiate between flip flop and latch 21. What are basic gates? 3. Realize logic gates using NAND and NOR gates only 9. BTLInstitute of Technology & Management . What is modulus of a number? 39. 47. What is a ripple counter? 38. What is a static and a dynamic display. Compare synchronous and asynchronous counters 37. Explain the working of 7483 adder chip. 60 Dept. Compare demux and decoder 33. 2. Define LSI. What is a encoder and decoder 31. State De-morgans theorem 5. Mention the different logic families. Of ECE. Why NAND and NOR gates are called as universal gates. What is LCD and LED. What is an up counter and down counter? 43. Differentiate between half adder and half subtractor 14. How do you eliminate race around condition 23. Give examples for SOP and POS 6. Explain how it can be used as EX-3 to BCD conversion and vice versa 27. What is common cathode and common anode LED? 44. Give the block diagram of sequential circuits 18. Give the applications of mux and demux 30. What is a half adder? 13. What is a full adder? 15. 46. What does LS stand for. Define a logic gate. Explain how a shift register can be used as ring and johnson counter 41. Differentiate between combinational and sequential circuits. Explain how transistor can be used as NOT gate 7. What is a priority encoder? 34. Give examples 16. Give the block diagram of parallel adders 24. What is a shift register? 40.Possible Viva Questions 1. 4. List the types of LCD's and LED's. What is a truth table? 12. MSI . What is a code converter? 35. Give the applications of johnson and ring counters 42. What are BCD Give their applications or uses 25.

Of ECE. Which is the fastest logic? Dept.49. 61 BTLInstitute of Technology & Management .

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