# PROJECT REPORT ON

**CCII based Pipelined ADC
**

Submitted for partial fulfillment of award of

BACHELOR OF TECHNOLOGY

Degree In

**Electronics and Communication Engineering
**

By

VIDHI GOSWAMI (0061352807) NEHA (0111352807) GARIMA PRABHAKAR (0151352807) KRITIKA CHOUDHARY (0121352807)

Under the guidance of Mrs. Veepsa Bhatia

INDIRA GANDHI INSTITUTE OF TECHNOLOGY, DELHI, INDIA JANUARY-MAY, 2011

1

CERTIFICATE

Certified that Vidhi (0061352807), Neha (0111352807), Garima (0151352807), and Kritika (0121352807) have carried out the simulation and implementation work presented in this thesis entitled “CCII based pipelined ADC” for the award of Bachelor of Technology from Indira Gandhi Institute Of Technology, Delhi, India under my supervision and guidance. The thesis embodies result of original work and studies carried out by students themselves and the contents of the thesis do not form the basis for the award of any other degree to the candidate or to anybody else. To the best of my knowledge, the matter embodied in the thesis has not been submitted to any other university/institute for the award of any Degree or Diploma.

Mrs. Veepsa Bhatia (SUPERVISOR) Designation: Asst. Professor Department: Electronics & Communication Indira Gandhi Institute of Technology

Date:

2

ACKNOWLEDGEMENT

We would like to take this opportunity to thank everybody who has contributed in the successful completion of our project. First and foremost, we would like to express our deep sense of respect and gratitude towards our advisor and guide, Mrs. Veepsa Bhatia for her invaluable guidance and encouragement. This project would not have been possible without her personal attention. We want to thank her for giving us the opportunity to work under her. We consider it our good fortune to have got an opportunity to work with such a wonderful person. We would also like to thank the head of our electronics and communication department, Dr. Shail Bala Jain for motivating and guiding us.

VIDHI GOSWAMI (0061352807) NEHA (0111352807) GARIMA PRABHAKAR (0151352807) KRITIKA CHOUDHARY (0121352807)

3

INDEX

S.No.

1. 2. 3. 3.1 3.2 4. 5. 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8

Contents

Certificate Acknowledgement Chapter-1 Introduction and working Introduction Architecure of pipelined ADC Chapter-2 Orcad (p-spice) Chapter-3 Current conveyors CCII Introduction CC description CC generations CMOS implementation Advantages of CCs Applications of CCs Coding for CCII Simulation output Chapter-4 Sample and Hold circuit (S/H) General explanation Working CMOS implementation using CCII Coding for S/H Simulation output Chapter-5 Multiplying DAC (MDAC) Introduction Explanation CMOS implementation using CCII Comparison of settling time for the MDAC Coding for MDAC Simulation output

4

Page 2 No. 3

6 7 8 9 13 14 15 15 17 17 18 19 23 24 25 25 26 28 32 33 34 34 35 36 37 41

6.

7.

6.1 6.2 6.3 6.4 6.5

7.1 7.2 7.3 7.4 7.5 7.6

8. 8.1 8.2 8.3 8.4

Chapter-6 Comparator Introduction CMOS implementation Coding for comparator Simulation output Chapter-7 Clock generator and delay circuit 9.1 Introduction 9.2 Implementation 9.3 VHDL code Conclusion References

42 43 43 45 49 50 50 51 52 53 54

9.

10. 11.

Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14

List of Figures

1.5-bit/stage pipelined ADC architecture Current conveyor general block diagram The CMOS CCII circuit Simulation output for CCII Typical sample and hold circuit CCII based S/H Simulation output for S/H CCII based MDAC circuit Comparison of settling time for the MDAC Simulation output for MDAC CMOS based comparator circuit Simulation output for comparator Non-overlap clock generator Overall delay circuit

8 15 17 23 25 26 32 35 36 41 43 49 51 52

5

Chapter-1 Introduction and Working
6
.

Jiann-Jong Chen (Department of Electronic Engineering.
Simulation tool used:
ORCAD 9. the efficacy of the OA always determines the SC circuit performance. for this reason. The switched-capacitor (SC) circuits are usually used in pipelined ADCs not only they can construct the S/H circuit but also for the MDAC. But no paper discussed the CCII-based ADC. Chia-Chun Tsai. Compared with traditional OAs. It has been proven that the digital signal processing (DSP) shows better accuracy than analog signal processing. Trong-Yen Lee. National Taipei University of Technology . Two main building blocks of the pipelined ADC.Taipei.18 μm CMOS technology. This paper presents a new CCIIbased pipelined ADC instead of using traditional OA-based SC techniques which can employ the advantages of CCII. Wen-Ta Lee. The ADC is the main link between the analog input and DSP part. The digital error correction technique is also applied to increase the performance of our pipelined ADC. sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCIIs instead of operational amplifiers (OAs). The ADC based on pipelined architectures can offer both high resolution and high speed instead of large size and power consumption which make the architectures well suited for many applications. Simulation results show that the proposed CCII-based pipelined ADC can work at 10MHz with an 8bit resolution. we have implemented a new CCII based pipelined ADC which is proposed by Yuh-Shyan Hwang. The SC circuit is usually made by OAs.1/p-spice
7
. hence the CCII-based circuits are popularly used in many applications. we have used 0. Taiwan). CCIIs have higher accuracy and wider frequency ranges.
Technology used:
Here. Lu-Po Liao.Introduction
In this project.

thus the conversion of a sample traverses two stages in a clock cycle.5-bit/stage pipelined ADC architecture
The operation of the pipelined ADC consists of two phases.1: 1. It is composed of one S/H stage and eight sub-ADC stages. The even stages and odd stages operate in opposite.5-bit/stage pipelined architecture where the 0.5-bit output and a MDAC. the MDAC even stages generate and amplify the residue yielding the input signals for the even stages.
Fig. the S/H stage samples the input signal while the MDAC of even stages sample the output of odd stages and the sub-ADC dose the analog-to-digital conversion. Each pipelined stage performs a low resolution sub-ADC with 1.
8
. In the first phase.5-bit redundancy in each stage is used for digital correction to relax the requirement for the comparators. In the second phase. . The block diagram of the 8-bit pipelined ADC is shown in Fig.Architecture of Pipelined ADC
The ADC is realized with the 1.

Chapter-2 ORCAD (p-spice)
1 2 3
9
.

Berkeley (1975). Inc.
PSpice is a PC version of SPICE (which is currently available from OrCAD Corp. flip-flops.orcad.4
5 Introduction:
6
SPICE is a powerful general purpose analog and mixed-mode circuit simulator that is used to verify circuit designs and to predict the circuit behavior. NOR.). All analyses can be done at different temperatures. ). A student version (with limited capabilities) comes with various textbooks. The default temperature is 300K. A bode plot is generated.com/pspicead. PLDs and many more digital components. 4 • Noise analysis 5 • Parametric analysis 6 • Monte Carlo Analysis In addition. Here are the most important ones: 1 • Non-linear DC analysis: calculates the DC transfer curve. This makes it a useful tool for a wide range of analog and digital applications. FPGA. 2 • Non-linear transient and Fourier analysis: calculates the voltage and current as a function of time when a large signal is applied.
10
. This is of particular importance for integrated circuits. of Cadence Design Systems. PSpice has analog and digital libraries of standard components (such as NAND. as its name implies: Simulation Program for Integrated Circuits Emphasis. 3 • Linear AC Analysis: calculates the output as a function of frequency. MUXes. 10 transistors and 2 operational amplifiers. It was for this reason that SPICE was originally developed at the Electronics Research Laboratory of the University of California.aspx The PSpice Light version has the following limitations: circuits have a maximum of 64 nodes. SPICE can do several types of circuit analyses. Fourier analysis gives the frequency spectrum. Information about Pspice AD is available from the OrCAD website: http://www. The OrCAD student edition is called PSpice AD Lite.

PSpice was the first version of UC Berkeley SPICE available on a PC. having been released in January 1984 to run on the original IBM PC. It was developed by MicroSim and is used in electronic design automation.
11
. 7 PSpice is a SPICE analog circuit and digital logic simulation software that runs on personal computers. and the Microsoft Windows platform. Today it has evolved into an analog mixed signal simulator. Sun workstations. Subsequent versions improved in performance and moved to DEC/VAX minicomputers. MicroSim was bought by OrCAD which was subsequently purchased by Cadence Design Systems. The name is an acronym for Personal Simulation Program with Integrated Circuit Emphasis. hence the first letter "P" in its name. This initial version ran from two 360 KB floppy disks and later included a waveform viewer and analyser program called Probe.The circuit can contain the following components: 1 • Independent and dependent voltage and current sources 2 • Resistors 3 • Capacitors 4 • Inductors 5 • Mutual inductors 6 • Transmission lines 7 • Operational amplifiers 8 • Switches 9 • Diodes 10 • Bipolar transistors 11 • MOS transistors 12 • JFET 13 • MESFET 14 • Digital gates 15 • and other components. the Apple Macintosh.

magnetic part editor and Tabrizi core model for nonlinear cores. has several internal solvers.PSpice. auto-convergence and checkpoint restart. now developed towards more complex industry requirements. It also supports many additional features. support of parametrized models. a Model Editor. which were not available in the original Berkeley code like Advanced Analysis with automatic optimization of a circuit. is integrated in the complete systems design flow from OrCAD and Cadence Allegro. encryption.
12
.

Chapter-3 Second generation Current Conveyor (CCII)
13
.

in current mode circuits (CMCs). speech recognition. the currents decide the circuit operation and enable the design of the systems that can operate over wide dynamic range. CCs’ advanced circuit and device applications are presented in this tutorial article. These circuits can give large bandwidths and are suitable for low-voltage applications. Current feedback amplifiers (CFAs). pace makers.. VMCs are rarely used in low-voltage circuits as the minimum bias voltages depend on the threshold voltages of the MOSFETs. op amps. cellphones etc. All these structures can be implemented in CMOS. CCs’ unique architectures can easily transform into other current mode structures. Operational floating Conveyors (OFCs) Current Conveyors (CCs) etc. etc.Introduction
A current conveyor is a four (possibly five) terminal device which when arranged with other electronic elements in specific circuit configurations can perform many useful analog signal processing functions such as filter . All conventional analog circuits viz. current conveyor based current-mode circuits get lots of attention in analog signal processing applications. Current conveyors (CCs) are being increasingly employed to replace operational amplifiers in almost all analog signal-processing applications because their current mode architectures are particularly suitable for today’s low-voltage high frequency applications. The low end of the circuit operating range is limited by the leakage currents and noise floor level while the high end is decided by degradation of the trans-conductance per unit current available above the threshold voltage. In recent years. voltage to frequency converters. which suffer from low bandwidths arising due to the stray and circuit capacitances and are not suitable in high frequency applications. Analog VLSI can address almost all real world problems and finds exciting new information processing applications in variety of areas such as integrated sensors. oscillator and impedance function synthesis . The need for low-voltage low-power circuits is immense in portable electronic equipments like laptop computers. are voltage mode circuits (VMCs). However. are the popular CMC structures and most widely used structure among them is the CCII structure. hand writing recognition etc . image processing. voltage comparators etc.
14
.

VX = VY and the input resistance (RX ) at port X is zero .
15
. The commonly used block representation of a CC is shown in Figure 1.CC descripition
A CC is a three or more port (X. Z) network. Y . 0 or −1 and R X is the intrinsic resistance offered by the port X to the input currents. Here.e. C assume a value either 1. The operation of this device is such that if a voltage is applied to input terminal Y. we will explain only two generations.
First generation current conveyors:
It is a three port device. For an ideal CC. Current conveyor general block diagram
whose input-output relationship is given by
where A. i. B.
CC Generations
There are many generations of current conveyors. 1st and 2nd. an equal potential will appear on input X.
Fig 2.

a second version in which no current flows in terminal Y. was introduced.
16
. an input current being forced into X. This version has proven to be more useful than CC1. The voltage at X follows that applied to Y. As well . the current I will be conveyed to output terminal Z. The characteristic equation is given by:
The terminal Y exhibit an infinite input impedence. thus X exhibit a zero input impedence.Similarly. The characteristic equation is given by:
Second generation current conveyors:
To increase the versatility of the current conveyor. will result in an equal amount of current in terminal Y.

However. and the supply voltage is 3.CMOS implementation of CCII:
Fig.0 V and consume 0.3: The CMOS CCII circuit
The CMOS CCII circuit is designed as shown in Fig. Transistors M1~M7 are composed as a voltage buffer and the current through M8 and M9 is as same as that through M6 and M7.
Advantages of using CCII instead of Operational amplifiers
1. The proposed CCs are suitable for high frequency LV analog and
mixed signal systems. linearity and voltage tracking error between terminals X and Y which can achieve the requirement in the S/H and MDAC design. 3. in class A CCII has the bandwidth of about 200 MHz. Among all the other realizations. CCs are capable of operating at low voltage of ±1. 2. These CCs have bandwidths of 100 MHz with input current range of −500 to 500 μA when operated in class AB mode. M10 and Cc are used for frequency compensation and Vb is the bias voltage.6 mW power.
17
.3V. this realization of CCII exhibits good performance in terms of noise.

oscillator and impedance function synthesis . 2.4. In generation of mathematical functions such as square rooting and current squaring i.
18
. CCII or CCIII.e. etc. A current conveyor when arranged with other electronic elements in
specific circuit configurations can perform many useful analog signal processing functions such as filter . The structure can be modified to function as CCI. even for complicated mathematical computing.
Applications of circuits using CCs
1. This flexibility can be utilized in future current mode circuits.

11 +KT1L = 0 KT2 = 0.8 MJSW = 0.2 +WR =1 WINT = 4.5 +CGDO = 6.1860065 +CIT = 0 CDSC = 2.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 1.7E-10 CGSO = 6.MODEL NMOS NMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.747147E5 A0 =2 +AGS = 0.2320546 +PDIBLC2 = 1.885522E-4 A2 = 0.58*10-11 fal time = 1.640458E-6 +KETA = -6.593301E-11 VSAT = 1.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL =0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.6E-11 AT = 3.8388608 +PSCBE1 = 1.610453E-9 +DWB = -4.0948017 NFACTOR = 2.04*10-11 .3119338 +RDSW = 105 PRWG = 0.083251E-10 PBSW = 0.8 MJSWG = 0.344942E-9 VOFF = -0.631374E-3 +U0 = 296.2091688
19
.0295587 W0 = 1E-7 NLX = 1.61E-18 UC1 = -5.31E-9 +UB1 = -7.4826 PRWB = -0.8 MJ = 0.Coding for CCII:
*rise time = 6.597846E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 1.1E-9 +XJ = 1E-7 NCH = 2.1 DROUT = 0.1269477 +CJSWG = 3.7E-10 CGBO = 1E-12 +CJ = 9.245202E-3 K3 = 1E-3 +K3B = 0.32616E-18 +UC = 7.410779E-9 LINT = 2.01 RSH = 7.1269477 +CF =0 PVTH0 = -2.904263E10 PSCBE2 = 1.3549E17 VTH0 = 0.7062594 PDIBLC1 = 0.4021873 DVT2 = 7.3750766 +K1 = 0.3022984 DVT1 = 0.028975E-5 +DSUB = 0.5 KT1 = -0.045919E-8 +XL =0 XW = -1E-8 DWG = -2.506962E-8 B1 = 2.0217897 PCLM = 1.452647 B0 = 5.022 UA1 = 4.550345E-4 PB = 0.369258E-3 PRDSW = -1.3762949 +CJSW = 2.1 MOBMOD = 1 +PRT = 0 UTE = -1.991317E-3 ETAB = 6.546939E-8 PVAG = 0 +DELTA = 0.860244E-3 A1 = 7.670588E-3 PDIBLCB = -0.5842025 K2 = 1.3E-10 PBSWG = 0.179955E-9 UB = 2.8451012 UA = -1.

033999E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.168535E5 A0 = 1.316175
20
.5 PRWB = -0.0201833 A1 = 0.5 +CGDO = 7.818572E-4 +DSUB = 1.1 +U0 = 112.0235926 K3 = 0.7483291 PRWG = 0.282772E-4 ETAB = -3.022 UA1 = 4.1590089 +K3B = 4.4728931 PDIBLC1 = 2.824041E-9 VOFF = -0.47E-10 CGBO = 1E-12 +CJ = 1.046463E-10 PBSW = 0.+PK2 = 1.850167E10 PSCBE2 = 5E-10 PVAG = 0 +DELTA = 0.2687016 W0 = 1E-6 NLX = 1.845281E-3 WKETA = -2.180017E-3 PB = 0.195045E-21 +UC = -1E-10 VSAT = 1.4971827 +WR =1 WINT = 0 LINT = 2.56934E-11 PUB = 0 +PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.2490116 DVT2 = 0.949253E-8 +DWB = -2.3 +RDSW = 198.943206E-8 +XL =0 XW = -1E-8 DWG = -1.11 +KT1L = 0 KT2 = 0.288698E-6 +KETA = 0.4146818 +CJSW = 2.276128E-4 +PSCBE1 = 4.5 KT1 = -0.266704E-3 +PU0 = 1.22E-10 PBSWG = 0.7211984 +AGS = 0.61E-18 UC1 = -5.518344E-3 PCLM = 1.MODEL PMOS PMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.040084E-3 LKETA = -1.9624066 +CIT = 0 CDSC = 2.138043E-3 +PDIBLC2 = -9.5750728 K2 = 0.3806925 B0 = 4.9123142 MJSWG = 0.0932981 PUA = -2.1589E17 VTH0 = -0.1E-9 +XJ = 1E-7 NCH = 4.966066E-6 PDIBLCB = -1E-3 DROUT = 4.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 7.3936726 +K1 = 0.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL =0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.5106786 UA = 1.2 MOBMOD = 1 +PRT = 0 UTE = -1.31E-9 +UB1 = -7.0979832 NFACTOR = 1.47E-10 CGSO = 7.2328472 A2 = 0.8560642 MJ = 0.296252E-7 B1 = 1.6E-11 AT = 3.9123142 MJSW = 0.01 RSH = 8.5560978 DVT1 = 0.350276E-3 ) * .45072E-9 UB = 1.316175 +CJSWG = 4.

3u MN2 N6 N8 N1 N1 PMOS l= .01 *V4 N31 0 0V *.step lin param width 0.18u W= .3u MN7 N3 N6 0 0 NMOS l= .18u W= .316832E-3 * MN1 N7 N3 N1 N1 PMOS l= .01ns 20ns *.tran 0.51646E-11 PUB = 1E-21 +PVSAT = 50 PETA0 = 1E-4 PKETA = -3.456598E-4 PRDSW = 8.6u MN11 N11 N12 N8 N8 NMOS l= .6u MN4 N6 N7 0 0 NMOS l= .338191E-3 WKETA = 0.18u W= .3u MN9 N5 N6 0 0 NMOS l= .18u W= .3u 0.18u W= .0246885 LKETA = -2.dc V31 0 1.18u .18u W= .7V VX N12 0 PULSE (0 0.18u W= .8 0.001n 0.3u MN3 N7 N7 0 0 NMOS l= .02u *V31 N31 0 0V *.18u W= .6u MN10 N10 N2 N6 N6 NMOS l= .18u W= .6u MN8 N5 N9 N2 N2 PMOS l= .param width = 1u *.9V C2 N3 N5 1ff C1 N8 0 1ff .6u C3 N10 N3 1PF VY N11 0 0.4838247 +PK2 = 1.9 0.6u MN5 N1 N9 N2 N2 PMOS l= .5089586 PUA = -5.+CF =0 PVTH0 = 8.18u W= .001n 5n 10n) VDD N2 0 1.dc iref 20ua 100ua 2ua *iss N4 0 1mA
)
21
.016897E-3 +PU0 = -1.8V Vb N9 0 0.18u W= .3u MN6 N3 N9 N2 N2 PMOS l= .01n 0.

1nS 20ns *.1 *.DC V_IND 0 3.05n) *VINbar N32 0 PULSE (2.end
22
.01n 0.op *.*VIN N31 0 PULSE (3.025n .dc v2 0 2 0.001n 0.PRINT ac VDB(R2) VP(R2) .1 *.3 2.probe .9 3.001n 0.001n 0.05n) *.01n 0.ac dec 100 1khz 1000Ghz * .8 0.9 0.PRINT ID(MN1) *.3 0.plot tran V(vin) .TRAN .001n 0.025n .

4: Simulation output for CCII
23
.Simulation output for CCII:
Fig.

Chapter-4 Sample and Hold circuit (S/H)
24
.

Working:
Fig. They are typically used in analog-todigital converters to eliminate variations in input signal that can corrupt the conversion process. freezes) its value at a constant level for a specified minimal period of time. In hold mode the switch disconnects the capacitor from the buffer. a sample and hold circuit is an analog device that samples (captures. Sample and hold circuits and related peak detectors are the elementary analog memory devices. The capacitor is invariably discharged by its own leakage currents and useful load currents. and whose output remains constant at a value corresponding to the most recent measurement until the next measurement is made. or proportional to. The buffer amplifier charges or discharges the capacitor so that the voltage across the capacitor is practically equal. input voltage. but the loss of voltage (voltage drop) within a specified hold time remains within an acceptable error margin. which makes the circuit inherently volatile.5: Typical sample and hold circuit
A typical sample and hold circuit stores electric charge in a capacitor and contains at least one fast FET switch and at least one operational amplifier.
General explanation:
In electronics. grabs) the voltage of a continuously varying analog signal and holds (locks.To sample the input signal the switch connects the capacitor to the output of a buffer amplifier.
25
.Definition:
A circuit that measures an input signal at a series of definite times.

Each value is sampled and held. the input is often compared to a voltage generated internally from a digital-to-analog converter. A true sample and hold circuit is connected to the buffer for a short period of time. it is essential that the capacitor have very low leakage. and that it not be loaded to any significant degree which calls for a very high input impedance. In some kinds of analog-to-digital converters. the resulting conversion would be inaccurate and possibly completely unrelated to the true input value.
CCII based CMOS impementation of S/H circuit
26
. If the input value was permitted to change during this comparison process.Purpose
The reasons for using such a circuit are varied. using a common sample clock. In addition. Such successive approximation converters will often incorporate internal sample and hold circuitry. The circuit tries a series of values and stops converting once the voltages are "the same" within some defined error margin. a track and hold circuit is designed to track input continuously.
Implementation
In order that the input voltage is held constant for all practical purposes. sample and hold circuits are often used when multiple samples need to be measured at the same time.

When φ1=0.Fig. The output voltage can be expressed as
27
.5 is the S/H circuit.6: CCII based S/H in the sample mode and the φ1=1. the S/H is in the hold mode and the output Vout will be copied from the voltage sampled in C1. whenFig. the S/H is input signal is sampled on the capacitor C1.

885522E-4 A2 = 0.022 UA1 = 4.8 MJSWG = 0.7E-10 CGBO = 1E-12 +CJ = 9.0948017 NFACTOR = 2.670588E-3 PDIBLCB = -0.083251E-10 PBSW = 0.028975E-5 +DSUB = 0.61E-18 UC1 = -5.6E-11 AT = 3.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 1.32616E-18 +UC = 7.597846E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 1.1E-9 +XJ = 1E-7 NCH = 2.1 DROUT = 0.7062594 PDIBLC1 = 0.3549E17 VTH0 = 0.1 MOBMOD = 1 +PRT = 0 UTE = -1.344942E-9 VOFF = -0.546939E-8 PVAG = 0 +DELTA = 0.5842025 K2 = 1.245202E-3 K3 = 1E-3 +K3B = 0.58*10-11 fal time = 1.045919E-8 +XL =0 XW = -1E-8 DWG = -2.3119338 +RDSW = 105 PRWG = 0.610453E-9 +DWB = -4.904263E10 PSCBE2 = 1.452647 B0 = 5.0295587 W0 = 1E-7 NLX = 1.4826 PRWB = -0.8 MJ = 0.860244E-3 A1 = 7.7E-10 CGSO = 6.4021873 DVT2 = 7.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL =0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.04*10-11 .01 RSH = 7.2320546 +PDIBLC2 = 1.Coding for simulation of sample and hold circuit (S/H): Taking: VN11=Vin VN5=VOUT
*rise time = 6.2 +WR =1 WINT = 4.747147E5 A0 =2 +AGS = 0.593301E-11 VSAT = 1.MODEL NMOS NMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.410779E-9 LINT = 2.3762949 +CJSW = 2.8 MJSW = 0.1269477 +CJSWG = 3.1269477
28
.179955E-9 UB = 2.991317E-3 ETAB = 6.1860065 +CIT = 0 CDSC = 2.0217897 PCLM = 1.11 +KT1L = 0 KT2 = 0.550345E-4 PB = 0.640458E-6 +KETA = -6.3022984 DVT1 = 0.8451012 UA = -1.5 +CGDO = 6.3E-10 PBSWG = 0.31E-9 +UB1 = -7.506962E-8 B1 = 2.5 KT1 = -0.8388608 +PSCBE1 = 1.631374E-3 +U0 = 296.3750766 +K1 = 0.

5750728 K2 = 0.56934E-11 PUB = 0 +PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.966066E-6 PDIBLCB = -1E-3 DROUT = 4.4146818 +CJSW = 2.3936726 +K1 = 0.2328472 A2 = 0.0235926 K3 = 0.266704E-3 +PU0 = 1.1589E17 VTH0 = -0.040084E-3 LKETA = -1.6E-11 AT = 3.5 +CGDO = 7.022 UA1 = 4.288698E-6 +KETA = 0.316175
29
.180017E-3 PB = 0.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 7.3 +RDSW = 198.0201833 A1 = 0.824041E-9 VOFF = -0.1 +U0 = 112.350276E-3 ) * .518344E-3 PCLM = 1.296252E-7 B1 = 1.845281E-3 WKETA = -2.5106786 UA = 1.1590089 +K3B = 4.138043E-3 +PDIBLC2 = -9.369258E-3 PRDSW = -1.195045E-21 +UC = -1E-10 VSAT = 1.168535E5 A0 = 1.9123142 MJSW = 0.MODEL PMOS PMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.4728931 PDIBLC1 = 2.11 +KT1L = 0 KT2 = 0.+CF =0 PVTH0 = -2.7211984 +AGS = 0.0932981 PUA = -2.850167E10 PSCBE2 = 5E-10 PVAG = 0 +DELTA = 0.47E-10 CGSO = 7.4971827 +WR =1 WINT = 0 LINT = 2.943206E-8 +XL =0 XW = -1E-8 DWG = -1.2 MOBMOD = 1 +PRT = 0 UTE = -1.5 PRWB = -0.2091688 +PK2 = 1.046463E-10 PBSW = 0.818572E-4 +DSUB = 1.1E-9 +XJ = 1E-7 NCH = 4.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL =0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.47E-10 CGBO = 1E-12 +CJ = 1.5560978 DVT1 = 0.949253E-8 +DWB = -2.9624066 +CIT = 0 CDSC = 2.01 RSH = 8.282772E-4 ETAB = -3.61E-18 UC1 = -5.2490116 DVT2 = 0.5 KT1 = -0.033999E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.31E-9 +UB1 = -7.276128E-4 +PSCBE1 = 4.0979832 NFACTOR = 1.7483291 PRWG = 0.3806925 B0 = 4.45072E-9 UB = 1.8560642 MJ = 0.2687016 W0 = 1E-6 NLX = 1.

18u W= .8 0.18u W= .6u MN5 N1 N9 N2 N2 PMOS l= .18u W= .9V V3 N11 0 0.6u MN4 N6 N7 N4 N4 NMOS l= .step lin param width 0.param width = 1u *.6u MN11 N11 N12 N8 N8 NMOS l= .9123142 MJSWG = 0.6u MN8 N5 N9 N9 N2 PMOS l= .01ns 20ns *.18u W= .338191E-3 WKETA = 0.1n 20n) .18u W= .5089586 PUA = -5.3u MN2 N6 N8 N1 N1 PMOS l= .18u W= .dc V31 0 1.+CJSWG = 4.456598E-4 PRDSW = 8.016897E-3 +PU0 = -1.3u MN9 N5 N6 N4 N4 NMOS l= .3u MN6 N3 N9 N2 N2 PMOS l= .6u MN10 N10 N2 N6 N6 NMOS l= .316175 +CF =0 PVTH0 = 8.3u MN7 N3 N6 N4 N4 NMOS l= .18u W= .6u C1 N8 0 1ff C2 N3 N5 1ff C3 N10 N3 1ff V1 N2 0 1.18u .18u W= .dc iref 20ua 100ua 2ua *iss N4 0 1mA
30
.51646E-11 PUB = 1E-21 +PVSAT = 50 PETA0 = 1E-4 PKETA = -3.3u MN3 N7 N7 N4 N4 NMOS l= .18u W= .0246885 LKETA = -2.18u W= .18u W= .01 *V4 N31 0 0V *.02u *V31 N31 0 0V *.316832E-3 ) * MN1 N7 N3 N1 N1 PMOS l= .8 1n 1n 1n 0.3u 0.tran 0.8V V2 N9 0 0.7V V4 N12 0 PULSE ( 0 1.22E-10 PBSWG = 0.4838247 +PK2 = 1.

PRINT ID(MN1) *.001n 0.025n .3 2.probe .ac dec 100 1khz 1000Ghz * .01n 0.05n) *.001n 0.3 0.1 *.TRAN .001n 0.plot tran V(vin) .1nS 20ns *.025n .DC V_IND 0 3.05n) *VINbar N32 0 PULSE (2.dc v2 0 2 0.8 0.op *.9 0.end
31
.*VIN N31 0 PULSE (3.9 3.1 *.001n 0.PRINT ac VDB(R2) VP(R2) .01n 0.

7: Simulation output for S/H
Here: VN11=Vin VN5=VOUT
32
.Simulation output for S/H circuit:
Fig.

Chapter-5 Multiplying Digital to analog converter (MDAC)
Introduction:
33
.

This is equivalently a zero-order hold operation and has an effect on the frequency response of the reconstructed signal. The conventional DAC’s have an internal Vref . usually an electrical voltage.
Explanation:
The DAC fundamentally converts finite-precision numbers (usually fixedpoint binary numbers) into a physical quantity. that is output voltage of DAC equals product of input voltage reference and digital code Vout = Vin * N. The effect of this is that the output voltage is held in time at the current value until the next input number is latched resulting in a piecewise constant output. Multiplying DAC have wide range of voltage reference. Standard DAC have constant voltage reference or narrow range of voltage reference. These numbers are written to the DAC. whereas a multiplying DAC has an external Vref. Usually these numbers are updated at uniform sampling intervals and can be thought of as numbers obtained from a sampling process. Multiplying DAC allows o/p voltage to be varied i\p with input reference voltage.The output voltage Vo of a DAC is proportional to reference voltage Vref. at which time the DAC output voltage changes rapidly from the previous value to the value represented by the currently latched number. sometimes along with a clock signal that causes each number to be latched in sequence. Vref can be a time varying signal. Normally the output voltage is a linear function of the input number.
CCII based CMOS implementation of MDAC:
34
. So multiplying DAC may multiply input voltage reference and digital code.

the Vout can be expressed as below by simplifying αv =1
The output Vout is determined by two terminals X and Z with the same current which makes the output voltage settling faster. The settling time ts of the MDAC circuit can be derived as
35
.Fig.5-bit/stage architecture for the pipelined ADC. The output voltage Vout is
To correspond 1.8: CCII based MDAC circuit
The MDAC circuit shown in Fig. and the two capacitors are series together in the next phase φ2 and the bottom plate of capacitor C2 connects to VR (VR = ±V ref or 0). the input is sampled on both capacitors C1 and C2. When φ1=1. The feedback capacitor C3 between terminals X and Z plays the major role to determine the output voltage simultaneously. 4(b) operates similar to the S/H circuit.

The circuit with the Z-terminal capacitor feedback can decrease the settling time. Fig. 5 shows the simulation result of settling time for the MDAC circuit.9: Comparison of settling time for the MDAC circuit
36
. the circuit is up to 38% in settling time faster than that of without the Z-terminal capacitor feedback.
Comparison of settling time for the MDAC circuit
Fig. With the Z-terminal capacitor feedback.Where ξ is the factor that effects the settling time and CL is the loading capacitance.

6E-11 AT = 3.7E-10 CGSO = 6.179955E-9 UB = 2.61E-18 UC1 = -5.01 RSH = 7.8451012 UA = -1.1 DROUT = 0.631374E-3 +U0 = 296.4826 PRWB = -0.32616E-18 +UC = 7.0217897 PCLM = 1.593301E-11 VSAT = 1.5 KT1 = -0.1E-9 +XJ = 1E-7 NCH = 2.904263E10 PSCBE2 = 1.58*10-11 fal time = 1.022 UA1 = 4.597846E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 1.0948017 NFACTOR = 2.31E-9 +UB1 = -7.506962E-8 B1 = 2.991317E-3 ETAB = 6.3762949
37
.5842025 K2 = 1.747147E5 A0 =2 +AGS = 0.028975E-5 +DSUB = 0.3750766 +K1 = 0.11 +KT1L = 0 KT2 = 0.Coding for MDAC:
Taking: VN3=Vout VN13=Vin
*rise time = 6.7E-10 CGBO = 1E-12 +CJ = 9.04*10-11 .1860065 +CIT = 0 CDSC = 2.5 +CGDO = 6.MODEL NMOS NMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.3119338 +RDSW = 105 PRWG = 0.045919E-8 +XL =0 XW = -1E-8 DWG = -2.7062594 PDIBLC1 = 0.410779E-9 LINT = 2.3549E17 VTH0 = 0.452647 B0 = 5.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL =0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.2 +WR =1 WINT = 4.245202E-3 K3 = 1E-3 +K3B = 0.3022984 DVT1 = 0.344942E-9 VOFF = -0.1 MOBMOD = 1 +PRT = 0 UTE = -1.610453E-9 +DWB = -4.670588E-3 PDIBLCB = -0.550345E-4 PB = 0.860244E-3 A1 = 7.8 MJ = 0.4021873 DVT2 = 7.8388608 +PSCBE1 = 1.640458E-6 +KETA = -6.2320546 +PDIBLC2 = 1.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 1.885522E-4 A2 = 0.0295587 W0 = 1E-7 NLX = 1.546939E-8 PVAG = 0 +DELTA = 0.

818572E-4 +DSUB = 1.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 7.7483291 PRWG = 0.1589E17 VTH0 = -0.296252E-7 B1 = 1.8 MJSW = 0.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL =0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.1269477 +CF =0 PVTH0 = -2.0979832 NFACTOR = 1.1 +U0 = 112.4971827 +WR =1 WINT = 0 LINT = 2.2687016 W0 = 1E-6 NLX = 1.7211984 +AGS = 0.8 MJSWG = 0.31E-9 +UB1 = -7.845281E-3 WKETA = -2.01 RSH = 8.11 +KT1L = 0 KT2 = 0.MODEL PMOS PMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.0235926 K3 = 0.168535E5 A0 = 1.3806925 B0 = 4.288698E-6 +KETA = 0.9624066 +CIT = 0 CDSC = 2.850167E10 PSCBE2 = 5E-10 PVAG = 0 +DELTA = 0.2 MOBMOD = 1 +PRT = 0 UTE = -1.47E-10 CGBO = 1E-12
38
.040084E-3 LKETA = -1.0932981 PUA = -2.5106786 UA = 1.266704E-3 +PU0 = 1.282772E-4 ETAB = -3.5 KT1 = -0.45072E-9 UB = 1.1E-9 +XJ = 1E-7 NCH = 4.5750728 K2 = 0.3936726 +K1 = 0.5 PRWB = -0.350276E-3 ) * .5560978 DVT1 = 0.56934E-11 PUB = 0 +PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.966066E-6 PDIBLCB = -1E-3 DROUT = 4.943206E-8 +XL =0 XW = -1E-8 DWG = -1.3 +RDSW = 198.2328472 A2 = 0.61E-18 UC1 = -5.369258E-3 PRDSW = -1.47E-10 CGSO = 7.824041E-9 VOFF = -0.1269477 +CJSWG = 3.195045E-21 +UC = -1E-10 VSAT = 1.+CJSW = 2.6E-11 AT = 3.138043E-3 +PDIBLC2 = -9.1590089 +K3B = 4.3E-10 PBSWG = 0.022 UA1 = 4.5 +CGDO = 7.2091688 +PK2 = 1.2490116 DVT2 = 0.518344E-3 PCLM = 1.033999E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.276128E-4 +PSCBE1 = 4.4728931 PDIBLC1 = 2.0201833 A1 = 0.083251E-10 PBSW = 0.949253E-8 +DWB = -2.

8V V2 N9 0 0.8 1n 1n 1n 0.6u MN16 N14 N19 N16 N16 NMOS l= .180017E-3 PB = 0.4146818 +CJSW = 2.18u W= .456598E-4 PRDSW = 8.18u W= .9123142 MJSW = 0.18u W= .8 0 1n 1n 1n 0.316175 +CF =0 PVTH0 = 8.016897E-3 +PU0 = -1.316175 +CJSWG = 4.3u MN6 N3 N9 N2 N2 PMOS l= .5089586 PUA = -5.18u W= .338191E-3 WKETA = 0.6u MN13 N8 N19 N14 N14 NMOS l= .18u W= .6u MN15 N13 N19 N15 N15 NMOS l= .18u W= .0246885 LKETA = -2.18u W= .18u W= .4838247 +PK2 = 1.3u MN2 N6 N8 N1 N1 PMOS l= .51646E-11 PUB = 1E-21 +PVSAT = 50 PETA0 = 1E-4 PKETA = -3.6u MN5 N1 N9 N2 N2 PMOS l= .6u MN18 N18 N11 N17 N17 NMOS l= .3u MN9 N5 N6 N4 N4 NMOS l= .9V V3 N13 0 0.9V V4 N18 0 0V V5 N19 0 PULSE ( 0 1.6u MN8 N5 N9 N9 N2 PMOS l= .6u MN10 N10 N2 N6 N6 NMOS l= .1n 20n)
39
.8560642 MJ = 0.18u W= .3u MN7 N3 N6 N4 N4 NMOS l= .18u W= .316832E-3 ) * MN1 N7 N3 N1 N1 PMOS l= .18u W= .046463E-10 PBSW = 0.6u MN4 N6 N7 N4 N4 NMOS l= .18u W= .18u W= .6u MN12 N12 N19 N13 N13 NMOS l= .6u C1 N12 N14 1ff C2 N15 N16 1ff C3 N3 N5 1ff C4 N10 N3 1ff V1 N2 0 1.18u W= .6u MN11 N8 N11 N12 N12 NMOS l= .+CJ = 1.18u W= .18u W= .18u W= .9123142 MJSWG = 0.6u MN17 N17 N19 0 0 NMOS l= .3u MN3 N7 N7 N4 N4 NMOS l= .1n 20n) V6 N11 0 PULSE ( 1.6u MN14 N15 N11 N14 N14 NMOS l= .22E-10 PBSWG = 0.18u W= .

3 0.18u .DC V_IND 0 3.05n) *.1nS 20ns *.01n 0.TRAN .PRINT ID(MN1) *.001n 0.001n 0.3u 0.ac dec 100 1khz 1000Ghz * .01ns 20ns *.dc iref 20ua 100ua 2ua *iss N4 0 1mA *VIN N31 0 PULSE (3.01 *V4 N31 0 0V *.001n 0.025n .end
40
.probe .plot tran V(vin) .op *.tran 0.025n .05n) *VINbar N32 0 PULSE (2.02u *V31 N31 0 0V *.8 0.1 *.001n 0.01n 0.3 2.step lin param width 0.8 0.param width = 1u *.dc v2 0 2 0.1 *.PRINT ac VDB(R2) VP(R2) ..9 0.9 3.dc V31 0 1.

10: simulation output for MDAC
Here. VN3=Vout VN13=Vin
41
.Simulation output for MDAC:
Fig.

Chapter-6 Comparator
42
.

a feedback latch circuit (M1~M4).11: CMOS based comparator circuit
A low power transconductance latched comparator is employed in the pipelined ADC design and the circuit is shown in Fig. another important circuit in the pipelined ADC is the comparator which can be composed with resistors for use as the flash ADC (i. a comparator is a device that compares two voltages or currents and switches its output to indicate which is larger. reset transistors (M13. They are commonly used in devices such as Analog-to-digital converters (ADCs). Since there are error correction circuits in the proposed pipelined ADC. input transistors (M9. the required accuracy of the comparator can be tolerated. and the cutting
43
. ± 1/4Vref still can be achieved. This comparator is constructed of a power switch (M15). M14). it can employ the lower accuracy comparators rather than the pre-amplifier ones. M11). Therefore. sub-ADC) in every stage.Introduction:
In electronics.
CCII based CMOS implementation of comparator:
Fig. Comparing to the CCII.e.

the comparator is in a reset period. M7~M8).
44
. the cutting transistors (M10. The feedback latch circuit (M1~M4) amplifies the voltage gap at terminal Vout+ and Vout.achieves to the voltage level of VDD.transistors (M10. the power consumption is very low. When the voltage at terminal Vout+ or Vout. M12) with feedback inverters (M5~M6.to the full range which due to the difference in the input transconductance. the comparator is in the operation period.at the GND level. Because the feedback inverter cut off the DC current path. At this period. When the CLK is low. the power switch is turn on and reset transistors are turned off. At this period. M12) are turned off by the feedback inverter. When the CLK is high. the power switch M15 is turned off and the reset transistors are turn on which make the terminals Vout+ and Vout.

022 UA1 = 4.5 KT1 = -0.1860065 +CIT = 0 CDSC = 2.11 +KT1L = 0 KT2 = 0.028975E-5 +DSUB = 0.506962E-8 B1 = 2.7062594 PDIBLC1 = 0.179955E-9 UB = 2.631374E-3 +U0 = 296.32616E-18 +UC = 7.640458E-6 +KETA = -6.593301E-11 VSAT = 1.MODEL NMOS NMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.58*10-11 fal time = 1.1 DROUT = 0.344942E-9 VOFF = -0.8388608 +PSCBE1 = 1.6E-11 AT = 3.2320546 +PDIBLC2 = 1.Coding for comparator
Taking: VN4=Vout+ VN5=VoutVN3=Vref
*rise time = 6.610453E-9 +DWB = -4.8451012 UA = -1.3022984 DVT1 = 0.546939E-8 PVAG = 0 +DELTA = 0.5842025 K2 = 1.01 RSH = 7.245202E-3 K3 = 1E-3 +K3B = 0.4021873 DVT2 = 7.885522E-4 A2 = 0.1E-9 +XJ = 1E-7 NCH = 2.3119338 +RDSW = 105 PRWG = 0.597846E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 1.04*10-11 .904263E10 PSCBE2 = 1.747147E5 A0 = 2 +AGS = 0.0295587 W0 = 1E-7 NLX = 1.2 +WR = 1 WINT = 4.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 1.3750766 +K1 = 0.452647 B0 = 5.4826 PRWB = -0.991317E-3 ETAB = 6.3549E17 VTH0 = 0.3E4 +WL =0 WLN = 1 WW =0 +WWN = 1 WWL = 0 LL = 0 +LLN = 1 LW =0 LWN = 1
45
.61E-18 UC1 = -5.045919E-8 +XL = 0 XW = -1E-8 DWG = -2.1 MOBMOD = 1 +PRT = 0 UTE = -1.31E-9 +UB1 = -7.0948017 NFACTOR = 2.860244E-3 A1 = 7.0217897 PCLM = 1.410779E-9 LINT = 2.670588E-3 PDIBLCB = -0.

+LWL = 0 CAPMOD = 2 XPART = 0.56934E-11 PUB = 0 +PVSAT = 2E3 PETA0 = 1E-4 PKETA = -3.5 KT1 = -0.083251E-10 PBSW = 0.6E-11 AT = 3.2490116 DVT2 = 0.2328472 A2 = 0.282772E-4 ETAB = -3.8 MJ = 0.824041E-9 VOFF = -0.31E-9 +UB1 = -7.7211984 +AGS = 0.3936726 +K1 = 0.550345E-4 PB = 0.845281E-3 WKETA = -2.168535E5 A0 = 1.369258E-3 PRDSW = -1.7E-10 CGSO = 6.1E-9 +XJ = 1E-7 NCH = 4.4E-4 CDSCD = 0 +CDSCB = 0 ETA0 = 7.288698E-6 +KETA = 0.2091688 +PK2 = 1.966066E-6 PDIBLCB = -1E-3 DROUT = 4.1589E17 VTH0 = -0.040084E-3 LKETA = -1.8 MJSW = 0.2 MOBMOD = 1 +PRT = 0 UTE = -1.01 RSH = 8.MODEL PMOS PMOS ( LEVEL = 7 + TNOM = 27 TOX = 4.1 +U0 = 112.61E-18 UC1 = -5.3E-10 PBSWG = 0.850167E10 PSCBE2 = 5E-10 PVAG = 0 +DELTA = 0.022 UA1 = 4.3806925 B0 = 4.5750728 K2 = 0.266704E-3 +PU0 = 1.1590089 +K3B = 4.0932981 PUA = -2.0979832 NFACTOR = 1.5560978 DVT1 = 0.3762949 +CJSW = 2.9624066 +CIT = 0 CDSC = 2.195045E-21 +UC = -1E-10 VSAT = 1.818572E-4 +DSUB = 1.0201833 A1 = 0.518344E-3 PCLM = 1.7483291 PRWG = 0.45072E-9 UB = 1.276128E-4 +PSCBE1 = 4.5106786 UA = 1.2687016 W0 = 1E-6 NLX = 1.7E-10 CGBO = 1E-12 +CJ = 9.5 +CGDO = 6.5 PRWB = -0.033999E-7 +DVT0W = 0 DVT1W = 0 DVT2W = 0 +DVT0 = 0.3 +RDSW = 198.1269477 +CJSWG = 3.4971827 +WR = 1 WINT = 0 LINT = 2.350276E-3 ) * .8 MJSWG = 0.0235926 K3 = 0.138043E-3 +PDIBLC2 = -9.943206E-8 +XL = 0 XW = -1E-8 DWG = -1.4728931 PDIBLC1 = 2.949253E-8 +DWB = -2.296252E-7 B1 = 1.11 +KT1L = 0 KT2 = 0.1269477 +CF = 0 PVTH0 = -2.3E4 +WL =0 WLN = 1 WW =0
46
.

456598E-4 PRDSW = 8.3u MN3 N10 N9 0 0 NMOS l= .18u W= .316175 +CJSWG = 4.8560642 MJ = 0.316175 +CF = 0 PVTH0 = 8.18u W= .+WWN = 1 WWL = 0 LL = 0 +LLN = 1 LW =0 LWN = 1 +LWL = 0 CAPMOD = 2 XPART = 0.6u MN13 N5 N6 N0 N0 NMOS l= .6u MN12 N11 N3 N0 N0 NMOS l= .18u W= .47E-10 CGBO = 1E-12 +CJ = 1.51646E-11 PUB = 1E-21 +PVSAT = 50 PETA0 = 1E-4 PKETA = -3.18u W= .6u VREF N3 0 0.7V VX N6 0 PULSE ( 0 1.18u W= .7V VOUT N5 0 0.6u MN11 N4 N3 N11 N11 NMOS l= .316832E3 ) * MN1 N10 N9 N8 N8 NMOS l= .3u MN9 N5 N1 N10 N10 NMOS l= .8V VIN N1 0 0.18u W= .9V
47
.1n 20n) VDD N2 0 1.5089586 PUA = -5.18u W= .18u W= .3u MN6 N1 N5 0 0 NMOS l= .6u MN14 N4 N6 N0 N0 NMOS l= .18u W= .5 +CGDO = 7.6u MN4 N9 N10 0 0 NMOS l= .18u W= .6u MN5 N1 N5 N2 N2 NMOS l= .3u MN2 N9 N10 N8 N8 NMOS l= .22E-10 PBSWG = 0.6u MN8 N3 N4 0 0 NMOS l= .0246885 LKETA = -2.47E-10 CGSO = 7.016897E-3 +PU0 = -1.3u MN7 N3 N4 N2 N2 PMOS l= .338191E-3 WKETA = 0.8 1n 1n 1n 0.6u MN10 N10 N1 0 0 NMOS l= .18u W= .6u MN15 N8 N6 N2 N2 NMOS l= .9123142 MJSWG = 0.9123142 MJSW = 0.4146818 +CJSW = 2.18u W= .180017E-3 PB = 0.18u W= .18u W= .046463E-10 PBSW = 0.4838247 +PK2 = 1.18u W= .7V VOUT+ N4 0 0.

9 0.3u 0.8 0..dc iref 20ua 100ua 2ua *iss N4 0 1mA *VIN N31 0 PULSE (3.05n) *.probe .01ns 20ns *.05n) *VINbar N32 0 PULSE (2.001n 0.plot tran V(vin) .025n .step lin param width 0.TRAN .end
48
.3 0.18u .001n 0.9 3.02u *V31 N31 0 0V *.01n 0.PRINT ac VDB(R2) VP(R2) .dc v2 0 2 0.tran 0.1nS 20ns *.001n 0.8 0.025n .dc V31 0 1.DC V_IND 0 3.param width = 1u *.ac dec 100 1khz 1000Ghz * .1 *.01 *V4 N31 0 0V *.01n 0.1 *.3 2.op *.PRINT ID(MN1) *.001n 0.

12: simulation output for comparator
Here: VN4=Vout+ VN5=VoutVN3=Vref
49
.Simulation output for comparator
Fig.

Chapter-7 Clock generator and delay circuit
50
.

8. Dealy circuit: An electronic simulation device for reproduction of a signal with a delay equal to a predetermined time interval τ.13: Non-overlap clock generator
51
.
Implementation:
• •
• • •
There are many switches in the entire design. Under the 10 MHz operation frequency. The circuit of the control signal generator is shown in Fig.
Fig. It generates two control signals. The signal can range from a simple symmetrical square wave to more complex arrangements. the time interval between these two clocks is 1ns. The overall delay circuit used in proposed pipelined ADC is shown in Fig. CLK1 and CLK2.Clock generator and delay circuit: Introduction:
A clock generator is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in synchronizing a circuit's operation. we employ D-type flip-flops to complete the delay function. Here. The digital error correction circuit is also realized in our design.

all.14: Overall delay circuit
VHDL coding for the delay circuit:
Library ieee.The overall delay circuit is:
Fig. entity d_not is port (a. Use ieee. end d_not. end d_not11. b:out std_logic).
52
. architecture d_not11 of d_not is begin process(clk) begin if(clk=’1’) b<=not a. end process.clk:in std_logic.std_logic_1164. end if.

S/H and MDAC circuits are constructed of CCIIs instead of OAs.5 bit/stage architecture with error correction circuits in the pipelined ADC. Two main building blocks of the pipelined ADC.18μm CMOS technology and consumes 29mW under a 3. Because of the 1.Conclusion:
A new CCII-based pipelined ADC is implemented in this project.
53
. The Z-terminal capacitor feedback in CCIIs can shorten the settling time. The CCII-based pipelined ADC is realized in a 0. the required accuracy of the comparator can be tolerated.3V power supply.

† AND S.S.C. Inc.com/pspicead. Krishnan Marg. A New CCII-Based Pipelined Analog to Digital Converter Yuh-Shyan Hwang. OrCAD website for CAPTURE. JAMUAR2
1Thin Film Technology Group. Sedra and Gordon W Roberts
54
. New Delhi 110016. Jiann-Jong Chen Department of Electronic Engineering National Taipei University of Technology Taipei.com/orcadcapture. 3. Wen-Ta Lee. New Delhi 110012. Trong-Yen Lee.
OrCAD website for PSpice (http://www.orcad.aspx) 4. Hauz Khas. 5. RAJPUT1.References:
1. Taiwan.O. download. Delhi. Lu-Po Liao. Current conveyor theory and practice
Adel S. (http://www.orcad.)
2. Dr. National Physical Laboratory. R. has application notes. examples and interesting links. K. (Cadence Design Systems. Indian Institute of Technology.aspx). India 2Department of Electrical Engineering. OrCAD Corp. India
6.S.S. PSpice User’s manual. Low Power and High Performance Current Conveyors for Low Voltage Analog and Mixed Mode Signal Processing Applications∗ S. Chia-Chun Tsai. Low Voltage.