UNITED

STAlES

PAlENT

AND TRADEMARK

OFFICE
UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS
P.O. Box 1450 Alexandria, Virginia www.uspto.gov 22313-1450

APPLICATION

NO.

FILING DATE 02/2712009 7590
07/30/2012

FIRST NAMED INVENTOR

ATTORNEY

DOCKET NO.

CONFIRMATION

NO.

95/001,152
22852

6,324,120

8963.002.RXUSOO
EXAMINER ESCALANTE,OVIDIO ART UNIT 3992

4649

901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413

LLP

FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER

PAPER NUMBER

MAIL DATE

DELIVERY

MODE

07/30/2012

PAPER

Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication.

PTOL-90A

(Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE

BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES

Inter Partes RAMBUS, INC. Patent Owner v. SAMSUNG ELECTRONICS, CO., LTD. and MICRON TECHNOLOGY INC. Requestors

Appeal 2011-009664 Reexamination Control Nos. 95/000,178 & 95/001,152 United States Patent 6,324,120 B2 Technology Center 3900

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and STEPHEN C. SIU, Administrative Patent Judges. EASTHOM, Administrative Patent Judge.

DECISION ON (RAMBUS'S) REQUEST FOR REHEARING

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 Rambus seeks relief in its Patent Owner's Request for Rehearing, see 37 C.P.R. § 41.79, from the Decision of the Board of Patent Appeals and Interferences reversing the Examiner's decision not to maintain the rejections of claims 26, 29, and 33 and affirming the Examiner's decision to reject claims 1-4, 6, 8-11, 15, 16, 19, and 21-25.1 In Response, Micron filed Third Party Requestor's Comments to Patent Owner's Request for Rehearing Opposing Rambus's Request ("Micron's Opposing Comments"). In a rehearing request, appellants have the burden to "state with particularity the points believed to have been misapprehended or overlooked by the Board." 37 C.P.R. § 41.52 (a)(1). Rambus has not made the requisite showing. A. The Board's Decision to Affirm the Rejection of Claims 1-4, 6, 811, 15, 16, 19, and 21-25. Rambus seeks reconsideration of the Board's affirmance of the Examiner's anticipation rejection of the claims listed supra based on iAPX. (Bd. Dec. 4-11; Rambus Reh'g Req. 1.) Rambus maintains that the Board improperly relied on Micron's Responsive Brief which the Office, by petition decision, ruled expunged. (See Rambus Reh' g Req. 21 (citation omitted).) Rambus fails to explain how any consideration of Micron's expunged Respondent Brief shows Examiner error as to the claim rejections. The Board considered Rambus's appeal from the decision by the Examiner. (See Bd. Dec. 2, 3 (quoting 37 C.P.R. 41.77 (a): "'The Board ... may affirm or reverse each decision of the examiner on all issues raised on Decided January 19,2012 after oral hearing of this appeal and a related inter partes reexamination appeal (App. No. 2011-008431) involving the same parties.
1

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 each appealed claim .... "').) The Board relied, in part, on two previous Board decisions, adopting and incorporating them by reference. (Bd. Dec. 6 (relying on BPAI 2011-008431 and 2010-011178).) The Board also included separate findings, most of which coalesced with those prior decisions. (See Bd. Dec. 4-11.) Rambus does not point to anywhere in the Decision wherein any Board reliance on Micron's Responsive Brief redounds to a reversal of the rejection. A cursory inspection of the Decision's iAPX anticipation analysis reveals only four Board cites to Micron's Responsive Brief, and each cite thereof has parallel cites to either Rambus's Appeal Brief, the Examiner's RAN (Right of Appeal Notice), the' 120 patent, or a combination thereof. For example, the Decision reasons as follows: Rambus's arguments reduce to the unsupported argument that the claims, which recite a "synchronous memory device," require a single chip. (See Rambus App. Br. 6-26; accord Micron Resp. Br. 14 ("Rambus's brief relies on substantially the same single-chip argument rebutted above (although stated in different forms), and should be rejected because the relevant claims are not limited to single-chip structures.").) (Bd. Dec. 7.)2 Rambus does not dispute that the arguments addressed in the quotation were not single-chip arguments of one form or another. The Decision's iAPX anticipation analysis stands separately and without any

See also Bd. Dec. 8-9 (citing Rambus's Appeal Brief, the RAN, and Micron's Responsive Brief in parallel; Bd. Dec. 10 (citing the' 120 patent, the RAN, Micron's Responsive Brief, and a Federal Circuit decision (n.7) essentially in parallel; Bd. Dec, 10-11 (citing Rambus's Appeal Brief, Micron's Responsive Brief and the RAN in parallel).)
2

3

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 necessary support from Micron's Responsive Brief. To address Rambus's concerns, the Decision is hereby considered to be without the citations to Micron's Responsive Brief.3 Rambus's sought-after relief seeking "rehearing and reversal of the Examiner's rejection over iAPX" (Rambus Reh'g Req. 21) is granted as to the rehearing but denied as to the reversal. B. The Board's Decision to Reverse the Examiner's Decision to Confirm Claims 26,29, and 33. 1). Claims 26 and 29 as Obvious over Bennett Rambus incorrectly contends that Micron did not propose an obviousness rejection. (Rambus Reh'g Req. 1-2.) The Decision explains how Micron did. (See Bd. Dec. 15-16; accord Micron's Opposing Comments 1-2). Moreover, the Board remanded the rejection as a new ground so that whether or not Micron originally proposed the rejection is not material. (See Bd. Dec. 17; 28 n. 22.)4 Rambus also asserts that the Decision overlooked its expert testimony that large memories in Bennett have up to 232 addresses which points skilled artisans to cards, and not chips. (Reh'g Req. 3.) Rambus also contends that "Bennett's memory ... [is] not a synchronous DRAM, which is a single chip." (See Rambus Reh'g Req. 4.)

Micron "preserves its right to appeal the Office's Decision ... which expunged Micron's Respondent Brief form the record." (Micron's Opposing Comments 7.) 4 Citing 37 C.P.R. § 41.77(b) (denominating a reversal of a refusal to reject as a new ground of rejection even ifbased on the "Board['s] ... knowledge of any grounds not raised in the appeal").
3

4

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 Rambus's contentions do not address in a persuasive fashion the Board's rationale that the Examiner "erred by failing to maintain the rejection of claims 26 and 29 based on the unsupported conclusion that it would not have been obvious to employ a well-known DRAM as a substitute for a similar generic memory chip as disclosed by Bennett." (Bd. Dec. 17.) Bennett's generic synchronous single-chip memory disclosure and Rambus's concession that DRAMs were a well-known, if not dominant, type of memory chip (see, e.g., Rambus Reh' g Req. 2, n.2) render obvious the claimed combination. (See Bd. Dec.14-17) (citing the Action Closing Prosecution at 112-113 (finding that Bennett discloses a synchronous memory devicej.)? Moreover, the claims at issue do not require 232 addresses so that the argument is not commensurate with the claim scope. Rambus' s similar contention that Bennett does not show how to employ "two or three PC cards worth of memory together with the VBI ... on a single DRAM chip" (Rambus Reh' g Req. 4) has nothing to do with the rejection, is not commensurate with the claim scope, and attempts to shift focus from the thrust of the obviousness rejection which does not require forming such large memories. And as Micron points out, Mr. Murphy, Rambus's expert, cites to Bennett's disclosure of "'up to 232 addresses of 32 bit words. '" (Micron Cr. App. Br. 9 (quoting Murphy Decl. at,-r 55).) As Micron explains, Bennett is not only forward looking and contemplates large address space in future memory chips, but Bennett also specifically contemplates less address space Reference is to the ACP in the USPTO's EDAN computer system for Reexamination Control No. 95/001,152.
5

5

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 in chips having a small number of pins. (See Micron Cr. App. Br. 7-9.) The Decision relies on Micron's citations to Bennett as responding to Rambus's contentions, including Rambus's reliance on Murphy. (See, e.g., Bd. Dec. 16 (citing Micron Cr. App. Br. 5-9; Micron Reb. Br. 4-7).) Rambus also contends that the Board overlooked its own waiver procedures with regard to Micron's failure to "show in its Appeal brief how Bennett discloses the other features of claims 26 and 29. (Rambus Reh' g Req. 5.) As indicated supra, the Decision primarily focuses on how the Examiner erred by considering Micron's Cross-Appeal Brief and Rambus's responses thereto. Rambus does not direct the Board's attention to authority mandating a procedural burden on Micron, on appeal, to repeat the Examiner's findings with which Micron agrees as to "the other features of claims 26 and 29." Recognizing that the Examiner had not made relatively "recent" findings, the Decision states that "[o]n remand, the Examiner has discretion to sort out the various contentions and make specific findings either way." (See Bd. Dec. 17.)6 Rambus's related argument that "by not presenting arguments in its appeal brief, Micron foreclosed any opportunity that Rambus would have had to rebut Rambus' s arguments in Rambus' s respondent brief' describes a proper procedure, contrary to Rambus' s argument that the Board should not Under 37 C.P.R. § 41. 77 (b), the Decision contemplates a possible reopening of prosecution to the Examiner (a remand) in part because the record reflects that more recent findings by the Examiner (i.e., as to Bennett's BUSY signal block read operation) may contradict earlier findings made in this reexamination proceeding. (See Micron Reb. Br. 8, n. 1.) Our Decision invites the Examiner to sort out any contradictions (that may exist), but Rambus chose not to exercise the option of presenting arguments and evidence to the Examiner.
6

6

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 have allowed that procedure. (See Rambus Reh'g Req. 5.) That is, 37 C.F.R. § 41.68 (a) (3) states that "[t]he respondent brief shall be limited to issues raised in the appellant brief to which the respondent brief is directed." The rules also provide opportunity for new arguments in a rehearing to respond to a new ground of rejection in lieu of a remand to the Examiner. See 37 C.F.R. § 41.79 (b) (2) and (3). Rambus argues that Board overlooked its evidence cited in its Respondent Brief that Bennett fails to disclose block size information as set forth in claims 26 and 29. (Rambus Reh'g Req. 6.) Rambus somewhat contradicts itself by pointing out that Micron referred to its request for reexamination in its Rebuttal Brief to show the claimed elements "which the Board should have disregarded." (Rambus Reh'g Req. 6.) The Board relied

on Micron's Reexamination Request, Appeal Brief, Rebuttal Brief, and the Examiner's Non-Final Office Acton, RAN and Action Closing Prosecution findings, and Rambus's Brief and proffered evidence, i.e., the record, to arrive at its conclusion of obviousness. (See Dec. 16-17 (citations omitted).) For example, Micron's Rebuttal Brief points out that the Examiner's NonFinal Office Action and RAN agree with Micron's contention that Bennett's VII and VIII parameters specify the block size for single word reads. (See Micron Reb. Br. 8.) The Board (BPAI 2012-001638) recently, relying in part on a federal District Court proceeding involving the same parties and similar issues, considered Rambus's similar arguments on the merits about the block size information element (and other similar elements) as recited in similar

7

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 claims." The previous District Court Order (note 7) and the Board's prior , 1638 decision make extensive factual findings with respect to Bennett and the same or related claim element in dispute here. The Board's prior findings and conclusion with respect to the block size information element in its prior decision (BP AI 2012-001638 at 6-8, 18-21), are adopted and incorporated by reference. The' 1638 decision and our findings comport with the Examiner's findings in this reexamination proceeding. (See e.g., Non-Final Office Action at 122-123 (July 22,2009).) But because the prior

, 1638 decision is newly incorporated by reference herein, out of caution and to provide further opportunity for response, this Rehearing Decision is hereby denominated a new one with respect to the block size information element pursuant to 37 C.F.R. § 41.79 (d). Rambus also tangentially argues that the Board overlooked Rambus's contention that Bennett does not disclose that the clock would have been provided to a DRAM, but would have been provided to a separate VBI interface on the bus. (See Rambus Reh'g Req. 5.) But as Micron's Rebuttal Brief essentially points out, this argument is a variation of Rambus' s numerous single-chip arguments. (See e.g., Micron Reb. Br. 10-11 (responding to Rambus's assertion that Bennett discloses asynchronous memory devices); Non-Final Office Action at 121 (finding Bennett discloses December 15,2008 Order Granting in Part and Denying in Part Rambus's Motion to Strike; Denying Motion for Summary Judgment No.1 of Invalidity; and Striking Motion for Summary Judgment No.2 of Invalidity, Hynix Semiconductor Inc. v. Rambus Inc., No. 00-2905, Rambus Inc. v. Hynix Semiconductor Inc., No. 05-334, Rambus Inc. v. Samsung Electronics Co., Ltd., No 05-2298 RMW, and Rambus Inc. V. Micron Technology, Inc., No. 06-244 (N.D. Cal.) (stayed, Judge R. Whyte) (attached as Ex. 0-3 to the Rambus's respondent brief in the 2012-001638 reexamination proceeding).
7

8

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 a clocked (i.e., synchronous) dynamic random memory device).) As indicated supra, the Decision finds a synchronous memory dynamic random memory device obvious over Bennett based on a thorough review of the citations and arguments by Micron and Rambus and the findings by the Examiner. (See Bd. Dec. 14-16.) The prior' 1638 Board decision (at 8-11) also addresses similar arguments (as does the District Court order). Rambus fails to show that the Board overlooked a point warranting affirmance of the Examiner's decision not to reject claims 26 and 29 based on Bennett.

2) Claim 33 as Obvious Based on Bennett, and either of Wicklund, Bowater, or Olson. Rambus maintains that the Board overlooked evidence concerning the obviousness rejections based on Bennett and either of Wicklund, Bowater, or Olson. (Rambus Reh'g Req. 7-12.) As Micron contends, Rambus largely restates the same arguments the Board considered in its Decision. (See Micron's Opposing Comments 2.) Rambus's contention that the Board relied on findings by the Examiner made prior to the RAN in which the Examiner "reversed his position" mischaracterizes the record. (See Rambus Reh'g Req. 7 (citing Bd. Dec. at 17.).) The Board cited the Examiner's earlier finding that Bennett discloses an operation code, which the Board pointed to as met by, for example, Bennett's read-modify-write operation.
(See Bd. Dec. 17 (citing Micron Reb. Br. 11 which in tum cites the July 22,

2009 Office Action).)

Rambus fails to point to anywhere in the record

where the Examiner reversed that position.

9

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 Rambus also contends that the Board misapprehended claim 33 by reasoning that the "precharge information" constitutes nonfunctional descriptive material. (See Rambus Reh'g Req. 7-8.) But Rambus fails to rebut the thrust of the opinion which reasons that "claim 33 does not require the memory device ... to operate any differently based on that [precharge] information (i.e., as compared to some other type of information." (Dec. 18.) Rambus argues that the "DRAM outputs data in response to the operation code containing the precharge information." (Rambus Reh'g Req. 8.) That vague response does not even allege that the pre charge information portion of the operation code produces a responsive output. (Cf claim 15 "the operation code instructs the memory device to perform a read operation.") Rambus also argues that "the pre charge information tells the memory whether to precharge." (Rambus Reh'g Req. 8.) This argument contradicts the vague statement implying that the precharge information tells the device to output data, and it also attempts to incorporate limitations from the specification. Claim 33 does not require the device to do anything with the precharge information and merely adds the limitation that a "code includes pre charge information."
(See Bd. Dec. 18.)

Rambus points to the Board's citation to Wicklund as showing that the Board relies on a refresh cycle which is different than a pre charge cycle. (Rambus Reh'g Req. 8-9.) But the Board does not rely on refresh specifically, and Rambus does not dispute the thrust of the Decision finding that it was known in prior art systems (such as Wicklund's, Bowater's, and Olson's) that "precharge normally (i.e., when the DRAM is not in page mode) occurs at the end of a read or write function." (Bd. Dec. 17.)

10

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 Rambus also contends that prior art controller's had to issue two separate instructions, a read followed by a precharge, and that this somehow shows the unobviousness of "'banding'" the two separate instructions together into a single operation code. (Rambus Reh'g Req. 9.) The two signals were intimately related in the prior art with one normally following the other, thereby rendering the "banding" of the two in Bennett's operation code obvious, where Bennett bands together other instructions in an operation code such as the "read-modify-write." (See Bd. Dec. 17.)

Rambus's related contentions, for example, alleging "required additional logic" and a requirement for a controller's knowledge of "page boundaries" in large systems (Rambus Reh'g Req. 12), fail to show that the Board overlooked a material point related to the obviousness of sending the pre charge in an instruction for a read based in part on the undisputed finding that a precharge follows a read in the normal non-page mode in prior art systems. (See, e.g., Rambus Reh' g Req. 11-12.) Rambus also does not explain why ordinarily skilled artisans would have been unable to add additional logic which may have been required. Further, the claims at issue neither require a large system nor a page mode. In any event, a controller issuing a simple instruction involving a normal read and pre charge would not have been required to be aware of page boundaries which might occur in a page mode. Rambus fails to show that the Board overlooked a point warranting affirmance of the Examiner's decision not to reject claim 33 based on Bennett, and either of Wicklund, Bowater, or Olson.

11

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 3) Claims 26 and 29 as Obvious Based on iAPX and iRAM. Rambus argues that the Board "ignored the teachings of iRAM taken as a whole and instead relied on selected portions." (Rambus Reh'g Req. 13.) Rambus also maintains that nothing in iRAM suggests integrating the whole controller of iAPX. (Id.) But the device claims at issue do not require integrating the whole controller as the Decision explains. (See Bd. Dec. 19-20.) The Decision explains how Micron relied on a suggestion for some of the functions in the MCU interface as a simple integrated solution, as further suggested by iRAM's solution of integrating some MCU functions with DRAMs. (See Dec. 18-20.) Rambus maintains that the disclosed iRAM devices do not have a clock and thus are not synchronous. (Rambus Reh'g Req. 15.) The Board cited to page 3-446 of the AP-132 portion ofiRAM (see Dec. 20 (citing II which cites the noted page at Dec. 12).) The cited iRAM page describes "synchronous 2187 iRAM ... running at 10MHz by utilizing a method known as clock stretching." Rambus fails to show an overlooked point and in any case, the MCU and DRAMs function synchronously as a unit (i.e., a device), and the specific iRAM teaching adds to the myriad of discussed factors supporting obviousness. Rambus fails to show that the Board overlooked a point requiring affirmance of the Examiner's decision not to reject claims 26 and 29 based on iAPX and iRAM. 4) Claims 33 as Obvious Based on iAPX, iRAM, and Olson Rambus maintains that the Board overlooked its argument that Micron lacks standing to argue the proposed rejection. (Rambus Reh'g Req. 15.) To the contrary, the Board implicitly decided against Rambus as to standing 12

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 as it has done in related appeals involving similar standing arguments. (See discussion below). Also, the Board has discretion to enter new grounds of rejection regardless of the source for the rejection. (See supra note 4.) Rambus also maintains that the Board overlooked its proffered evidence indicating that any modification for sending precharge information would have been to the MCU in the iAPX system which is part of the memory device according to the rejection, and Rambus also maintains that the controller in the iAPX system would have "no perspective on where the page boundaries are located." (See Rambus Reh'g Req. 16.) These arguments are beyond the scope of the memory device claimed which does not require a page mode or controllers. And even if a controller or other requestor is somehow implicitly required, skilled artisans would have recognized that an iAPX modified controller would have had sufficient "perspective" to send a pre charge signal to an integrated DRAM in the same code as the read signal since the pre charge signal normally would have followed the controller's read signal in prior art systems (especially where the claims do not require a page mode; i.e., a mode which requires such "perspective" according to Rambus). Rambus fails to show that the Board overlooked a point requiring affirmance of the Examiner's decision not to reject claims 26 and 29 based on iAPX, iRAM, and Olson. 5.) Secondary Considerations. Rambus contends that the Board overlooked evidence showing a known projected speed difference between microprocessors and DRAMs, and also overlooked Dr. Farmwald's solution, which all occurred in the late

13

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 1980s to 1990. Rambus also alleges the Board overlooked other evidence.
(See Rambus Reh'g Req. 17-19.)

But the Board found that Rambus' s evidence showed that known solutions kept pace with any speed-gap problems until at least the filing of the grandparent application in 1990, i.e., that Dr. Farmwald's DRAM proposed a single-DRAM solution related to a problem predicted to occur in the future. (See Bd. Dec. 24.) Dr. Farmwald's testimony supports that finding and shows that any speed gap at the time of filing of the invention was satisfied by other solutions and that the gap would not be satisfied by a single DRAM as broadly recited in claims 26, 29, and 33 (assuming arguendo these claims require a single DRAM). For example, Dr. Farmwald states that "even up into the early part of the '90's, it wasn't going to be a problem" because more DRAM chips could be used in "an expensive system," and "that's why we were up here at 50 [DRAM chips] in 1990." (E-5 at 276; see Bd. Dec. 24.)8 He also testified to building a "500 Megahertz [DRAM] running at 8 Bits wide" as a goal at "somewhere between 1995 and 2000," (id. at 277) or maybe in '''93, '94,
'95" (see id. at 278).

Primarily, Rambus does not show that the Board overlooked or misapprehended that fact that Dr. Farmwald testified to future problems to be solved by his touted solution - i.e., a single 8-bit wide DRAM running at 500MHz. And in 1990, at the time of filing, Dr. Farmwald was employing

8 See Rambus's Rehearing Request at 19 (citing "E-5.") "E-5" designates Trial Testimony Excerpts of Michael Farmwald (listed as an 8 page NPL submission of Sept. 5, 2008 as Exhibit E-5 in the USPTO EDAN 95/000,178 reexamination file.). 14

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 an expensive multichip solution so that there essentially was not an unsolved long-felt problem in 1990 at the time of filing, as the Board reasoned. Bd. Dec. 24.) Rambus's testimony. cited marketing articles do not contradict Dr. Farmwald's

(See

The cited article to Clark only reports what Rambus "claims" assertion that the articles

(Clark at B 1) to have solved despite Rambus's

show the existence of a long-term problem at the time of filing." The Clark article does not show how any purported solution relates to the claims at issue here. Rather, the article states that the new design "requires a fundamental redesign oftoday's popular memory chips, known as DRAMs,

and other chips that work with them." (Clark B 1.) The article also points
out that any Rambus-based system involves more than a single chip, i.e., "a

reduced number of chips," and that some companies were interested in Rambus "mainly for the next generation of 1[?] megabit DRAMs." (Clark

B3.) Moreover, the article points out that any Rambus solution" avoids

more expensive memory chips, including SRAMs."

(Id. (emphasis added).)
Any touted 500

In other words, the article does not help Rambus.

MHz speed advantage comes from modifying DRAMs and other chips required to work as a system, companies were interested in the next generation of DRAMs, and Rambus's previous "expensive" purported solution, merely avoids Rambus fails to show that

solutions using SRAMs.

Rambus only specifically points the Board to "R39338," an article to Clark, "Rambus Speeds Up Memory Chips," San Francisco Chronicle (March 1992). (See Rambus Reh'g Req. 19 (generally citing all the articles in Exhibit L of the Resp. Br).)
9

15

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 the Board overlooked evidence pointing to a solution of a long-felt need or any other evidence supporting nonobviousness. The claims at issue here read on a variety of memory devices, including slow devices, since the claims do not recite speed (as a functional limitation). And as the Board reasoned, the evidence suggests that any commercial success would have been due to a whole host of other unclaimed features helping to gain the touted 500 MHz speed (also unclaimed) from a single DRAM. (See Bd. Dec. 23-24 (listing other unclaimed features).) In other words, the claims lack a nexus to and are not commensurate in scope with the proffered showing as the Decision explains. (See id.) Rambus's point that commercial success was due to the "single chip synchronous DRAM of claims 26, 29, and 33" (Rambus Reh'g Req. 18) also does not show that the Board overlooked a material point. Rambus does not proffer sufficient evidence showing that praise, success, or other evidence of unobviousness, were based solely on the broadly recited synchronous DRAM - i.e., one not specifically or implicitly requiring the touted high speeds andlor other unclaimed features cited by the Board as necessary to obtain that speed. The Board specifically considered "a single chip DRAM" as encompassed by claims 26, 29, and 33. (See Bd. Dec. 22.) 6.) Other Contentions Rambus's contention that the Board did not address Rambus' s argument that the Board does not have authority to address written description issues lacks relevance. The Board has authority to address priority issues and in any case, decided the issue in Rambus's favor, rendering any lack of authority moot. (See Rambus Reh' g Req. 21; Bd. Dec. 27.) 16

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 Rambus's contention that the Board "[s]urprisingly ... did not address Rambus's arguments regarding Micron's [lack of] standing, but the Board did consider and address the Samsung' s issues that Micron attempted to appeal" (Rambus Reh'g Req. 20), fails to show the Board overlooked a consideration. Rambus's standing argument was addressed previously in a petition decision in this and numerous other reexamination proceedings which Rambus apparently chose not to appeal to a district court. 10 Fundamentally, as the petition decisions reason, the Board has authority to consider appeals from decisions by the Examiner. (See Bd. Dec. 2- 3 (citing 37 C.F.R. 41.77 (a) "The Board ... may affirm or reverse each decision of the examiner on all issues raised on each appealed claim ....").)

CONCLUSION Rambus fails to show that the Board overlooked a point requiring affirmance of the Examiner's decision not to reject claims 26, 29, and 33.

REHEARING DECISION The Rehearing Decision is designated as a new decision under 37 C.F.R. § 41.79 (d) with the Board's prior Decision deemed to be without reference to Micron's expunged Responsive Brief and with the Board's prior As Micron notes, the petition decision sanctions Micron's participation in the merged proceeding. See Micron's Opposing Comments 7 (citing Dec. on Petitions 4 (June 7, 2011 ) (referring to and relying on related petition decisions and reasoning that "Micron ... was permitted to address the rejections and proposed rejections that were before the Office at the time of the RAN.").
10

17

Appeal 2011-009664 Reexamination Control 95/000,178 & 95/001,152 Patent 6,324,120 decision (BPAI 2012-001638) adopted and incorporated by reference in response to Rambus' s contention that the Board overlooked evidence related to the block size information element recited in claim 26. We otherwise decline to modify the Decision affirming the Examiner's decision to reject claims 1-4,6,8-11, 15, 16, 19, and 21-25 and

reversing the Examiner's decision to confirm claims 26,29, and 33.

DENIED

ak

Counsel for Patent Owner: Naveen Modi, Esq. Finnegan, Henderson, Farabow, Garrett & Dunner, LLP 901 New York Avenue, NW Washington, DC 20001-4413 Counsel for Third Party Requester Samsung Electronics Co., Ltd.: David L. McCombs, Esq. Haynes and Boone, LLP 2323 Victory Avenue, Suite 700 Dallas, TX 75219 Counsel for Third Party Requester Micron Technology Inc.: Tracy W. Druce Novak Druce & Quigg, LLP (NDQ Reexamination Group) 1000 Louisiana Street, 53rd Floor Houston, TX 77002 18