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E1771E11

E1771E11

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DATA SHEET

1G bits GDDR5 SGRAM
EDW1032BBBG (32M words x 32 bits)
Specifications
• Density: 1G bits • Organization — 2Mbit x 32 I/O x 16 banks — 4Mbit x 16 I/O x 16 banks • Package — 170-ball FBGA — Lead-free (RoHS compliant) and Halogen-free • Power supply: — VDD: 1.5V ±3% and 1.35V ± 3% — VDDQ: 1.5V ±3% and 1.35V ±3% • Data rate: 7.0Gbps/6.0Gbps/5.0Gbps/4.0Gbps (max.) • 16 internal banks • Four bank groups for tCCDL = 3tCK • 8n prefetch architecture: 256 bit per array Read or Write access; 128 bit for x16 • Burst length (BL): 8 only • Programmable CAS latency: 6 to 20 • Programmable Write latency: 3 to 7 • Programmable CRC READ latency: 0 to 3 • Programmable CRC WRITE latency: 8 to 14 • Programmable EDC hold pattern for CDR • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/32ms • Interface: Pseudo open drain (POD-15) • On-die termination (ODT): nom. values of 60Ω or 120Ω • Pseudo open drain (POD-15) compatible outputs — 40Ω pulldown — 60Ω pullup • ODT and output driver strength auto-calibration with external resistor ZQ pin (120Ω) • Programmable termination and driver strength offsets • Selectable external or internal VREF for data inputs; programmable offsets for internal VREF • Separate external VREF for address / command inputs • Operating case temperature range — TC = 0°C to +95°C

Features
• x32/x16 mode configuration set at power-up with EDC pin • Single ended interface for data, address and command • Quarter data-rate differential clock inputs CK, /CK for address and commands • Two half data-rate differential clock inputs WCK, /WCK, each associated with two data bytes (DQ, /DBI, EDC) • Double Data Rate (DDR) data (WCK) • Single Data Rate (SDR) command (CK) • Double Data Rate (DDR) addressing (CK) • Write data mask function via address bus (single/double byte mask) • Data Bus Inversion (DBI) and Address Bus Inversion (ABI) • Input/output PLL on/off mode • Address training: address input monitoring via DQ pins • WCK2CK clock training: phase information via EDC pins • Data read and write training via Read FIFO (FIFO depth = 6) • Read FIFO pattern preload by LDFF command • Direct write data load to Read FIFO by WRTR command • Consecutive read of Read FIFO by RDTR command • Read/Write data transmission integrity secured by cyclic redundancy check (CRC–8) • Read/Write EDC on/off mode • DQ Preamble for Read on/off mode • Low Power modes • RDQS mode on EDC pin • On-chip temperature sensor with read-out • Automatic temperature sensor controlled self-refresh rate • Digital tRAS lockout • Vendor ID, FIFO depth and Density info fields for identification • Mirror function with MF pin • Boundary Scan function with SEN pin

Document No. E1771E11 (Ver. 1.1) Date Published September 2011 (K) Japan Printed in Japan URL: http://www.elpida.com

Elpida Memory, Inc. 2011

0Gbps Package BG: FBGA Revision Data Sheet E1771E11 (Ver. 1.0 Package 170-ball FBGA Part Number E D W 10 32 B B BG .0 6.EDW1032BBBG Ordering Information Part number EDW1032BBBG-40-F EDW1032BBBG-50-F EDW1032BBBG-60-F EDW1032BBBG-70-F Organization (words x bits) 32M x 32 Max.5V Environment Code F: Lead Free (RoHS compliant) and Halogen Free Speed 40: 4.0 7.0Gbps 70: 7.0Gbps 60: 6. Interface B: VDD = 1.F Elpida Memory Type D: Packaged Device Product Family W: GDDR5 SGRAM Density/Bank 10: 1Gb/16-bank Organization 32: x32 Power Supply.0Gbps 50: 5.0 5.1) 2 .60 . Data Rate (Gbps/pin) 4.

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1.1) 3 . Data Sheet E1771E11 (Ver.

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Function Clock Data Clocks Clock Enable Chip Select Command inputs Bank Address inputs Address inputs Data Input/Output Data bus inversion Error Detection Code Address bus inversion /xxx indicates active low signal.      9664 9''4 9664 9''4 9664 9''4 :( 9''4 &. /WE BA0 .1) 4 . '4 '4 9''4 9664 =4 9664 9''4 '4 '4 '%. $ $ 9'' '4 '4 9''4 9664 966 $ $ 1& $ $ 966 9664 9''4 5(6(7 &.( 9664 9''4 '4 '4 '%. /WCK23 /CKE /CS /RAS.DQ31 /DBI0 ./DBI3 EDC0 . /WCK01. /CAS.BA3 A0 . 9664 9''4 &$6 9''4 '4 '4 9'' $ $ $%. :&. ('& '4 '4 9''4 5$6 9''4 9664 9''4 :&. WCK23. ('& '4 '4  9664 9''4 9664 9''4 9664 9''4 9'' 966 95()& 966 9'' 9''4 9664 9''4 9664 9''4 9664 95()' '4 966 9'' 966 9''4 9664 966 %$ $ 6(1 %$ $ 966 9664 9''4 966 9'' 966 95()' '4 9664 9'' '4 '4 9'' %$ $ &. /CK WCK01. Signal ZQ /RESET MF SEN VREFC VREFD VDDQ VSSQ VDD VSS NC Function Impedance Reference Reset Mirror Function Scan Enable Reference voltage for command and address Reference voltage for DQ and /DBI I/O power I/O ground Power supply Ground Not connected Data Sheet E1771E11 (Ver. %$ $ 9'' '4 '4 9'' 9664 '4 '4 9''4 :&.A11 DQ0 . 9664 9''4 9664 9664 '4 '4 9'' 966 1& SLQ LV 2)) LQ [ PRGH Signal CK. 9''4 &6 9''4 9664 9''4 9664 9''4 9664  '4 '4 ('& '%. :&. 1.EDC3 /ABI Note: 1.

Commands are registered at every rising edge of CK. an access starts at a selected location and continues for a total of eight data words. Data Sheet E1771E11 (Ver. The GDDR5 SGRAM uses a 8n prefetch architecture and DDR interface to achieve high-speed operation. GDDR5 replaces the pulsed strobes (WDQS & RDQS) used in previous DRAMs such as GDDR4 with a free running differential forwarded clock (WCK.073.EDW1032BBBG 1. Accesses begin with the registration of an ACTIVE command. The device can be configured to operate in x32 mode or x16 (clamshell) mode. Configuration The Elpida GDDR5 SGRAM is a high speed dynamic random-access memory designed for applications requiring high bandwidth. which is then followed by a READ or WRITE command. The GDDR5 SGRAM operates from a differential clock CK and /CK. /WCK) with both input and output data registered and driven respectively at both edges of the forwarded WCK. Corresponding to the 8n prefetch a single write or read access consists of a 256 bit wide. Read and write accesses to the GDDR5 SGRAM are burst oriented. The address bits registered coincident with the ACTIVE command and the next rising /CK edge are used to select the bank and the row to be accessed.1) 5 . The mode is detected during device initialization. It contains 1. 1.741. two CK clock cycle data transfer at the internal memory core and eight corresponding 32 bit wide one-half WCK clock cycle data transfers at the I/O pins.824 bits and is internally configured as a 16-bank DRAM. The GDDR5 interface transfers two 32 bit wide data words per WCK clock cycle to/from the I/O pins. Addresses are registered at every rising edge of CK and every rising edge of /CK. The address bits registered coincident with the READ or WRITE command and the next rising /CK edge are used to select the bank and the column location for the burst access.

/WCK01 is associated with DQ0-DQ15.EDC3 /ABI ZQ /RESET MF SEN VREFC VREFD VDDQ VSSQ VDD VSS NC Output Input Input Input Input Supply Supply Supply Supply Supply Supply - Data Sheet E1771E11 (Ver. Input WCK23. to select one location out of the memory array in the respective bank. WCK01. Data Input/Output: 32 bit data bus Data bus inversion: /DBI0 is associated with DQ0-DQ7. Bank Address inputs: BA0-BA3 define to which bank an ACTIVE. /RESET low asynchronously initiates a full chip reset. Error Detection Code: The calculated CRC data is transmitted on these pins. Clock Enable: /CKE low activates and /CKE high deactivates internal clock. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 low. /CK.DQ31 /DBI0 . /DBI1 with DQ8-DQ15. /CKE.A11 Input DQ0 . BA0-BA3 also determine which Mode Register is accessed with a MODE REGISTER SET command. Address inputs: A0-A11 provide the row address for ACTIVE commands. The value of /CKE latched at power-up with /RESET going high determines the termination value of the address and command inputs. EDC2 and EDC3. WCK clocks operate at nominally twice the CK clock frequency. /CKE must be maintained low throughout READ and WRITE accesses. Reference voltage for DQ and /DBI inputs. and /DBI3 with DQ24-DQ31. and EDC3 with DQ24-DQ31. Mirror Function: VDDQ CMOS input. WCK01. In addition these pins drive a hold pattern when idle and can be used as an RDQS function. device input buffers and output drivers. Chip Select: /CS low enables. All latencies are referenced to CK. BA0-BA3 are sampled with the rising edge of CK. /WE BA0 ./DBI3 I/O I/O EDC0 . Input buffers excluding CK. A8-A11 are sampled with the rising edge of CK and A0-A7 are sampled with the rising edge of /CK. All commands are masked when /CS is registered high. but internal command execution continues. Isolated power for the input and output buffers. The address inputs also provide the op-code during an MODE REGISTER SET command. /DBI2 with DQ16-DQ23. 1. /CAS. Isolated ground for the input and output buffers. Address inputs are latched on the rising edge of CK and the rising edge of /CK. Reference voltage for command and address inputs. /WCK01. and /CS high disables the command decoder. Command inputs are latched on the rising edge of CK. /WCK01. /CAS and /WE (along with /CS) define the command to be entered. Taking /CKE high provides Precharge Power-Down and SelfRefresh operations (all banks idle). EDC0 is associated with DQ0-DQ7. /WCK23 is associated with DQ16-DQ31. /DBI3. /CS provides for individual device selection on memory channels with multiple memory devices. Must be tied to Ground when not in use. EDC0 and EDC1. /DBI1. /DBI2. or Active Power-Down (row active in any bank). /CK Type Input Detailed Function Clock: CK and /CK are differential clock inputs. READ. Must be tied to Power or Ground. WCK23. EDC2 with DQ16-DQ23. /CS is considered part of the command code. Input buffers excluding /CKE are disabled during Self-Refresh.BA3 Input Input Input A0 . /WCK23 /CKE Input /CS /RAS.1) 6 . bank selected by BA0-BA3) or all banks (A8 high). Address bus inversion Impedance Reference: external reference pin for auto-calibration Reset: VDDQ CMOS input. and the data bits during LDFF commands. WRITE or PRECHARGE command is being applied. Scan Enable: VDDQ CMOS input.1 Signal Description Table 1: Signal Description Signal CK. WCK23. Power supply Ground Not connected WCK01. Data Clocks: WCK and /WCK are differential clocks used for WRITE data capture and READ data output. /DBI0. CK and /CK are externally terminated.EDW1032BBBG 1. With /RESET low all ODTs are disabled. A0-A5(A6) provide the column address and A8 defines the auto precharge function for READ and WRITE commands. Command inputs: /RAS. /CKE is synchronous for Power-Down entry and exit and for Self-Refresh entry. /WCK23 are disabled during Power-Down. EDC1 with DQ8-DQ15.

1) 7 . Table 3: Clamshell Mode and Mirror Function Mode x16 non-mirrored x32 non-mirrored x16 mirrored x32 mirrored MF VSSQ VSSQ VDDQ VDDQ EDC1 (MF=0) or EDC2 (MF=1) VSSQ VDDQ (terminated by the system or controller) VSSQ VDDQ (terminated by the system or controller) Data Sheet E1771E11 (Ver. The MF ball should be tied directly to VSSQ or VDDQ depending on the control line orientation desired. data and WCK pins assisting in routing devices back to back. meaning that the signal names shown in the respective functional description apply both to mirrored (MF=1) and non-mirrored (MF=0) modes. 1. The pins affected by this Mirror Function mode are listed in Table 2. the pin is part of the two bytes that are disabled in this mode and therefore not needed for EDC functionality.EDW1032BBBG 1. non-terminating. For x16 mode this pin is tied to VSSQ. 1. Table 2: Ball Assignment with Mirror Function Signal Ball A2 B2 C2 D2 E2 F2 M2 N2 P2 R2 T2 U2 G3 L3 MF=0 DQ1 DQ3 EDC0 /DBI0 DQ5 DQ7 DQ31 DQ29 /DBI3 EDC3 DQ27 DQ25 /RAS /CAS M=1 DQ25 DQ27 EDC3 /DBI3 DQ29 DQ31 DQ7 DQ5 /DBI0 EDC0 DQ3 DQ1 /CAS /RAS Ball A4 B4 D4 E4 F4 H4 K4 M4 N4 P4 T4 U4 D5 H5 MF=0 DQ0 DQ2 DQ4 DQ6 A10 A0 A8 A7 DQ30 DQ28 DQ26 DQ24 A9 A1 Signal M=1 DQ24 DQ26 DQ28 DQ30 A8 A7 A10 A0 DQ6 DQ4 DQ2 DQ0 A11 A6 Ball K5 P5 H10 K10 A11 B11 E11 F11 H11 K11 M11 N11 T11 U11 MF=0 A11 A6 BA3 A3 BA1 A5 DQ8 DQ10 DQ12 DQ14 BA0 A2 BA2 A4 DQ22 DQ20 DQ18 DQ16 Signal M=1 A9 A1 BA1 A5 BA3 A3 DQ16 DQ18 DQ20 DQ22 BA2 A4 BA0 A2 DQ14 DQ12 DQ10 DQ8 Ball G12 L12 A13 B13 C13 D13 E13 F13 M13 N13 P13 R13 T13 U13 MF=0 /CS /WE DQ9 DQ11 EDC1 /DBI1 DQ13 DQ15 DQ23 DQ21 /DBI2 EDC2 DQ19 DQ17 Signal MF=1 /WE /CS DQ17 DQ19 EDC2 /DBI2 DQ21 DQ23 DQ15 DQ13 /DBI1 EDC1 DQ11 DQ9 /WCK23 /WCK01 WCK01 WCK23 WCK23 WCK01 /WCK01 /WCK23 Functions within the GDDR5 SGRAM that refer to external signals are transparent with respect to Mirror Function mode. For x32 mode this pin is active and always terminated to VDDQ in the system or by the controller. The disabled pins in x16 mode will be in Hi-Z state. address. Once the configuration has been set.2 Mirror Function Mode The GDDR5 SGRAM provides a mirror function (MF) pin to change the physical location of the command. it cannot be changed during normal operation. Usually the configuration is fixed in the system.3 Clamshell Mode Detection The GDDR5 SGRAM can operate in a x32 mode or a x16 mode to allow a clamshell configuration with a point to point connection on the high speed data signals. The x16 mode is detected at power-up on the pin at location C-13 which is EDC1 when configured to MF=0 and EDC2 when configured to MF=1. The referenced package pin is determined by the Mirror Function mode the devices is configured to. The configuration is set with /RESET going high.

Table 5: Addressing Scheme 32M x 32 Row Address Column address Bank address Autoprecharge Page size Refresh Refresh period A0-A11 A0-A5 BA0-BA3 A8 2 KB 8k/32ms 3. The addresses should be provided to the GDDR5 SGRAM in two parts. as shown in Table 5. 1. 'DWD 1RWH WKH ILJXUH VKRZV WKH UHODWLRQVKLS EHWZHHQ WKH GDWD UDWH RI WKH EXVHV DQG WKH FORFNV DQG LV QRW D WLPLQJ GLDJUDP Figure 1: GDDR5 Clocking and Interface Relationship 1. DDR means that the data is registered at every rising edge of WCK and rising edge of /WCK. /CK).1) 8 . Commands are registered at every rising edge of CK. /CAS and /WE. &. GDDR5 uses a double data rate data interface and an 8n-prefetch architecture. :&.EDW1032BBBG 1. the first half is latched on the rising edge of CK along with the command pins such as /RAS.5 Addressing The GDDR5 SGRAM uses a double data rate address scheme to reduce pins required on the GDDR5 SGRAM as shown in Table 4. Table 4: Address Pairs Clock Edge Rising CK Rising /CK BA3 A3 BA2 A4 BA1 A5 Address Inputs BA0 A2 A11 A6 A10 A0 A9 A1 A8 A7 Addressing schemes for x32 mode and x16 mode differ only in the number of valid column addresses.9 µs Data Sheet E1771E11 (Ver. The use of DDR addressing allows all address values to be latched in at the same rate as the SDR commands. /WCK). Addresses are registered at every rising edge of CK and every rising edge of /CK. The data interface uses two differential forwarded clocks (WCK. the second half is latched on the rising edge of /CK. &. WCK and /WCK are continuously running and operate at twice the frequency of the command/address clock (CK. &RPPDQG $GGUHVV :&. All addresses related to command access have been positioned for latching on the initial rising edge for faster decoding.4 Clocking The GDDR5 SGRAM operates from a differential clock CK and /CK.9 µs 64M x 16 A0-A11 A0-A6 BA0-BA3 A8 2 KB 8k/32ms 3.

/CAS = L. WDM WDMA WRTR PRE REF PDE PDX SRE SRX PREALL L H = logic high level.5 2. 6. Double Byte Mask WRITE TRAINING PRECHARGE PRECHARGE ALL REFRESH POWER-DOWNENTRY POWER-DOWNEXIT SELF-REFRESHENTRY SELF-REFRESHEXIT Notes: 1.5.7 2 2. A0-A5 A9 (A6) Note X X X X 2. In address training mode READ is decoded from the command pins only with /RAS = H.5 2. This command is REFRESH when /CKE(n) = L. 1.8 2.EDW1032BBBG 1. X = Don’t Care.9 2. physical addresses are inverted when address bus inversion (ABI) is activated and /ABI=L.3 2. 3.5 2. BA0-BA3 provide the bank address. 9. but not floating.5 2 2 2 6 OPCODE RA L L H H L L L L H H H X X X X X X X WRITE with Autoprecharge. 5. /WE= H.5 2. BA0-BA3 and CA are used to select burst location (BST) and data. A0-A11 provide the row address (RA).6 Commands Table 6: Command Truth Table Operation DESELECT NO OPERATION (NOP) MODE REGISTER SET ACTIVATE READ READ with Autoprecharge LOAD FIFO READ TRAINING WRITE without Mask WRITE without Mask with Autoprecharge WRITE with Single Byte Mask Code DESEL NOP MRS ACT RD RDA LDFF RDTR WR WRA WSM /CKE /CKE n-1 n /CS L L L L L L L L L L L L L L L L L L H L H X X L L L L L L L L L L L L L L L L H L H L H L L L L L L L L L L L L L L L L L H L H L L H L /RAS /CAS /WE X H L L H H H H H H H H H H H L L L X H X H L X H X H L H L L L L L L L L L L L H H L X H X H L X H X H L H H H H H L L L L L L L L L H X H X H H X H BA3BA0 X X MRA BA BA BA BST X BA BA BA BA BA BA X BA X X X X X X A11 X X A10 X X A8 X X A6-A7. BA0-BA3 provide the Mode Register address (MRA). DESELECT and NO OPERATION are functionally interchangeable. 2. A0-A11 the opcode to be loaded. A0-A5 (A6) provide the column address (CA).1) 9 .5 2. Data Sheet E1771E11 (Ver. no sub-word addressing within a burst of 8. 4. 8. respectively. L = logic low level. Single WSMA Byte Mask WRITE with Double Byte Mask WRITE with Autoprecharge. Signal may be H or L.5 2.8 2. 7. Addresses shown are logical addresses.4 L L L H L L H H L L H X X X X X X X L H L L L H L H L H L L H X X X X X X X DATA X X X X X X X X X X X X X X X X CA CA CA CA CA CA X X X X X X X X 6 CA CA 2. and SELF-REFRESH ENTRY when /CKE(n) is H. BA0-BA3 provide the bank address (BA).

5 -0. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This is a stress rating only.5 -0.0 2.0 2. and functional operation of the device at these or any other conditions above those indicated in the operational sections of these specification is not implied. 2. -0.1) 10 . Electrical Characteristics Symbol VDD VDDQ VIN VOUT TSTG TJ IOUT Min. Data Sheet E1771E11 (Ver.5 -0. 1.0 2.5 -55 — — Max.EDW1032BBBG 2.0 +150 +125 50 Unit V V V V °C °C mA Table 7: Absolute Maximum Ratings Parameter Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSSQ Voltage on VREF and inputs relative to VSS Voltage on I/O pins relative to VSS Storage Temperature Junction Temperature Short Circuit output current Caution: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage of the device.

135 — VREFD . /DBI inputs with VREFD DC input logic high voltage for DQ.69 * VDDQ VREFC + 0.49 * VDDQ 0.0.15 — VREFD + 0. 8.5 — VDDQ .3095 0.51 * VDDQ 0.4.455 0.69 * VDDQ 0.7V/ns for POD135.56 125 Unit Note V V V V V V V V V V V V V V V μA μA V 9 9 10 11 2 2 3. Source of reference voltage and control of Reference voltage for DQ and /DBI pins is determined by VREFD. 0V ≤ VOUT ≤ VDDQ) Output logic low voltage External resistor value Notes: 1. 6.5 — VDDQ .3 — 0.0. 10. Any input 0V ≤ VIN ≤ VDDQ.30 — 0. Data Sheet E1771E11 (Ver.35 1.71 * VDDQ — VREFC . GDDR5 SGRAMs are designed to tolerate PCB designs with separate VDDQ and VDD power regulators.27 — VDDQ . VIHX and VILX define the input voltage levels for the receiver that detects x32 mode or x16 mode with /RESET going high. AC noise in the system is estimated at 50 mV peak-to-peak for the purpose of DRAM design. /DBI input slew rate must be greater than or equal to 3V/ns for POD15 and 2.0.35 — — — — — — — — — — — — — — — — 120 max.0.3 — 0.135 — VREFD + 0.5 — — — — — — — — — — — — — — — — 120 max.545 1.3 +5 +5 0.5 1.71 * VDDQ 0. /DBI inputs with VREFD2 DC input logic low voltage for DQ.455 1. 1.0. IOZ is measured with DQs disabled.3 — -5 -5 — 115 POD135 typ.69 * VDDQ VREFC + 0.1 Operating Conditions Table 8: DC Operating Conditions POD15 Parameter Device supply voltage I/O Supply voltage Reference voltage for DQ and /DBI pins Reference voltage for DQ and /DBI pins Symbol VDD VDDQ VREFD VREFD2 min. 4. MF VILR VIHX VILX Input leakage current (any input 0V ≤ VIN ≤ VDDQ.09 — VREFD2 . /DBI inputs with VREFD DC input logic low voltage for DQ. 0V ≤ VOUT ≤ VDDQ.3905 1. 1.0. 1. ADR/CMD input slew rate must be greater than or equal to 3V/ns for POD15 and 2. all other pins IL not under test = 0V) Output leakage current (DQs are disabled. 1. 1.10 — VREFD2 . 7.0. VREFD Offsets are not supported with VREFD2.545 0.69 * VDDQ 0. Half VREFD and VREFD Offset Mode Registers.5 6 External reference voltage for address and VREFC command DC input logic high voltage for address and VIHA(DC) command inputs DC input logic low voltage for address and command inputs DC input logic high voltage for DQ. 11.49 * VDDQ 0.3905 0.09 — VREFD2 + 0.15 — VREFD .1) 11 . MF Input logic high voltage for EDC1/2 (x16 mode detect) Input logic low voltage for EDC1/2 (x16 mode detect) VILA(DC) VIHD(DC) VILD(DC) VIHD2(DC) VILD2(DC) VIHR Input logic low voltage for /RESET. All voltages are measured at the package pins. The slew rate is measured between VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC). IOZ VOL(DC) ZQ Ω 0°C ≤ TC ≤ 95°C.71 * VDDQ — VREFC .4 3.27 — 0.30 — VDDQ . DB. 3. The slew rate is measured between VREFC crossing and VIHA(AC) or VILA(AC). 9. 1. 5.3095 1.7V/ns for POD135.3 — -5 -5 — 115 typ. SEN.0.10 — VREFD2 + 0.71 * VDDQ 0.0. all other pins not under test = 0V. 1. External VREFC is to be provided by the controller as there is no alternative supply. IL is measured with ODT off.51 * VDDQ 0. SEN. 2.62 125 min.EDW1032BBBG 2.0.3 +5 +5 0. /DBI inputs with VREFD2 Input logic high voltage for /RESET.

/WCK Clock input voltage level for CK.3 — — VREFC + 0. /CK Clock input differential voltage: CK.18 — VREFD . The input reference level for signals other than CK and /CK is VREFC.1 — — — — VDDQ + 0. VREFD2 or the internal VREFD.18 — VREFD + 0. The CK and /CK input reference level (for timing referenced to CK and /CK) is the point at which CK and /CK cross. VREFC + 0. Please refer to the applicable timings in the AC timings table.27 -0.6. VILA(AC) VIHD(AC) VILD(AC) VIHD2(AC) VILD2(AC) POD135 typ. VREFC . Data Sheet E1771E11 (Ver. All voltages are measured at the package pins.0.108 VREFD .0.10 max. For AC operations.0. VREFC + 0. and is nominally 70% of VDDQ with POD15.0.7 VREFC .40 — typ.5.0. VREFC .845V to a maximum of 1. VIDWCK is the magnitude of the difference between the input level in WCK and the input level on /WCK. 8. all DC clock requirements must be satisfied as well.15 — VREFD2 . WCK.8 0°C ≤ TC ≤ 95°C. Please refer to the applicable timings in the AC Timings table. 3. /CK Clock input differential voltage: CK.36 0.4.20 0.045V.135 — VREFD2 . 10.7 5. The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.198 0.15 — VREFD2 + 0.7 2. /CK. — VREFC . All voltages are measured at the package pins.0.0.20 — VREFD . /WCK Clock input differential voltage: WCK. — — — — — — max. 2.12 VREFD .1 — — — — VDDQ + 0. The input reference level for signals other than WCK and /WCK is either VREFD.36 Unit Note V V V V V V 0°C ≤ TC ≤ 95°C. 8. VIDCK is the magnitude of the difference between the input level in CK and the input level on /CK.3 3 3 VREFC . VREFC + 0.40 0.1) 12 . /DBI inputs with VREFD AC input logic high voltage for DQ.4. and is nominally 70% of VDDQ.EDW1032BBBG Table 9: AC Operating Conditions POD15 Parameter Symbol min. The slew rate is measured between VREFC crossing and VIXCK(AC). /CK single ended slew rate WCK. VREFD2 or the internal VREFD. /DBI inputs with VREFD2 Notes: 1. 11.3 — — VREFC + 0. The slew rate is measured between VREFD crossing and VIXWCK(AC).7 3. /CK Clock input crossing point voltage: WCK. this provides a minimum of 0.135 — VREFD2 + 0. If POD135. 5.0. VREFD is either VREFD.12 VREFD + 0. /DBI inputs with VREFD AC input logic low voltage for DQ.0. /WCK single ended inputs CK.0. /WCK Notes: 1. The WCK and /WCK input reference level (for timing referenced to WCK and /WCK) is the point at which WCK and /WCK cross.20 — VREFD + 0.09 Unit Note V V V V V V V/ns 10 V/ns 11 V V 3. Table 10: Clock Input Operating Conditions POD15 Parameter Clock input mid-point voltage: CK. 7.36 — AC input logic high voltage for address and VIHA(AC) command inputs AC input logic low voltage for address and command inputs AC input logic high voltage for DQ.09 max. 2. Symbol VMP(DC) VIDCK(DC) VIDCK(AC) VIDWCK(DC) VIDWCK(AC) VIN CKslew WCKSlew VIXCK(AC) VIXWCK(AC) min. VREFC + 0.7 3.8 3. /WCK single ended slew rate Clock input crossing point voltage: CK.1 0.7 6.0.30 -0. For optimum performance it is recommended that signal swings are larger than shown in the table. — VREFC .22 0.108 VREFD + 0. 9. This provides a minimum of 0. 4.1 0. DRAM timings relative to CK cannot be guaranteed if these limits are exceeded. /CK Clock input differential voltage: WCK.9V to a maximum of 1.0.10 POD135 min. /DBI inputs with VREFD2 AC input logic low voltage for DQ.9 2.40 min.18 0.2V.3 2. — — — — — — max. 1. 6.

8 INDEX MARK ECA-TS2-0327-02 Data Sheet E1771E11 (Ver.1 ± 0.0 10.1) 13 .05 170-B0.15 M S A B B 0.4 0.35 ± 0.1 INDEX MARK 0.1 0.0 ± 0.05 B0.1 S 0. 1.45 ± 0.8 2. Package Drawing 170-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Unit: mm 12.12 S A 0.2 S A 14.EDW1032BBBG 3.0 ± 0.2 S 1.8 12.2 S B 0.

MOS devices must be stored and transported in an anti-static container. Each unused pin should be connected to VDD or GND with a resistor. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Production process of MOS does not define the initial operation status of the device. The unused pins must be handled in accordance with the related specifications. hence causing malfunction. It is recommended to avoid using insulators that easily build static electricity. MOS devices must not be touched with bare hands. MOS devices are not initialized until the reset signal is received. The operator should be grounded using wrist strap.1) 14 . Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. it is possible that an internal input level may be generated due to noise. etc. static shielding bag or conductive material. humidifier should be used. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Steps must be taken to stop generation of static electricity as much as possible. 1. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. CME0107 Data Sheet E1771E11 (Ver. and quickly dissipate it.EDW1032BBBG NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. CMOS devices behave differently than Bipolar or NMOS devices. I/O settings or contents of registers.. When it is dry. If no connection is provided to the input pins. Environmental control must be adequate. power-on does not guarantee output pin levels. the MOS devices with reset function have not yet been initialized. Reset operation must be executed immediately after power-on for MOS devices having reset function. Hence. All test and measurement tools including work bench and floor should be grounded. when once it has occurred. Immediately after the power source is turned ON. if it is considered to have a possibility of being an output pin.

this product is not intended for use in the product in aerospace. or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. 4) Usage in environments with static electricity.S. or third parties by or arising from the use of the products or information listed in this document. The incorporation of these circuits. products does not cause bodily injury. including sea air. 5) Usage in places where dew forms. Inc. medical equipment for life support. you must follow the necessary procedures in accordance with such laws or regulations. Inc. including the maximum ratings. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Also. Elpida Memory. if you export products/technology controlled by U. combustion control. If these products/technology are sold. Inc. Inc. safety equipment. including water. software and information. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. SO 2 . 1. [Product applications] Be aware that this product is for use in typical electronic equipment for general-purpose applications. Inc. consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes. and NO x . CL 2 . 2) Usage in exposure to direct sunlight or the outdoors. Elpida Memory. oils. transportation. or a third party is granted license to use these products. is granted under any patents.EDW1032BBBG The information in this document is subject to change without notice. confirm that this is the latest version. so that the equipment incorporating Elpida Memory. Inc.1) 15 . 7) Usage near heating elements. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents. aeronautics. export control regulations. NH 3 . Example: 1) Usage in liquids. implied or otherwise. you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory. or flammable items. software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. 3) Usage involving exposure to significant amounts of corrosive gas. express. H 2 S. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits. Descriptions of circuits. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan. Accordingly. Inc. Elpida Memory. fire or other consequential damage due to the operation of the Elpida Memory. Before using this document. impact. copyrights or other intellectual property rights of Elpida Memory. Inc. Even within the guaranteed ranges and conditions. However. Inc. or others. or stress. M01E1007 Data Sheet E1771E11 (Ver.. leased. software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. Elpida Memory. installation conditions and other related characteristics. or in dusty places. operating supply voltage range. traffic. Inc. or transferred to a third party. heat radiation characteristics. makes every attempt to ensure that its products are of high quality and reliability. or strong electromagnetic waves or radiation. nuclear power. No license. or another country's export control laws or regulations. chemicals and organic solvents. 6) Usage in environments with mechanical vibration. product. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory. Customers are instructed to contact Elpida Memory's sales office before using this product for such applications. igniters. copyrights. and circuit layout licenses) of Elpida Memory.

1 Date Description Part Number Correction Type D : Monolithc Device to Packaged Device Apr.EDW1032BBBG Revision History Ver. 2011 Initial version Sep.0 1. 1. 2011 Data Sheet E1771E11 (Ver.1) 16 . 1.

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