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ECE 438( Digital Integrated Circuits)
Cadence Tutorial 2
Schematic Entry & Digital Simulation ( Using Virtuoso Schematic and Analog Artist ( Spectre))
Department of Electrical & Computer Engineering
University of Waterloo, Ontario, CANADA
Developed by: Manisha Shah ( Lab Instructor) Assisted by : Paul Hayes, Rasoul Keshavarzi Acknowledgments I would like to thank Mr. Javid Jaffari for his input in doing cosmetic modifications for better look and providing some useful information in the Appendix of the tutorial. This document will help students to learn cadence tools. Please send any comments, corrections email@example.com or and suggestions for improvement to firstname.lastname@example.org . Your feedback will be greatly appreciated. _______________________________________________________________________________
This document is solely for educational purpose without any commercial advantage. It is mainly focused for students of University of Waterloo, Canada. Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, san Jose, CA 95134
The following Cadence CAD tools will be used in this tutorial:
Virtuoso Schematic for schematic capture. Analog Artist (Spectre) for simulation.
We will practice using CADENCE with a CMOS Inverter: creating (1) Schematic (2) Symbol (3) Symbol Test Bench. Computer Account Setup Please revisit Unix Tutorial before doing this new tutorial. YOU SHOULD HAVE YOUR ENVIRONMENT SET UP FOR CADENCE AND ADDITIONAL TOOLS Running the Cadence tools Log in to your unix account. Open the terminal window. Now you should be able to run the Cadence tools. Never run Cadence from your root directory, it creates many extra files that will clutter your root. Instead please create a directory (e.g. cadence). mkdir cadence cd cadence Now start Cadence by typing
startCds –t cmosp18
The command will start Cadence and after a while you should get a window with the “icfb”, also called Command Interpreter Window (CIW) as below: Fig 1.
3 CADENCE MAIN WINDOW ( Note: “icfb” in the Title bar)
Fig 1 Cadence icfb ( CIW) window “You will also get a "Cadence Update" window which you can read and then close or minimize. With in “icfb(CIW)”you can launch other applications and you can also manage your files and libraries. NEVER use Unix commands (cp, mv) for moving Cadence design files as you may run into trouble later. For more information on the various Cadence tools I encourage you to read the corresponding user manuals. You can get to the manuals by pressing Help -> Cadence Documentation on any Cadence window (e.g. CIW(icfb)) or in the “Library Manager(F6)” You can also open the on-line manuals by typing following at the prompt in your terminal window. cdsdoc& Spend some time browsing the manuals to understand what is available (a lot!). During the semester you will have to look for information in the on-line manuals to complement the (limited) info given by these tutorials.”
We are going to create a new library. Howver, there are two different ways to work with. In this tutorial we will work mainly from “icfb(CIW)” window. But it will be a good idea to read the following paragraph and the “Note” started on the page 4 before you proceed. Now we need to create a new library (to contain your circuits) so from the icfb ( Fig 1) Command Interpreter Window (CIW) go to File -> New -> Library from the File menu. You will see a “New Libarary” window (Fig 2). Fill in the name of the new library (e.g. CMOSInverter) in the dialog window (this will create the library in the directory where you started icfb, you could also choose to set a path if you wanted another directory). Click on “Attach to existing tech library” and click OK.
1 Reference A
Fig 2 New Library Window You will get another window called “ Attach Design Library to Technology File” ( Fig 3) . Select “cmosp18” as Technology Library and click OK
Fig 3 Attach Design Library Note : (Starts here) Note ends on page 6. The above steps can be also performed using the Library Manager. After you start Cadence and get the “icfb CIW” window, go to Tools->Library Manager or press F6 on keyboard. It will open the Library Manager window (Fig 4) as shown below. You can create the new library (CMOSInverter) from the Library Manager following the same steps as explained above. Now the “CMOSInverter” library should appear in the Library Manager window. It is easier to work with Library Manager. However, for this document we will work through icfb- CIW window.
.5 Fig 4 Library Manager window (Press F6 to get Library Manager) It might be a good idea to put A1. . So.A2. when you open the Library Manager.in front of your library name. Otherwise you have to search thro’ all the libraries to locate your library as your created library is mixed with cadence system libraries.. E.g “A1_CMOSInverter”. This will place your libraries at the top in the “Library Manager” window under “Library” column (See Fig 5). A3. it will be easy for you to search (browse) your library next time.
Let's start our first schematic now! SCHEMATIC CAPTURE In the icfb CIW window go to File -> New -> Cell View.6 Fig 5 Library Manager (Library name “A1_CMOSInverter” at top) Note (Ends here). Fill in the information in the dialogue window as below and then press OK. Go back to page 3. Library Name : Cell Name : View Name : Tool : CMOSInverter myinverter (you can choose other name if you want) Schematic Composer-schematic . You will get a “Create New file” window (Fig 6).
If you pass the mouse pointer on top of the buttons you get short pop-up help messages. saving. 1 Fig 7 1 Reference A Virtuoso Schematic Editing window ( Composer) . drawing wires.7 Fig 6 Create New File window Wait for a while. You also have access to these commands (and others) from the menu. On the left side you have various shortcuts to common used commands such as: placing component instances (looks like an IC). Spend some time analyzing the window. zooming in and out.” You should notice that the top bar of the window will display the name of the library (CMOSInverter). It is not possible here to describe all the functionality of Virtuoso Schematic so you are strongly encouraged to read the on-line user manuals in cdsdoc. placing ports. copying. cellview (myinverter) and schematic at the end. You should get the “Virtuoso Schematic Editing” window as shown below (Fig 7). “The schematic window will appear. etc. stretching.
Select as follows in the Library Browser window. refered to as a Bindkey. “Note: The process of editing a design is called schematic capture. or go to Add -> Instance). We will pace the NMOS and PMOS transistors.8 You can zoom in or stretch the window to see the full view of the window and all icons of the various commands on the left side. Follow the steps now. or click on one of the icons on the left of the design entry form. We will select PMOS transistor and will place it on the Virtuoso Schematic window. Fig 8 Add Instance Window Now click on the Browse. Placing Instances Click on the “Instance” button (icon) on the left side (which looks somewhat like an IC. this will pop-up an “Add Instance” window (Fig 8).” 2 Let's start our first schematic to create the CMOS Inverter. or use a shortcut letter.on the schematic. Another window called “Library Browser – Add Instance” (Fig 9) will pop up. Library =>cmosp18 Cell => pfet View => symbol 2 Reference B . You can use several methods in the Cadence environment tools to achieve the same effect. We could select from the pull-down menus. Expand the Virtuoso Schematic Editing window if necessary.
. Now go back to “Add Instance” window.9 Fig 9 Library Browser Window ( Looks like Library Manager Window) There is no need to close the Library Browser window at present. Fig 8 changes to Fig 10. You will see that “Add Instance” has expanded to display various other parameters (see Fig 10 below). Javid Jaffari. This information is provided by Mr. Names => M1 Width =>800 nm Length => 180 nm Note : Please refer to Appendix 1 ( at the end of the document) for some useful information on parameters. Change following properties of pfet in “Add instance” as given here.
Width => 360 nm. You need to select “nfet” under the cell for NMOS. flip this outline until you get what you want.” press “Esc” key on the keyboard to release any command. rotate. Now click on the “Add Instance” window. Change following properties of the nfet in the “Add instance” window.10 Fig 10 Add Instance Window with variables “If you move the mouse now on top of the Virtuoso Schematic editing window you will see an "outline" (or ghost) of the transistor. Length => 180 nm _______________________________________________________________________________ 1 Reference A . Go back to the “Library Browser-Add Instance” by left clicking on this window. Select as follows: Library =>cmosp18 Cell => nfet View => symbol Notice carefully. then by clicking the left-mouse button you can place it in the schematic. Names => M2. 1 Also you can Now we will place the NMOS transistor. You can move.
please explore the different editing functions. I/O pins and power supply. if you move the mouse on top of the Virtuoso Schematic editing window you will see an "outline" of the transistor nfet. So far so good!!!! To change the parameters of the instance. Now we also need to add wires. . First let’s add wires (narrow) to connect transistor’s terminals and form a schematic of the CMOS Inverter.Then hit “Esc” on the keyboard. select the instance (by clicking on it with the mouse) and then use “properties” icon or press “q”. Very important key to remember!! Fig 11 NMOS and PMOS on schematic Ok. Again you can move. you will only learn by making mistakes and then correcting them. rotate. You will need to hit “Esc” every now and then. See the picture (Fig 11). you have NMOS and PMOS on your schematic. then click the left-mouse button and place the nfet in the schematic below the pfet.11 Now. You can also move. delete parts. You will notice that the “Add Instance” and “Library Browser” windows disappeared. flip this outline until you get what you want.
You will see an “add Wire” window. Connect all the wires likewise.12 Connecting Wires To connect the wires. To delete the wire. Now activate the Virtuoso Schematic Editing window by clicking on its title bar. click on the icon “Wire (narrow)” on the left side. You can choose the color whatever you want to. move the mouse over (you will see wire attached) and then double click at other end to connect wire between those points. You can delete unwanted wires if connected accidentally. You can click on the node (diamondshape) with left mouse button. Move the mouse over or click on the s key on your keyboard. select that wire by left mouse click and then hit Delete on the keyboard. See Fig 12 below. Fig 12 CMOS with no pins . When you are done hit “Esc” on the keyboard. This snaps the wires to connect between the little diamond-shapes displaying by the nodes.
Note that Direction in the form reads input. Then hit Esc. Place Vin at the input of the CMOS Inverter with left mouse click as shown (Fig 14). Fig 13 Add Pin Window Now. as shown below (Fig 13). click once on the schematic window. . The “Add Pin” form appears. click on the “Pin” icon at the lower left corner.13 Let’s connect the I/O pins now. Under the Pin Name type Vin. Adding Pins To add the input and output pins.
. Place Vout at the output of the CMOS inverter (Fig 15). Type Vout under Pin Name and select the direction output.14 Fig 14 CMOS with Input Pin Follow the same steps to connect the output pin. Hit Esc when you are done.
CMOS with Input. Then hit “Esc”. Click on the “Browse”. You will see an outline of the vss symbol. (You can also push “i” key on the keyboard to add instance). Move your mouse over the schematic window. Under Library select “Analoglib”. . Connect it to the wire at the source of the M2 (nfet) transistor as shown here ( Fig 16). The “Add Instance” form appears. under Cell select vss ( you might need to scroll down for vss) and make sure you have a symbol under view. Output Pins Placing Vdd and Vss Click on “Instance” icon. You will get the “library Browser” window. let’s connect Vdd and Vss.15 Fig 15 Now.
16 Fig 16 “vss” connected at the bottom Follow the same steps to connect the vdd. In the Add Instance form click “Browse”. select Library ->Analoglib. In the “library Browser” window. Then hit Esc. Click on “Add instance” icon. The final schematic should look somewhat like this (Fig 17). . Success ? It's a good idea to save your design from time to time in case the system crashes. Cell -> vdd and symbol -> view. Move your mouse over the schematic window and connect vdd to the wire at the source of the M1 (pfet) transistor.
vss Everything worked fine so far!!!! Congratulation!!! Check and Save your design Now you need to Check and Save your design (either click the top left button or go to Design -> Check and Save). “CMOS Inverter myinverter schematic” saved.17 Fig 17 CMOS with vdd. . if there are any you have to go back and fix them! The icfb window will give the message as shown below. “Schematic” check completed with no errors. Make sure you look at the “icfb” CIW window and there are no errors or warnings.
select Design => Create cellview=>From cellview…. This sequence creates symbols automatically. Change “Tool/data Type” to Symbol. then click OK. based on their primary input and output pins. 1 Reference A .” 1 Creating the Symbol Cellview (Of the CMOS schematic Inverter) “Now we will create a symbol (black box) to represent our circuit. We will create a test bench circuit for our CMOS Inverter. First we will model our circuit with a “Black Box” symbol. Just click OK. Later on we will connect the input source and the output load to these input and output pins respectively. The symbol Cellview will be created based on the already –available schematic Cellview. The Cellview form appears as shown below (Fig 18).” 1 In the Virtuoso Schematic window ( Fig 17). Notice the pins Vin and Vout in the boxes of “left Pins” and “right Pins”. The symbol ( black box) will be generated with Vin as left pin and Vout as right pin. Fig 18 Cellview From Cellview You will see another window “Symbol Generation Options” (Fig 19).18 NEW SECTION “Note: It is a standard practice to test each circuit with a “Test Bench” to make sure each circuit works. This is called creating a Cellview from another Cellview.
Fig 20 Virtuoso Symbol Editing Window . Please notice the difference between “Virtouso Schematic Editing” and “Virtouso Symbol Editing” windows.19 Fig 19 Symbol Generation Window It will open another window “Virtouso Symbol Editing” window (Fig 20).
first select Part name. It will open a dialoug window “Create New File” ( Fig 22) Select the library “CMOS Inverter”. Change the Part name to “cmos_inverter” To change the label for Instance name select “instance name” rectangle and using property icon change the “instance name to ci_1. Fig 21 New Section myinverter symbol Creating a Test Bench Now. Let’s name the cell name as “myinverter_testbench” . Then Edit=>properties=>objects. we will create a “Test Bench” circuit. See Fig 21. Fig 22 Symbol( Test Bench) Cell Name . Open a new file from the CIW window. Go back to “icfb” (CIW) window by clicking on the window. File => New=> cellview.20 To change labels. below.
It will open “Virtouso Schematic Editing: CMOS_Inverter myinverter_symbol schematic” window ( Fig 23).21 Click OK. So. select Library => CMOS Inverter Cell => myinverter View => symbol Move your mouse over above window and place the symbol on the window. Hit Esc. Fig 23 • Symbol Schematic window Add your inverter symbol to this window using following steps Go to “Add => Instance”. Click on “Browse”. In the “Library Browser” window. It will open “Add Instance” window. See Fig 24 Fig 24 Symbol Schematic Window Test Bench with Inverter .
Push “i” on keyboard to select instance. Connecting input source and output load To connect input source to symbol cellview. In the “Add Instance” window ( Fig 8). click on “Browse”. In the “Library Browser” window ( Fig 9). Change Rise time to 5 ns. Fall time to 1ns. Pulse width to 10ns and Period to 20 ns ( Fig 25). Before we proceed connect two short wires to both red squares. select Library => cmosp18 Cell => vpulse View => symbol Now click on the “Add Instance” window and change following properties.22 Now we have to connect input pulse source and output load (capacitor) to the symbol. Fig 25 Add Instance of Input Test Pulse .
Press “ESC” on keyboard To connect load capacitor. Using the instance. See Fig 26. However. Guess why ? We have to connect “ground (gnd)” to input pulse source and output load capacitor. In the “Add Instance” window. you will find warnings. Now. connect “gnd” from “analoglib” library to vpulse and capacitor.23 Now. select Library => cmosp18 Cell => Capacitor View => symbol Now click on the “Add Instance” window and Change Name to C0 and Capacitance to 50 f F. click on “Browse”. move your mouse over to open “Virtouso Schematic Editing: CMOS_Inverter myinverter_symbol schematic” window. Whenever you do check and save. In the “Library Browser” window. don’t forget to “icfb” CIW window for messages. Fig 26 CMOS Inverter Symbol – Test Bench Circuit You can perform check and save here. . Attach vpulse to the wire at Vin on the symbol. Press “Esc” on keyboard. Hit “Esc” when done. move your mouse over to open “Virtouso Schematic Editing: CMOS_Inverter myinverter_symbol schematic” window. Attach Capacitor to the wire at Vout on the symbol. Push “i” on keyboard to select instance.
(You can also push “i” key on the keyboard to add instance). below). This is much of the same process as you did for vdd and vss. You will get the “library Browser” window (Fig 28. We need two vdc. Assuming there are no errors we move further! Adding DC supply voltages Now.8 V and one for gnd (vdc=0) to connect to vss. Follow the instructions to add DC supplies. We need DC voltage sources (vdc). one for vdd which is 1. The “Add Instance” form appears (Fig 8). let me say something before you proceed. Under Library select “Analoglib”. under Cell select vdc ( you might need to scroll down ) and under view select symbol. Click on “Instance” icon.24 Fig 27 Final Test Bench Circuit for CMOS Inverter Symbol without power supply Now do check and save your design. . The DC voltage sources that we are going to add are in the analoglib library with the name vdc. Click on the “Browse”.
Enter 1.8 for the “DC Voltage”. Enter “V1” for the “Names”.25 Fig 28 “analoglib” Library for vdc Now click on the “Add Instance” window. . See below (Fig 29). You can notice that “add Instance” window has expanded.
Select Library ->analoglib. Then click on the selected object (vdd) and then place it to V1 at top and click again. Select vss from library “analoglib” and connect it to V2 at bottom (you can also copy paste vss on the schematic) Now we will connect ground ( from analoglib – Fig 28) to vss. You can also do copy paste vdd on the schematic. Then go to Edit->copy or click on copy icon on left.26 Fig 29 Add Instance window Then go back to schematic window and place vdc somewhere on the schematic window close to your CMOS Inverter. You can also place vdc source one after the other (no need to click on Instance in-between). respectively by filling the DC voltage property to the appropriate value. Cell -> gnd and view-> symbol in the “Library Browser” window. Select vdd from library “analoglib” and connect it to V1 at top. Then go back to schematic window and connect “gnd” to V2 as shown below. Click on browse in “Add Instance” window. select vdd. At the end hit Esc. Place another vdc (V2) of 0V under the V1. Click on “instance”. Then hit “Esc”. The vdd is now connected to V1 at top. . To copy. Connect these two sources (V1 and V2) with wire (Use “wire (narrow)” icon). Hit “Esc”.
then a pop-up window will appear (Fig 30). where you can change what you want:” 1 Fig 30 1 Reference A Edit Object Properties Window . if you filled in the wrong value for the DC voltage for vdc you can always change that later by first selecting the instance (click on it in the schematic) and then go to Edit -> Properties -> Objects (or click on the properties icon).27 “In case you made a mistake you can always go to Edit -> Undo. or you can correct your mistake by some form of edit. For example.
the pins vdd and vss needs to be added in the symbol cellview of “myinverter” cell and also in the testbench circuit as shown here after doing the changes in the main schematic. You can now do that easily by yourself. Ok. To match with the layout design ( the next stage). final testbench schematic is ready. the vdd and vss in the schematic design( Fig 17) were replaced with pins vdd and vss instead ( Delete the vdd and vss of analoglib in the schematic and connect the vdd and vss pins . Test your skill !!!! CAUSTION : Don’t forget to do “Check and Save” every time you change your design for any schematic . However. So. Fig 31 Final CMOS schematic Connect the wires as shown in figure above.Refer to “Adding the Pins” section to connect pins). you can notice some changes in the symbol here when comparing with the testbench circuit of Fig 27 . Fix the errors if you see any. .28 The final testbench circuit should look something like this ( Fig 31). Perform “Check and Save” on your testbench. Assuming no errors we are ready for the simulation.
and choose Spectre in the pop-up window( Fig 33). You will get “Virtuoso Analog Design Environment (1)” (also known as “Virtuoso Analog Artist”) window (Fig 32). Fig 32 Analog Design Enviornment First we need to choose the simulator. In the “Virtuoso Analog Design Environment (1)” window. go to Setup -> Simulator/Directory/Host.29 Let’s now perform the simulation on the testbench circuit to see the final results !!! SIMULATION In the Virtuoso Schematic window (the above window one which has symbol cellview “myinverter_symbol”) go to Tools -> Analog Environment. then click OK: (Spectre is similar to spice) . we will choose Spectre.
( Fig 35).30 Fig 33 Simulator ( Spectre) In the Virtuoso Analog Design Environment. .. go to “Setup -> Model Libraries……… ”.. Enter the stop time for transient analysis. From “Virtouso Analog Artist”( Fig 32) go to Analyses -> Choose. Click OK. Let’s type 500n for stop time. In this case we will choose a transient analysis. Click on “Add” button. Fig 34 Model Library Setup Now you need to choose the type of simulation. Then click OK. Enter following path in the box under the “Model Library file” /home/cadence/kits/cmosp18/models/spectre/icfspectre.init See Fig 34.
The currents can be selected by clicking on the terminals(red squares). . Ok. We will click on input and output nets(wires) to select input and output voltages. That will bring your testbench cellview window in front.31 Fig 35 Choosing Analysis Now in the “Virtouso Analog Artist” (Fig 32)go to “Outputs -> to be plotted -> select on schematic”. If you are pressing right on the pins a circle should appear around each chosen pin. Select node voltages by clicking on the net. Look at your “Analog Artist” window( Fig 36). Did you notice something written under the “Outputs” ? net3 and net6 represents the input and output node voltages respectively.
You can zoom in particular portion of your waveforms ( Fig 38) and find out the rise time. input and output square waves! ( Fig 37). fall time. You will need to wait for a while. delay of the output waveforms. This can be tricky! CAUTION Each time you change the schematic you have to do Check and Save!. You should finally get the desired simulation results. Remember that we have applied a vpulse source with particular values of rise time. delay. period to the CMOS Inverter circuit and we will get the output with certain rise time. fall time. It will start simulation.32 Fig 36 net 3 and net 6 “Outputs” Now we can finally simulate! Click on the “Netlist and Run Simulation” button (looks like a green light) on the right or go to “Simulation -> Netlist and Run”. Later on you can perform optimizations to your design ( circuit). You should check your “icfb” window for messages while it is running the simulation. fall time and delay. In case you have errors you will need to go back and correct them. .
. Here is the “zoomed in” waveforms.33 Fig 37 Simulation Results You can zoom in your waveforms.
34 Fig 38 Zoomed in Waveforms of Simulation Results “It's a good idea to save the state of your simulation before you exit the simulation window. Type state1 as state and click Ok ( Fig 39). You can do that by going to Session -> Save State (Fig 36).” 1 1 Reference A . This will be helpful if you want to redo any of the simulations without having to re-enter everything from scratch.
3. so you can print a lot of ways. uncheck Plot With header (if checked) click on plot options . modify the image and then you can save as . go to Design -> Plot -> Submit. You can paste that image in the “Paint” program. in this way you can have access to the file in the future without having to start Cadence: 1. myinverter_schematic.bmp or other type of image. To save. You can save the Waveform. on the waveform viewer menu go to File->Save as Image. click OK on the second window. Save as whatever option you prefer. 4. 1 Reference A .bmp and then print it. enter a file path. Browse the folder where you want to save the image. click OK on the first window” 1 Later on you can open your . On this menu there are a lot of options. If you are working thro’ windows with remote login. e.ps.ps file) under the current directory you are working ( one from where you run your cadence at the consol) 6. What I usually do is to write the schematic to a postscript file. 5.. Later on you can open and print the image using appropriate computer program.g.another form pops up check Center Plot click on Fit To Page check Send Plot Only to File. you can capture the screen image using “Print Screen” button on the keyboard. 2.ps file in the Ghostview program from the directory where it is saved and you can print it.35 Fig 39 Saving State PRINTING AND PLOTTING “To print the schematic in Virtuoso Schematic from the menu bar along the top. uncheck Mail Log To (if checked) 7. Click on help for more details. then print.ps OR myinverter_symbol. You have different options to save the waveform as . This will save the file (.
14. 11. this is not an appropriate way. OK.36 Congratulations. For example suppose that we want to see the effect of transistor sizing on the propagation delay of the inverter. and click OK. 4.Save the schematic. 5. you can enter “2*Wn” or “any other number*Wn” in the width field.Select “Wn”. This enables analysis the effects of sweeping a parameter on the circuit performance. 9. This feature enables assigning some variables to required parameter. however.ca) Parameter Analysis: Suppose that one wants to have the waveforms for various transistor sizing or any other parameters.Do the same for PMOS transistor. To perform this task these steps should be followed: 1. 6. save the schematic. 2.You may here set any desired value to these variables by double clicking on them.Do any setting needs to be done same as selecting “tran” type of analysis and simulator engine “Spectre” and model libraries.Variables Copy from Cellview 8. 10. respectively.Select the NMOS transistor and push ‘q’ to open its property window. Cadence has provided a parameter analysis feature. and “Total Steps” with desired values. 3.Open the Analog Design Environment where you use it for running simulations. USA Reference B : Schematic Entry & Digital Simulation ( Cadence Tutorial) : Royal Military College of Canada APPENDIX 1 By: Javid Jaffari (jjaffari@vlsi.The list of variables will become visible in the bottom-left side of the window. However. REFERENCES Reference A : Cadence Tutorial 1 : University of Virginia. and run simulation. As shown in Fig 2. A new window will be opened. to keep the ratio between width of the pmos and nmos constant. 5. 2000n. and run the simulation.In the Width field enter “Wn” instead of actual value as shown in fig 1.uwaterloo. to do parameter analysis you don’t need to enter any values here. 7.Analysis Start . However.Tools Parametric Analysis….Fill the “From”. this is the end of Tutorial1.Setup Peak Name For Variable Sweep1… 12. Let choose 500n. “To”. 13. One way is to change the corresponding parameter for each simulation.
g. Figure 1 .You will find the simulation which running for a range of “Wn” from 500 nm to 2000nm in 5 steps. vdd. Results for the output of the inverter are given in Fig.37 15. You may do this kind of parameter analysis for any other parameters (e.3. output load capacitance. …).
38 Figure 2 Figure 3 .
Then create a new symbol. Methodologies: Approach 1) Parametric Analysis: 1. When you want to have access to some specific parameters from a symbol abstraction level. 2. For example suppose that you want to have different inverters with different transistor widths. tpLH)/2 directly. Therefore.39 Passing Parameters through the Hierarchy This is another feature of Cadence. Following. Create a chain shape test circuit schematic for the inverter corresponding to the given assumptions as shown below: (Assign names to the input and output wires to make them easily traceable) . Assumptions: Output capacitive load = 10 fF VDD=1. Problem: Find the (WP/WN) ratio of a CMOS inverter which minimizes the propagation delay of the gate. The solution is to write pPar(“Wp”) and pPar(“Wn”) in the field of width of property windows of PMOS and NMOS devices. This new symbol has the ability to get two values for Wp and Wn and assign to the width of the transistors. we solve a problem by using calculator and defining expressions. but obviously with the same schematics. Discussion: It is known that the minimum delay CMOS does not necessarily correspond to symmetric or equal tpHL. you may use this feature. Assign “ratiox600 nm” to the PMOS width. tpLH design. _______________________________________________________________________________ APPENDIX 2 Using Calculator and Expressions for Parameter Analysis and Optimization Cadence provides some useful features to do optimization and parametric analysis on circuits. Create a CMOS Inverter. the objective will be minimizing the (tpHL. (Note that here “ratio will be the variable which we want to find in order to make delay minimum”) 3.8v WN=600 nm tr=tf=20 pS. The feature allows user to pass specific values to each instance’s parameter of a symbol separately.
13. Click “InSig” from “Results Browser”. 15. In the “Analog Design Environment” perform “model library” and “choose analyses” setting (transient). 20. Place the cursor in the Signal 1 textbox. Name (opt. 14. Click “OutSig” from “Results Browser”.40 4.9 which is (VDD/2). 16. In the “Setting Outputs”. 5. to remove the tick. In “Calculator” window. Click >>> . Below picture: 7. Change the Edge Type 2 to “falling” 21. 17. 9.9 which is (VDD/2). (Note that you had to ran the simulation one time before to see the signals in the browser) 10. Outputs->Setup… 6. 11. 8. In “Calculator” window. The result browser will be opened. Place the cursor in the Signal 2 textbox. In the “Analog Design Environment”. there is a list of functions click “delay”. In “Calculator” window.)=tpHL. Click >>> 19. The Calculator window will be opened. Change the Thershold Value 2 to 0. Click Calculator “Open”. Change the Edge Type 1 to “rising” 18. In “Result Browser” window. open “tran-tran”. Change the Thershold Value 1 to 0. Options->Set PRN. Tools->Browser. The two windows will be like below: 12.
A new window will be opened. Change Step Control to Logarithmic. 32. and “/” buttons when are needed. The output will be the plot of three parameters for different PMOS/NMOS width ratios. To do this. 10. “+”. we must follow the same way we did for tpHL and tpLH and use “(”. Let choose 0. 25. 27. Repeat previous steps this time for tpLH. Like below: 26.41 22. 4. In the “Setting Outputs” window. OK. and “Total Steps” with desired values. It can be seen that the minimum delay ratio does not necessarily correspond to the symmetrical point.5. Analysis -> Star 33. An expression for tpHL has been added. Tools -> Parametric Analysis…. Setup->Peak Name For Variable->Sweep1… 30. You will see that the three expressions are listed. This is the output plot. . In the “Parametric Analysis”. Fill the “From”. 31. Click “Get Expression”. 24. then “Add”. “)”. “Delay” which is equal to (tpLH+tpHL)/2. but assign “falling” to Edge Type 1 and “rising” to Edge Type 2. Now you have two expressions in the “Setting Outputs” window. Click Apply 23. Go back to “Analog design Environment” window. respectively. Select “ratio”. As shown in below. “To”. Following is the picture of the “Setting Outputs” window after adding three expressions. (You need to redo steps to define delays from 12 to 22). Now create an expression namely. 29. 28.
Variables->Add/Edit…. Tools -> Optimization….5. However the ratio which tpLH=tpHL is 2. Select “ratio”. 28. Set the acceptable to 23p. In the “Analog Circuit Optimizer” window. Assign initial value 0. Delete “tpHL” and “tpLH” and just keep “Delay” 31. Goals->Retrieve Outputs…. 33. 29. And the corresponding delay will be 23. 30. 35. Double click on “Delay” 32. minimum 0. Let say 20p. Set a target for delay. and maximum 5. A new window will be opened. Approach 2) Optimization: Follow steps (1)-(27) of the first approach. 34.638 for this case.765. Then the three defined expression will be listed. Choose direction as minimize.74 pSec. Hit OK.5.42 The ratio which gives the minimum delay is 1. The window should become same as below: . 36. In the “Analog Circuit Optimizer” window.
Mr. (You should be aware that due to very nonlinear nature of the simulations. Optimizer->Run The output will be a graph of ratio and delay for every iteration. therefore you may need to change the initial value of skip such local optimums). the optimization may converge to some local minima. Here is the sample output graph for our problem. Javid Jaffari . You may stop the optimizer when it doesn’t give better result. Go Back -Appendix 1 & 2 by .43 37.
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