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Mn hc Thit b ngoi vi v k thut ghp ni (Peripherals & Interfacing Technique)

Gio vin: Bi Quc Anh, B mn K thut My tnh Introduction: The purpose of this course is to provide student with technical knowledge of each major subsystem of Interface, including processors, memories, IO bus,... especially Nonstandard zed Input Output via ports and applies to industry architectures across a wide range of hardware vendors This document could contain technical inaccuracies or typographical errors. Author believes the statements contained herein are accurate as of the date of editing of this doc. However, the Author makes no warranty of any kind with respect to the accuracy of the contents hereof.

1. Hardware

Central Sys.

Adaptor

Wide world
Computerized Dev: KB, Printer, Scanner, Mouse

Ports CPU, Mem, Bus, Controlle rs, ...

Controllers HDC, CRTC

Specific Devices: HDD, CRT, ...

Ti liu tham kho: Publications: - Microprocessor Interfacing techniques, R. Zaks & A. Lease, Sybex - Micro Processor and Interfacing, D. Hall, McGraw Hill; - IBM PC AT Technical Reference (Buses, Ports), IBM; - Introduction to the PC Architecture Course, IBM PC Institute, 1997 - Interfacing to IBM PC L. C. Eggebrecht, IBM Corp. - Parallel Port Complete, J.Axelson, LakeViewResearch. - Mastering Serial Communication, P.W. Gofton, Sybex. - PC Intern (System Programming), M. Tischer, Abacus. - Programming & Interfacing the 8051 MC, S. Yeralan, Addison-Wesley - ... Software: - TechHelp Ver. 4.0 / 6.0 - MSDN, Online Help. - Design tools: OrCAD, Protel, Cadence... - Programming Languages (C, Pascal, MASM, C++, VB, Delphi, VC++...) - .... Websites, .pdf files: - IBM, Microsoft, Intel, Motorola ... - ATMEL: atmel.com/product/microcontrollers 89Cxx (51/52/2051/8252, AVR - RISC, MSC51)... - National Semiconductor: ns.com/products: ADC 0809, DAC0800/1210, S&H LM198)... - INTERSIL: intersil.com/products/ICL7109, 7135... - Analog Devices Inc.: adi.com/products/adc, S&H...: AD574, AD1674 - USB: usb.org (pdf files for version 1.x & 2.x) - Cypress EZ USB, Developing Kit... - ...

ADC, DAC

Industry Objects: Scale, Furnace, GenSet, Tanks,...

2. Software: Device Drivers: SLLs, DLLs, DRVs, VxDs, DCUs,...

Interfacing?
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Chng.1 Kin trc h VXL MT


Kin trc thit b h kinh in, Kin trc h my tnh Hi Performance Hot ng ca h thng.

1.1. Kin trc H VXL, My tnh kinh in Embedded systems 1.1.1. S : 3 phn: - CS, - Ngoi vi & - Interface

1.1.1. a. Central Sub System CS: + CPU: Central Processing Unit: Khi nim: L b iu khin trung tm, thc hin cng vic c giao t trong b nh chng trnh bng cch thc hin cc php x l ln cc bin nh phn v iu khin thit b ngoi vi. Cng vic bao gm: Tm lnh, gii m lnh, [tm ton hng, x l v ct kt qu], In/Out vi cc port kiu Interrupt v DMA iu khin thit b ngoi vi. c trng Specifications: Kch thc ton hng (bit): 4, 8, 12, 16, 32, 64... Tc x l: Mips, clock multiplier, Kin trc: RISC vs CISC, DSP, Micro Controller... Pinning/Signalling (Data/Address - Mux, Control bus, IRQ, HRQ, RD/WR...), Register set, Instruction set Addressing Modes, Power: Slow/ sleep/ power down modes ... Memories (Semiconductor): K/n & ROM: Khi nim: Lu thng tin (ch/tr v s liu) dng nh phn, Dung lng ln (upto 100s Mega bit), tc truy nhp nhanh (downto ns access time). Physically: tnh cht vt l nh th no? ROMs: gm Mask ROM, PROM, EPROM, EAROM, OTROM, NonVolatile mem, ... L b nh ch c, vn lu thng tin khi mt in, Package : byte Access time:100..120ns Ghi/np ni dung: T/b chuyn dng (ROM Burner/Programmator) Memories (Semiconductor): SRAM RAMs: Lu thng tin tm thi, khng lu c khi mt in, c v ghi c, [Read/Write Mem].
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Static RAM: nhanh (80..3 ns), byte/nibble package, mt byte/chip nh (upto 64/256 KB/ chip), t, tiu th cng sut nhiu, CMOS RAM: chm v tiu th cc t, less W. Vd: MC 146818 RealTimeClockCMOS RAM Dng trong cc h nh, cache memory. Memories (Semiconductor): DRAM Dynamic RAM: DRAM: Tc /Access time (50-70ns), [10..20ns] Pre-fetched Mt bit/chip >> (1 Gbit/chip 1996, Korea), bit package => DRAM bank, Tiu th cng sut nh. Thng tin ch lu c 10ms => refreshing DRAM vi chu k @ 7,5ms => phc tp. Dng trong cc h c dung lng nh ln: my tnh, my ch... Memories (Semiconductor): FLASH & Others Flash memory: EAROM typed, c c, xo tng bank, ghi li c tng byte. Thng tin lu c 20 nm, dng nhiu hin nay v tng lai: BIOS, diskchip... Serial EAROM/FLASH: dng lu configuration, dng bus I2C (Philips). V d ng dng : th vi mch, TV, ... Dual [Quad] Ported RAM: Switching Sys., PGA RAM-DAC: VGA, VoiceChip PCMCIA .... Memories (Semiconductor): Logically: B nh cha thng tin g? Program memory: cha ch/tr ang c thc hin Data memory: cc bin ngu nhin, bin c cu trc, s liu c kiu truy nhp c bit FIFO, LIFO (Stack memory). + Controllers: [Optional], vi mch, nng hiu nng (performance) h thng, bao gm: B iu khin u tin ngt PIC Priority Interrupt Controller, Intel 8259A B iu khin truy nhp trc tip b nh DMAC Direct memory Access Controller, Intel 8237A. Timer: mch to cc khong thi gian, PIT- Programmable Interval Timer, Intel 8254. Mch qun tr nh: MMU- Memory Management Unit, sau ny, thng c built on chip vi CPU. Bus controller/Arbitor ... Bus System: K/n & Addr bus PCB (Printed Circuit Board)/ Cable (Twisted pairs, flat..), slot, connector... Ni hn 1 slave device, time sharing Thng tin: Address, data, control, status, Power Supply Chiu (dir), 3 state (Hi Z), Loading ADDRESS BUS: T cc BusMaster (CPU, DMAC, PCI host Controller) n SlaveDevices (Mem, Ports) chn/ ch tng IO/ Mem location trong tng chu k bus n Addr bit 2n Mem Locations & 2m IO Locations, m<n Bus System: Data bus Data bus: S bit (thng) ph hp vi kch thc ALU (8/16/32/64 bit)
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Chuyn Op-code (m lnh) trong chu k my M1, - CPU <= Program Memory, trong cc bus cycle M1 Vn chuyn data: - CPU <=> Data memory, - CPU <=> IO Ports v - Data Memory <=> IO Ports, DMA. Bus System: Control/Status bus: gm cc tn hiu: Control/ Response: CPU to Others (MEMR, MEMW, IOR, IOW, INTA, HLDA, BHE...), from CPU Status/Request to CPU: IRQ, HRQ, Ready, ... to CPU Bus System: Power Supply: +5V 5%, 10 n 20 Amp, cp cho cc Vi mch s, RedWire. (3.3V and less) Ground, Gnd, 0V, signal reference ground, chassis, BlackWire. +12V 10%, 1Amp, cp cho cc mch analog, motors, RS232, YellowWire. -12V 10%, 1Amp, (nh trn), BlueWire. - 5 V5%, 0.5 Amp, analog circuitries, WhiteWire. Power good: OrangeWire. Ngun thng minh: AXT 1.1.1.b. Thit b Ngoi vi: Data Input Devices: - Key board/ Key pad, Touch SCR: s phm, cng ngh phm, kiu d phm, output code, ghp ni CS - Mouse, track ball - Scanner, Camera, Camcoder: Colors, resolution, f, cng ngh CCD - Charge Couple Device, graphics file bmp - Digitizer, nhp graphics file vector - bn - Light Pen, Joy stick (Games) - Demodulator (MODEM): Kiu iu ch, tc bps, kiu nn - Microphone, - Barcode reader: my c m vch Laser/ LED, - Sensor, Transducers, Transmitters: Vt liu, thit b, nhy, tuyn tnh, di o... 1.1.1.b. T/b Ngoi vi: Data Output Devices: - Displays: Kiu hin th: Point/ 7Seg/ Text/ Graphics; Mono Chrome/Color (color numbers); Size, Resolution, Rate of Refreshing... - Cng ngh: - LED (Light Emitting Diodes): point, 7(16) Segment, Matrix character box (Bill Board), Outdoor LED Screen... - LCD (Liquid Crystal Display): single color, color, active, TFT (thin film transistor)... - Organic LED (Preliminary), - CRT (Cathode Ray Tube). - Printers: - Spec: Text-Graphics, Mono-Color, Resolution, ppm page per minute, Size, Line-PostScript, media... : - Pin Printer, - Jet Printer, - Laser Printer, - Thermal Transfer Printer, barcode Printer. - High Speed Text Printer, - ... 1.1.1.b. T/b Ngoi vi: Data Output Devices: Others - Plotter, jet - Modulator (MODEM) - Speaker - Actuator: Motor (dc/ac, Step), Relay, Valve,
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1.1.1.b. T/b Ngoi vi: Data Massive Storages: - Magnetic devices: FDD, HDD, RAID, Tape backup drive... - Optical devices: CD [Writer] Drives, Magnetic Optic disk drive... - Semiconductor devices: FlashChip, PCMCIA Card... 1.1.1.c. Interface: L do: khc nhau: - Tn hiu (dng, p), - Tc lm vic/tc trao i s liu, - Khng ng b... Nn cn c mch in t thch ng ho (Adapting) v ch/tr iu khin, gm: - Thit b (Hardware Circuitries), so called Adaptors: - Input/Output Ports: (Parallel/Serial): ghep ni vi Computerized devices (KB, Printer, Mouse, Scanner, Modem...) - Controllers: ghp ni vi nhng thit b chuyn dng FDC, HDC (IDE, EIDE), CRTC (EGA, VGA, SVGA...) - Converter: chuyn i tn hiu s thnh tng t v ngc li: ADC, DAC 1.1.1.c. Interface: Ch/tr iu khin Device Driver: - K/n: Hardware or Software? - lin kt System Programs and/or Application Programs vi IO hardware (SPIs v APIs). Cc hm ca thit b, BIOS, OS hoc theo ng dng: SLLs, DLLs, DRVs, ... 1.1.2. Kin trc my tnh hiu nng cao - hi performance architecture

1.1.2. Hi-Per. Architecture: 1.1.2.a. Local Buses: V d VESA VL-Bus 2.0 [late 1993], Memory [1985]. Also called system/host/processor bus. Ch lin kt CPU, MMU (Cache & DRAM) v PCI Host [Bridge], t, gn, unbuffered (direct connected to Processor); 33, 66, 100, 133, 200, 400, 800 MHz... clock. 32 bit A/D (16 bit support also), burst mode, max 132 MBps,

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reset ProgCounter = ResetAddr/vector

Addr

D0

D1
(data 4 byte)

D2

D3

D4
n

DMA?

Machine On Halt

DMA? y

H.1.3. V d burst mode 1.1.2.b. Hi Speed Bus: - Peripheral Component Interconnect PCI - 5/1993, Intel Ver. 2.0, Open Standard, - Local bus, mc trung gian gia Local v cc bus chun khc (ISA, MC, EISA) thng qua PIC Bridge/Controller. - C kim tra parity cho Addr v Data - Auto configuration of all PCI devices, share the same IRQ. Disabling IRQ => cm ton b PCI devices. - No DMA, device on PCI bus l bus master (Tt cho vic dng MultiTasking OS). - Burst mode: 32 bit @33MHz --> 96..132MBps, tu thuc s byte (t 32 byte n 4KB). Option 64bit @33MHz --> 264MBps - Most Platforms use:Intel, DEC Alpha, PowerPC, Spark - Modern OS: Block Typed Devices: tn sut vn chuyn cao, nhanh, data block 1.1.2.c. Expansion Bus: So called: standard buses, expansion bus, slots, IO bus, IO system, channel bus): ISA, EISA, MC... - MC bus: 32 bit, 10MHz, 20..40MBps, 15 BusMaster, Auto config, 1987, IBM - EISA bus: 32 bit, 8MHz, 33MBps, 4 BMs, AutoConfig (EISA card only), 1989, Compaq - ISA (Industry Standard Architecture), AT bus: - Spec. 8/16 bit (data), 8MHz, 5MBps max, 1 BM, no PnP, 1984, IBM. - Rt ph bin, cn tn ti lu, Espec. @ iPC, - Hn ch s IRQs, 4 DRQs, - Dng DIP switch/jumper config. - No data integrity features (no party checking) - Modern OS: Character Typed Devices 1.2. Hot ng ca h thng: Reset, Opcode fetch and Execute, Interrupt, DMA & Ready (wait state - ws) 1.2.1. Lu tng qut:

IRQ? n OpCode Fetch

y y

MaskOn

PC = Intr. Vector

OpCodeDecode

Execute

Hnh 1.3. Lu tng qut ca VXL (Motorola), Training courses

1.2.2. Reset : Cold Start: Nt reset/Power-On =>Xo trng thi hin hnh, cm ngt, DMA. CPU c khi to (PCProgram Counter (IP), Flags v SP...). Thng cc thit b trong h cng c reset. (Sau khi reset, CPU s tm v t/h lnh vi cc th tc sau) Warm Start: do lnh gi, (Int 19h, Ctrl_Alt_Del) POST (Power On Self Test ch/tr monitor/ BIOS) kim tra mi thit b theo nguyn tc ghi v c li (Registers, RAM) hoc c v kim tra Check Sum (ROM). Initializing: t cc tham s => configuring. [My tnh - Np h iu hnh ]. 1.2.3. DMA: (Xem Ch. 3.2.) 1.2.4. Interrupt: (Xem Ch. 3.3.) 1.2.5. Tm v thc hin lnh : Din ra ch yu trong thi gian hot ng. Ch/tr ngn ng my: tp hp cc lnh c cu trc, c ngha, thc hin 1 thut ton. Chu k lnh (Instruction Cycle): Khong thi gian CPU thc hin xong 1 lnh, gm: tm lnh, gii m lnh, [tm ton hng v thc hin lnh (thc hin cc php x l hoc vo-ra)]. di lnh: 1 hay nhiu byte, CISC Thi gian t/h: 1 hay nhiu chu k my (chu k bus). Chu k my (Bus/Machine Cycle): thi gian BusMaster thc hin thao tc trn bus. Clock cycle: Chu k my: 4..12 chu k clock, tu CPU. 1.2.5.1. Hot ng ca h thng: C 8 CPUs BusCycles: M1, opcode fetching, Addr =>Program mem, -MEMR Data mem Reading, Addr=>Data mem, -MEMR Data mem Writing, Addr=>Data mem, -MEMW Input Port Reading, Addr=> IO space, -IOR Out Port Writing, Addr => IO space, -IOW Interrupt Acknowledge, -INTA, Halt, waiting for Ext. Intr. hoc reset Bus Idle 2 DMACs bus (machine) cycles: IOR-MemW v MemR-IOW. 1.2.6. Wait State (Ready):
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Thng dng ghp ni: b nh, ngoi vi tc chm. Hot ng Khi BusMaster pht a ch & tn hiu c/ghi (thm cc tn hiu khc) thc hin 1 chu k bus, MMU/IO port [Controller] ch ng pht ra tn hiu Ready=0 (not Ready) yu cu BusMaster gi nguyn trng thi bus thm 1 [vi] nhp clock. Case Study: IOW bus cycles w/o and w 1 wait state:

Chng. 2 Giao thc ghp ni (Interfacing Protocols)


- Giao thc ghp ni - c im lp trnh I/O 2.1. Interface Protocols: K/n: L cc qui nh: Signals - Data format - Rate - Error detection & correction - Command & Response set - Scenario (kch bn) ISO 7 layer Model (Ref. Computer networks) C th phn chia thnh 2 nhm chnh (Siemens) : Transport-Oriented Protocols (1..4) (!!!) PhysicAL (wire, cable, connector), DataLink (CRC, CS, Token), NetWork (Comm. 2 networks ), Transport (Err-protected raw infor), Application-Oriented Protocols (5..7) : Session (Opening, End), Presentation (Common Language) v Application (Read/Write, Start/Stop, FileTransfer) 2.1.1. Signals: Khi thit k, xy dng ghp ni my tnh, cn ch c bit ti tn hiu theo cc yu cu: bus hay khng? => c dng bit (trng) a ch, Standard bus? ?: IDE v LPT cable c phi l bus? ti sao? Data: Serial vs Parallel Interface, format? Daisy chain cho t/h hoc ngun cp... Cc tn hiu iu khin v trng thi: Control signals Status signals Handshaking signals - bt tay V d 1: PC-LPT handshaking:

PC
LPT port

SLCT

SLTC_in
Line Printer

Hnh 2.1.a.LPT handshake Signal Phng php bin i tn hiu: bin, tn, pha, dng, quang (cp quang, Ir) V d 2: PC Comm-Modem handshaking:

RTS

CTS

PC 1

Modem
or PC 2
DTR DSR

Comm
Port

Comm Port

Hnh 2.1.b. CommPort Handshake Signals T/c vt l ca tn hiu: Mc in p: Voltage ? (TTL, 12V/ 24V/48V...) In/Out, Single End vs Differential (vi sai)
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Mc dng in: (Fan Out, Loading): - Number of Standard TTL/ LS TTL loads, - Sink: dng chy vo LowLevel, mA, - Source: dng chy ra HighLevel, mA/A. (H. 2.1.c) Ni chung cc tn hiu ra: 3 state, open collector, (Open Drain), Mux - dn knh, Switch - kha. Hot swap hot plugible: Y/c Vcc v t/h Cch ly (isolation): Relay, Opto Coupler, IrLED... Bus Slot, Connector, chun, s chn (pin)

Hnh 2.3.b. Optical Connector & S : S cch ly quang hc /v tn hiu In/Out:

Cable & Connectors: Connectors: D shell: DB9, DB25,... DIN, Cable: Flat, Coaxial, Shield, Twisted Pair Normal Optical Fiber...

Hnh 2.3.c. Si cp quang:

2.1.2. Format s liu: i vi file/text: s liu nhiu => khi trao i (vi DAS, PLC, Digi-Oscilloscope, GPS, TelSat...) ng gi s liu (packaging). Mi gi tin (packet) gm 3 phn: - Header: [c th c: tn bn tin, tn gi, s th t, k t bt tay, k t ng b, s k t/ byte trong gi tin...], khng mang tin. - Content: ni dung tin mang thng tin. - Tailer: M bt tay kt thc, [m kim tra li] khng mang tin. V d: HDC, FDC: Full Sector: gap - 5 byte ID field - 2 byte ID CRC - gap - data field: 512 byte - 2 byte CRC. FTP, Kermit, X-Modem.. Protocols: 128[256] B/pack.

Hnh 2.3.a. Connectors Hnh 2.3.d. USB data packet format Byte s liu/character/frame: (truyn khng ng b, RS-232, RS-485, RS-422...): k t hay byte c nh dng thnh 1 frame:
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1 start bit = 0, 5/6/7/8 data bit, D0 first, [parity: Even/ Odd], 1 / [1.5 / 2] stop bit = 1(s).

2.1.3. Tc trao i thng tin: Xut pht t: Nhu cu trao i thng tin ca T/b ngoi vi (nhanh nh LED Board, ADC..), => chn mi trng truyn thch hp, c lin quan ti t/h: Xem Bottle-neck? Khong cch - tch s k/c v tc => Song song (Word/ Byte/ nibble)/ ni tip (bit) Mi trng, ng truyn (cp ng, quang, wireless (radio, infrared) Synchronous/Asynchronous? Modulation/Demodulation ... => tc bao nhiu kbps/kBps, tc chun? V d: LPT: SPP mode: 50..100kBps - software, ECP: 2..4 MBps - DMA LAN Ethernet IEEE 802.3: 10/100 Mbps dual speed RS232: 2400/ 4800/ 9600/ 19200... bps 2.1.4. Kim tra, sa li, nng cao tin cy: Khi trao i thng tin thng hay gy ra li, c bit truyn xa/ chuyn i t/h. Nhiu phng php (Hardware, Software) h tr kim tra: [Block] check sum - BCC, phn mm, CRC, ECC,... vi mch/ software - subroutine Parity, 1 hoc 2 chiu Redundancy (RAID), tha dl, trao i ni dung s liu hn 1 ln v so snh. Case study: Barcode Phng php m ha, gii m v kim tra li Bar Code: EAN 13, CODE 39 (Intermec), CODE 128 (Zebra), UPC ... EAN 13 (European article numbering) Encoding: AAA BBBBB CCCC D; 4 dy vch, 6 vch/digit (b&w) A(National): VN 893, CN 690-692, JP 45-49, GE 400-440, RU 460-469 B: com/ org C: Product D - Check sum, right most: (right to left): 10 - [(D2*3 + D3*1 + D4*3 + D5*1...+ D13*1)mod10] V d: 893 12345 1234 7 CODE 128, Zebra, check sum modulo 103 2.1.5. Command & Response (Result/Reaction) set: Intelligent Devices (Computerized devices - mouse, KB, Printer, modem, FDC, HDC, RTU...) c nhiu tham s, ch hot ng => xy dng b lnh (command set) v thng tin tr v (response set). Dng phn mm x l => bt tn hiu. o Tp hp cc yu cu t CS - command set, o Tp hp cc tr li, trng thi - result/response/ reaction set. Cc cu lnh v tr li c syntax ring (cu trc v ng php). Case Studies: lnh AT v Response Hayes MODEMs: Lnh: ATDT 1260 ' Vi nhiu Options Tr li (reaction) OK [Error] . . . Connect @19200 (result) Lnh FX Printer: Esc * m, n1, n2; Sel Graph Mode Tham kho cc b lnh ca cc thit b chuyn dng: GPS, Gyrocompass, Digital Oscilloscope, SAGEM, TelSat, Programmer (Hi-Lo System All-11P2)... Mt command/response thng c cu trc: o m bt u k t ring nh @ / # / $/ AT... o m lnh, 1..3 bytes/ char, o tham s lnh, 1... n bytes, o m kim tra li check sum, CRC (d x l) o m kt thc, k t ring.
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C thm cc m (k t) i thoi/ reaction, [dng] k t iu khin ca ASCII nh: ENQ, ACK, NACK, Bell, OK, ERR, BUSY ... 2.1.6. Kch bn i thoi Scenario: Lit k cc trng hp c th ri p cc php x l tng ng m bo vic ghp ni: khng mt tin, tha tin, qun, treo... Thng xy dng: Step List hoc Chart: Time Out ! Master ENQ Slave ACK NAK nothing

Hnh 2.4. Scenario Chart

Hnh 2.5. USB Interlayer Interconnection Model 2.2.1. IO Mapping:

Hnh 2.6. Phn min cc cng I/O Memory Mapped IOs: o IOs chung vi Mem trong MemSpace => chim vng nh, tn vng nh o CPU x l cc cng IO bng cc lnh nh /v mem. - IO Mapped IOs: (Z80, x86...):
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o Khng chim khng gian nh, o CPU ch thc hin 2 lnh: IN v OUT x86 CPUs IO map: IO mapped IOs, 16 Addr bit IO => 64Kilo IO locations. - PCs IO map: o IO Mapped IOs, o Ch dng 10 lowest addr bit, A0..A9 => 1 kilo IO locations Soi gng 1st kilo Mirrored vi 63 kilo cn li, Mi IO port chim nhiu a ch (nh PIC, PIT, PPI..) => thiu IO space. S dng thm kiu Mem Mapped IOs. 2.2.2. Lnh In/Out: (x86) : Lnh IN v OUT: ch dng cc thanh ghi Accumulator: 8 bit: AL, 16 bit: AX v 32 bit: EAX. Ch a ch: o Direct: for IO space: 0..0FFh V d: in al,60h ; Read KB port out 23Eh, ax ; lnh sai, IOaddr>255 out 61h,al ; beep, set/reset key flag o Indirect: for IO space 0..0FFFFh, via dx register V d: mov dx,378h ; PLT port Addr mov al, A ;41h/ 65d out dx,al ; 'A' ==> Printer mov dx,3F8h ;Comm 1 port in al,dx;

Chng 3. Cc phng php trao i thng tin Polling - Thm d Interrupt - ngt & DMA - truy nhp trc tip mem - IO
3.1. Phng php thm d (polling) K/n Polling: Dng phn mm kim tra cc c trng thi @ IO Ports => quyt nh trao i s liu hay
khng. Nhanh, n gin, hay dng trong cc h nh hoc n nhim t thit b IO, Khng ph hp vi a nhim

Lu tng qut:
Polling

Device #1 Request ?

Device #1 Service Routine

Device #2 Request ?

Device #2 Service Routine

Device #n Request ?

Device #n Service Routine

Quit

Hnh 3.1. Lu PP IO interface polling 3.2. Phng php ngt (Interrupt): 3.2.1. Khi nim

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Trong mt s CPU, by/ x l cc s kin trong khi thc hin, nh Intel x86: - Divide by zero: tng ng thc hin lnh, Int 0, - Trap Single Step: thc hin tng lnh, debug- ger, Int 1, dng cng vi Trap Flag (Trace). - Break Point: to im dng, debugger, Int 3, - Overflow: (trn s hc), Int 4. - ... d. Exceptions: L vn hay iu kin CPU dng cng vic ang t/h, tm a ch v thc hin 1 ctc, c thit k x l s kin ny. Exception ging Interrupt, thc hin lnh ring. Trong PC, Exp khc Intr qua 2 im: - Lin quan ti vic thc hin chng trnh, - C u tin cao dng ch/tr - V d: Math Processor Exception (Apple Macintosh Computers): cc Error, thay i iu kin, k c ngt, c CPU pht hin trong khi chng trnh ang hot ng. 3.2.3. Case study: t chc ngt ca cc h VXL/My tnh a. Intel 8x51 Micro Controllers: H Intel 8x51 c 6 vectors ngt: 02 Ext. Interrupts: Int0 v Int1, 03 Timer Interrupts: Timer 0, 1, 2 v 01 Serial port Interrupt (pht/thu char). ng vi cc ngt ny, c cc a ch u cho ISR tng ng ti trang zero @ Prog. Memory: 0003, 000Bh, 0013h, 001Bh, 0023h v 002Bh. Ti cc a ch ny thng t lnh LJMP nnnn v c t lnh RETI nu khng c ISR.

Hnh 3.2. K/n ngt Khi CPU ang thc hin CTC, n dng lnh th n, ngu nhin, ngoi vi th i xin phc v bng cch pht ra tn hiu IRQ(i) (Interrupt Request) n CPU. Ni chung, CPU s ngng x l CTC v ct ng cnh vo Stack Mem, ri tm a ch ca ctc phc v ngt tng ng (Interrupt Service Routine - ISR) thc hin. Sau khi thc hin xong ISR, gp lnh iret (reti...), CPU khi phc li ng cnh ca CTC v tip tc thc hin. c im: L phng php Vo/ra kt hp tn hiu v phn mm, thc hin a nhim. Khi nim ngt: CTC b dng x l gi ctc L ch hot ng ring cho cc Vi x l/ my tnh kiu ON-LINE, Ngun ngt: ch yu t ngoi vi, CPU (exceptions, internal), Xy ra ngu nhin, Nhiu IOs, ngu nhin => Tranh chp => Gii quyt u tin ngt. u tin ngt Interrupt Priority: T/b u tin cao c th dng ISR ca t/b u tin thp H ln, nhiu IOs thng dng PIC (Intel PIC8259A) Ch s u tin do nh sx qui nh cho cc t/b ngoi vi, c nh, mc 0 l cao nht. Theo hnh trn: Level (j) > Level(i), i>j. u tin phn nh do cc tn hiu ngt trong CPU (Intel 8085: INTR, 5.5, 6.5, 7.5 v TRAP), Z80 CPU & others: u tin theo kiu Daisy Chain 3.2.2. Phn loi: Gm: Hardware, software, internal, exception, NMI... a. Software Interrupt: L vic gi 1 ctc (Subroutine) c xy dng ring m ctc ny cn c th c gi bi thit b ngoi vi. Cc lnh gi nh INT n; (Intel x86) hay SWI n; (Moto). Tuy nhin, vic thc hin lnh ngt mm ging nh gi th tc, v i khi c hiu l TRAP. Ngt mm khng phi l ngt b. Hardware: - Do Ports pht tn hiu NMI/ IRQ n CPU. - Chia thnh 2: Maskable (c th cm c) v Non Maskable (khng cm c) : Maskable Interrupt: l cc ngt thng thng, c th cm (disable) hay cho php (enable) bi cc lnh CLI v STI (Intel vs Moto!), so called mask che. Cc ngt s b cm - IF disable: sau khi CPU reset, trc c IRQ khc, sau khi th/h lnh CLI. Non Maskable Interrupt, NMI l ngt c mc u tin cao nht, thng cho cc vic: mt in, sai s liu (DRAM parity)... PC hin nay, thng khng dng NMI. c. Internal:
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b. Z80 system: Z80-CPU, 3 modes ngt: Cc lnh ReStart (nh Intel 8085), NMI v Daisy Chain. Kiu Daisy Chain: Ghp ni vi cc Z80-Ports: Z80-PIO, Z80-SIO, Z80-CTC... IRQs t cc ports l Open Drain, Khi CPU: M1 & IO Request => INTA n port1, Nu Port1 Resq, s pht m Addr ln data bus, nu khng Chuyn INTA n Port 2... u tin c nh/ jumper. c. x86 & PC interrupt Bng vector ngt IVT Interrupt Vector Table Real mode: CPU x86: 1st kilo byte (RAM) bng vector ngt 1st KB = 256 elements of 4 bytes Cha a ch u ca ISR tng ng. Khi khi to, BIOS np vo IVT c ca cc ISR ng vi IO.
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i vector ngt: i ni dung cc vector ny Cc ngt cng, NMI v Internal u tng ng vi 1 lnh ngt mm c cng vector type, tc c vector trong bng IVT.

Load ISR v xc nh a ch vt l, Enabling IRQi @ PICs, Mask Reg (OCW1): b(i) = 0, Thay vector ngt, cn lu vector c? Enabling c IF trong CPU, lnh STI, Set Interrupt Enable Flag, cho php ngt

Software Interrupt: Lnh Int n, n=0..FFh. M t lnh: Trc khi thc hin lnh, phi c chtr khi to ngt (Intr house-keeping): nh v ISR v i vector ngt, Khi gp lnh Int n, CPU s ct Flag Reg, CS v IP vo Stack mem, (n x 4) => IVT, c 4 byte tng ng np vo IP v CS, ISR bt u c thc hin. Khi gp lnh IRET, CPU khi phc li t Stack Mem IP, CS v Flag Reg (LIFO). Hardware Interrupt, irq: IRQ trong PC: dng 2 PICs - Priority Interrupt Controller Master PIC (20h, 21h), IRQ0..IRQ7 => Int 8..Int 0Fh Slave PIC (a0h,a1h) = IRQ8..IRQ15 => Int 70h..Int 77h

Hot ng: 1. Khi trao i s liu: Ngoi vi <=> vi IO port 2. IO port pht tn hiu IRQ(i) ti PIC 8259A, 3. PIC pht tn hiu INT => CPU. CPU thc hin nt lnh hin ti 4. Ct ng cnh main prog. vo stack mem 5. #1 INTA bus cycle => Prioritizing 6. #2 INTA bus cycle => c Vector type ca IO port, VectorType = i+8. 7. (VectorType x 4) => IVT, c c ISR tng ng, np vo IP&CS, IRS bt u c thc hin. 8. ISR: (nu dng ASM) - Realtime Prog. Languages: MASM, C, ... , - Enabling Interrupt for Higher priority Levels, - Ct nhng thanh ghi-ISR dngvo STACK Mem, - T/h ni dung ISR, - Khi phc Reg t STACK Mem, LIFO, - Depriorotizing: OCW2: V d: mov al,20h out 20h, al ; Non Specific EOI iret ; Return fron Intr. d. Xy dng PC ISR: - NN cao Pascal/C: Pointers (for Old Vector) v procedure c ch dn Interrupt. Ch cn c thm cc lnh STI v CLI hoc inline m my FAh v FBh (En/Dis). - MASM v OS: thay vector ngt trc tip, lnh mov cc con tr vo IVT; int 21h subfunctions: 25h v 35h ca DOS. - Case Study: Xy dng ng dng dng ngt cng ghp ni ngoi vi: IRQ1 (Any key), IRQ4: CommPort, IRQ5 (Option) v IRQ7 (LPT1, Falling Edge of -ACK)... - Thng tr ngt thi gian Int 1Ch thuc Int 8 ISR, Timer 80x86 Interrupt in Protected Mode: Int. Descriptor Table (IDT) c th nh v bt k vng nh no V tr v kch thc trong bng IDTR: 32bit addr v 16 bit limit Gate, not vector. 256 gate descriptor: trap/ interrupt/ task - ISR's Addr & Attribute Int/ trap cho php chuyn n ISR trong current task.

x86 & pc, Hardware Int Priority Interrupt Conteroller Intel 8259A: 8 Channel (8 I/O ports) u tin c nh, vng, vng nh trc Ni tng vi Slave PIC(s), m rng thm IOs Nhiu ch hot ng ICWs & OCWs Dng vi nhiu h VXL, IBM-PC ... Tham kho VXL ca MTV x86 & pc, Hardware Int: Hardware Interrupt, IRQ: Hot ng Hardware Intr trong PC, xem PIC 8259A Interrupt Housekeeping - chun b: files.sys[com], (Vd gmouse.com - cng comm 1)
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DMAC#1: 8 bit Channels, 64KB max:, 0h 01fh addr Ch0 - DRAM Refresh, Spare Ch1 - SDLC, LPTs ECP mode - Alt., Spare Ch2 - FDC, single byte mode Ch3 - LPTs ECP mode, Ir port, Spare DMAC #2: 16 bit Channels, 64KW max, 0C0h Ch4 - Cascade for DMAC 1 Ch5 - HDC, spare Ch6 - Spare, Ch7 - Spare Page Registers: 080h..08Fh: Gi a ch cao SysBus in DMA mode, AEN = 1 (AddrEnable)

CLI STI LIDT EA ; Load IDT t Effct Addr SIDT EA INT n IRET INT O ; ( INT 4) HLT ; Wait for Ext IRQ or Reset WAIT ; Wait for -Busy => inactive 3.3. Direct memory access DMA 3.3.1. Khi nim: Controlled by DMAC, bus master In/Out dng hardware [burst mode] => nhanh, 33/66MBps Chuyn block/ Single byte IO Mem, Mem Mem (t) Specified Block/ IO Requirement Stealing cycle (DRAM controller Intel 8208) DMA House keeping: Addr lines (DMAC & Page Reg) input/ Hi-Z Init: 8bit(Master:0..1F)/ 16bit (Slave:0C0..0DFh) Channel (i): DRQi v -DACKi Port (IO Addr), AEN = 1 (Address decode) IOR-MEMW hay MEMR-IOW Hi Addr of data memory => th/ghi trang t/ng. Addr t Ch0 (hex): 87, 83, 81, 82, 88, 89, 8A, IO space Low Addr => BaseAddrRegi, (TechHelp 6.0) Kch thc mng: BaseCounteri Single byte/ block Specificed block/ IO Port Requirement IOR-MEMW bus cycle Bt u t/h DMA, ngoi vi chuyn data => IO Port IO Port pht tn hiu DRQi ti DMAC. Nu chp nhn DMAC pht HRQ ti CPU (CPU logic circuitry) CPU dng hot ng @ state T3, Hi Z bus CPU Tr li t/h HLDA => DMAC & goes to sleep Thc hin DMA bus cycle: - (-DACKi = 0 & -IOR = 0) => IO Port 'nh' sl ln bus - Addr (DMAC & PR) => data mem, -MEMW => chuyn 1 byte/word Tng CurrentAddrReg, gim CurrentCounter. Nu CC=0 th pht T/C, nu <>0 => , next DMA bus cycle

3.3.2. Dmac intel 8237a: MTV 4 Channel of 8/16 bit IOR-MEMW & MEMR-IOW DMA bus cycles Mem to Mem Single byte/ block transfer (64KB/Kw max) u tin c nh/ vng Specified block (TC) / IO Requirement (EOP) Ni tng m rng s knh DMA ... 3.3.3. PCs DMA:
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Chng 4. I/O Interface bus overview


Gii thiu bus chun cho ghp ni, m rng: ISA/ PC-104 AT bus USB (Universal Serial Bus) Philips I2C PCI (Peripheral Component Interconnect) SCSI (Small Computer Systems Interface) GBIB (General Purpose Interface Bus) Siemens Profibus IEEE 1394 ... 4.0. Khi nim v bus: PCB (Printed Cirrciut Board), Cable (Copper/ Optic), Slot, Connector... Ni nhiu thit b slave [master], dng chung Nhiu line (bit) hoc i dy (I2C, USB, SSA, Profi) Thnh phn (physical lines/ time sharing): Address Data Control/ Status/Handshake ~ [Power supply] 4.1. Industry small architecture (isa) bus: ISA/ AT bus, 1984, IBM, PC-104 bus, Available in Pentium, PowerPC Platforms ghp thm cc thit b I/O chun vo Mother Board, 3..8 Slots, Hin ti cc my c th khng dng slot 8/ 16 bit for data transfers 8,33 MHz => 5 MBps max Only 1 BusMaster, CPU hoc DMAC No data integrity, khng kim tra parity, IO Check Dng ghp vi cc thit b chm, kiu k t: character typed devices : keyboard, mouse... Refer AT Technical Reference or TechHelp for detail

Topology Rev.1.1: 23/09/1998 Chia thnh nhiu Tiers Cc Tiers ni cc thit b: Hub hoc chc nng Mi Tier c Hub(s)

4.3. USB: specifications

Hnh 4.1. AT/ ISA/ PC 104 bus 4.2. Universal serial bus - usb:

Ch c 1 USB host (USB Controller) trong h Devices, c 2 loi: Hub, m rng thm thit b ni vo USB Cc thit b chc nng nh ISDN, JoyStick, KB, Printer... Thit b chun interface USB theo: USB Protocol Chun H ca USB: config v reset Communication Standard USB Controller/ Host polls bus & initiates all data transfer u im: Tn hiu vi sai pht/ thu, bc kim, chng nhiu CRC Protection /v data & control fields
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T pht hin attach/ detach, xc nh cu hnh cc thit b t ng mc h thng TimeOut /v trng hp mt gi tin/ gi tin li 4.3. USB: Physical interface

1.5 Mbps Low speed mode v 12Mbps (Revision 1.1) Ngun cp +5V, vi metre Power managment Revision 2.0: 480Mb/s

4.4. Philips I2C bus version 2.1. Jan. 2000

Philips, 1992 Ver. 1.0;... 1998 Ver 2.0, 2000: Ver 2.1, dng cho cc h thng nhng (embeded systems) Khng cn dng bus interface chip(s), built-in Integrated addressing & data-transfer, cho php dng phn mm nh cu hnh Thm/ bt IC khng nh hng bus system n gin tm li, khoanh vng li nhanh Gim thiu kch thc: 2-wire serial, khng cn cc mch Addr Decoder v glue logic, dng phn mm Truyn ng b, 100 kb/s Standard-mode, 400 kb/s Fast-mode, 3.4Mb/s HiSpeed-mode

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Multi byte R/W :Addr auto Inc/ Dec; Master/ Slave :Send A[ck] (=0) hoc /A (NACK) (=1) ty thuc bit tip theo l data hay Stop Mt s vi mch dng I2 C bus: Dallas RTC 1307, 1308: 64 byte RAM & Real Time Clock, Philips PCF 8593, Low Power Clock/ Calendar Atmel 93C46/24C96... EEROM C th ni nhiu Masters, trong 1 t/ ch 01 BMs Active

Start(Rep Start, S) Stop (P):

SCL=1, SDA= SCL=1, SDA=


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4.5. PCI - Peripheral Component Interconnect 5/1993, Intel Ver. 2.0, Open standard, Local bus, trung gian gia Local v cc bus chun khc (ISA, MC, EISA) thng qua PIC Bridge/Controller. C kim tra parity cho Addr v Data Auto configuration of all PCI devices, share the same IRQ. Disabling IRQ => cm ton b PCI devices. No DMA, device on PCI bus l bus master (Tt cho vic dng MultiTasking OS). Burst mode: 32 bit @33MHz --> 96..132MBps, tu thuc s byte (t 32 byte n 4KB). Option 64bit @33MHz --> 264MBps, 64bit 66MHz. Most Platforms use:Intel, DEC Alpha, PowerPC, Spark
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Modern OS: Block Typed Devices: tn sut vn chuyn cao, nhanh, data block 4.6. Small computer systems interface - SCSI SCSI (SCSI-1): 1990; SCSI-2: 1993 to now; UltraSCSI:... Dng cho Disk controller c b lnh ca n, Thng c 1 Adaptor, khng nm trn motherboard Support any SCSI device: Disk, CD-ROM, tape, scanner 5 to 40 MB/s 7 devices max, upto 15 with SCSI-2 FastWide and UltraSCSI

Hnh 4.15. Mng Profibus Tn hiu: C loi cable n v vi sai (chng nhiu tt hn), cc controller support 2 loi tn hiu. Khng ni 2 kiu trn cng bus. Most: SingleEnd, RS6000 differential. SCSI Common Command Set: c gi t device driver, xc dch bi th/b => Adaptor khng phi thay i khi gn thm thit b SCSI subsystem gm: Host adaptor ( interface gia host system v subsystem), SCSI controller, bus, thit b. SCSI Controller & devices: 8.. 16 devices, 1 as Controller. Th t u tin ca cc thit b, cao nht l 7 (Controller) 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 8 data bit => 1 parity bit. K/tra Data: ECC, a ch CRC @ mi sector 4.7. Siemens process & field bus profi bus 4.8. General purpose interface bus - GPIB As known IEEE 488; HPIB (Hewlette-Parkard Interface Bus), IEC 625 bus c thit k kt ni mng my tnh vi cc thit b ngoi vi, o lng - kim nghim, lab... kiu Program-mable Instrumentation 14 devices c th ni vo GPIB, ...1MB/s, couple meters 24 pin connector: 16 lines: 8 data, 3 handsshake, 5 management ( iu khin vic dng bus), remainders: Twisted/ Logic Gnd, Shield Computer as Controller; cc thit b khc l Talkers/ Listeners. Trg 1 t/: 1 device - Talker, Others Listeners ni mng:GPIB Card,cable,connector(Hnh 4-16/17/18)

Gii thiu: Mi trng cng nghip, Chun EN 50170-1-2 Kt ni nhng thit b vo ra phn tn, thng minh (PLCs, Motor drivers, ), 1 trong nhng layers ca mng CN: SINEC-L2 Bao gm cc giao thc: PROFIBUS DP (Distributed I/O):trao i sl vi cc slaves qui m nh, nh k, tc cao Profibus PA: Process Automation: IEC 61158-2: mi trng khc nghit. S liu v power chung line (PLC), 31.25 kbps PROFIBUS FMS (Fieldbus Message Specification): Kt ni PC vi cc thit b t ng ca Siemems: S7/M7/C7 Families kiu cell S liu c cu trc, khng ph thuc vo ng truyn.PROFIBUS F PROFIBUS FDL (Fieldbus Data Link): tng thch vi cc mng con Spec.: Token bus: cho nhiu masters (active nodes) Master - Slaves >1km (RS-485) v 9.6km (Optical Fiber) M ha Manchester II tin cy v chng nhiu tt

Hnh 4.16. Mt s PC's GPIB interface cards

Hnh 4.17. GPIB connector & signals

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Chng 5. Digital interface


PARALLEL IN/OUT PORTS: principle, PPI, Centronics PCMCIA, Dual ported Ram INTERCACING to devices: LED, LCD, encoder, STEP motor, ... HI-POWER INTERFACE: relay, scr, triac, power mosfet, igbt... SERIAL IN/OUT: Sync, async, RS-232, RS-485, RS-422 modem...

Hnh 4.18. IEEE-488 Instrumentation & connector 4.9. IEEE 1394 - Firewire IEEE 1394 serial bus, 1997, by Apple & TI, thay th SCSI Upto 63 nodes (devices) connect to a PC, hot plugible High speed: 60 to 400 Mb/s (7.5 to 50 MB/s) Cable: 6 wire (2- power carier lines 8..40Vdc/ 1.5A), 15'. Daisy chain extending to over 200' P1394 - PCI bus <=> Audio, Video devices, CD, disk, printer... Tree topology: 63...64k nodes (bridge across buses) Addressing single node, broadcasting all nodes, config time < 400 us More than one PC can be connected to P1394 bus

5.1. Parallel interface: 5.1.1. Nguyn l Output Port: latched Output (cht ra), D_Flip-Flops Unlatched Input, hnh 5.1. single

Cng ra n gin: dng cht 74 HC 374, (hnh 5.2) Ngoi vi c s liu => pht tn hiu strobe=0 Hnh 4.19. S ghp ni cc ngoi vi qua IEEE 1394 bus

Out Port: 74 HC 374: CPU pht a ch ra IO space => c t/h CS Pht data v -IOW => c t/h LE = (Rising Edge) => data c cht vo HC374 Port song song c tn hiu bt tay/ trng thi (outport): Gi 1 packet ra ngoi vi, ng b gia 2 pha IO device ch c cng khi c s liu (IBF) CsS ch gi s liu ra khi byte/char trc c c bi IO device (OBE) Ch Time-Out-Error

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Data Out port, X78h, TTL, (some bi-dir, In when 1s out!) Open Coll. Buffer - 8 bit latched out, back readable LPT: send control & printed chars to Printer Control Out Port: X7Ah, TTL 4 bit latched out, back readable LPT: -Strobe (b0), AutoFeed (b1), -Init (b2), SLCT(b3) IRQ_EN (b4), not outlet Status In, X79h, Unlatched, TTL 5 bit: b3..b7: Err, SLCT_IN, PE, -Ack, busy

5.1.2. Programmable ports Ports: Intel PPI 8255 (Programmable Peripheral Interface) Motorola PIA 6821 (Progr. Interface Adaptor) Z80 PIO (Parallel In/Out) ... Flexible Specifics: 2..4 In/ Out Ports, single line direction (PIA/ PIO) Mode: IN/OUT w [w/o] handshake, bus transceiver Control/ status/ HSK: Edge (, )/ Level (hi, lo) Case study PPI 8255: 4 ports: PA, PB, PCH & PCL, 24 IO lines 3 modes: M0, M1 & M2 n gin v hiu qu

Enable Int Req:


mov dx, 37Ah; LPT 1 control in al, dx or al, 00010000b out dx, al ;

Disable:
Port[BA+2]:=Port[BA+2] and $EF; Mode 1: enhanced parallel port - EPP Xircom, 1992, Hi speed - 2 MB/s (1 ISA bus cycle), bi-directional port, Ext HDD, Network... 8 Registers: Offset 0: SPP data , R/W data lines, w/o HSK Offset 1: SPP status, Read (b3..b7), b0 timeout Offset 2: SPP control, R/W 4bit C0..C3, C4: IRQ En, C5: byte dir Offset 3: EPP addr, R/W addr cycle w HSK Offset 4: EPP data, R/W data cycle w HSK Others: may be use for 16/32, port config, user define Mode 2: extended capabilities port - ECP MS-HP, 1993, 2..5 MB/s (1 ISA bus cycle), bi directional port, Ext HDD, Network... extension sys bus 16 FIFO byte buffer gi/ nhn, DMA: Mem <=> buffer C th ghp ni vi cc ngoi vi chm khi dng Rdy M phng h ca SPP, EPP mode R/W: data & commands: OUT -C1 (HostAck); IN -S7 (Per. Ack). -C1/ -S7 = 1 (sending data); 0 (command) Command: b7=1, b0..6: channel addr, b7=0, b0..6 run-length count for data compression mode (m cc byte ging nhau - graphics, hardware) OUT -C1 (HostAck); IN -S7 (Per. Ack).
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Hnh 5.3a. Ghp ni PPI 8255 vi PC qua ISA bus 5.1.3. Centronics port Centronics Computer Inc. so called LPT, 2 LPT ports (available) in PC Modes: SPP, EPP, ECP & IEEE 1284 (EPP+ECP) IRQ (7/ 5) & DRQ (1/ 3) support for many applications of Interface: Printer Local Area Network Ext. HDD Test Digi In/Out, ADC, DAC interface Programmers (All 11P2) Mode 0: Simple Parallel Port - SPP (Normal mode) 50..100kB/s, cable: 10' max - 25/ 36 lines

-C1/ -S7 = 1 (sending data); 0 (command) Command: b7=1, b0..6: channel addr, b7=0, b0..6 run-length count for data compression mode (m cc byte ging nhau - graphics) Many chip (SMC's super IO...) h tr decompress, phn mm gi ra phi 'compress' 6 registers: 3 SPP reg v 3 ECP reg Base addr + 400h: data FIFO & config A-Read only Base addr + 401h: Config B (interrupt, DMA...) Base addr + 402h: Extended Control Register Mode 2: ieee 1284 ( epp + ECP ), 1994, 5 MB/s IEEE 1284 standard - document: defines/ describes protocols for Parallel-port Communication. Include: 1284 port/ 1284 cable/ 1284 Peri. 5 communication modes: (Register use - Table 11-1 p206, Parallel Port Complete) Compatibility Mode: Host sends a byte to Peri. (with Busy v -Ack) Nibble Mode: Peri. to Host 4 bit, remainder - HSK Byte Mode: 8 bit, bi-dir EPP Mode: 8 bit, bi-dir, hi-speed ECP Mode: 8 bit, bi-dir: data, addr, compression 5.1.4. Dual ported ram chuyn mng s liu gia 2 h VXL (Master-Slave) vi tc cao, gn, ... (Switching Systems, PLCs, Graphics Accelerator...) SRAM, dung lng t 1KB n 256KB Multiple Reads & Writes ng thi Dng cc tn hiu: 2 x n bit Addr for 2 sides: Left - Right => 2n mem loc. 2 x 8 [16] bit of Data Cc tn hiu iu khin (RD, WR, CS) v trng thi Cc tn hiu bt tay/ trng ti Hng: Integrated Device Technology Inc. & Others; chip IDT 7707, 32Kbyte DPR

Kin trc phn nhiu tng m bo tnh vn hnh c lp vi phn cng: Socket service: Device driver - system manufacturer Card service: Device driver - Operating System Vendor Client Drivers/ Client Enablers, Driver to cc y/c ti h thng: do hng ch to Card cp Enablers/ Point Enablers: Driver chuyn thng tin trc tip Host Adaptor PC Card Standard - CardBus: 32 bit transfer Based PCI specification 33MHz/ 132 MB/s BusMasster support Compatible w 16 bit card

LED - Light Emitting Diode Bao gm: Point, 7(16) segment, matrix: text/ graphics Drive: Static/ Dynamic Scan Dng Latch/ PIO H5.6 Static Display H5.7: scan 8 x Com-mon Cathode 7 seg LEDs

5.1.5. PCMCIA Personal computer memory card international Association, Ver 2.1; pc card standard (5.0) 1996 L chun ca nhiu t chc/ cng ty: >500 members PC card device - credit card size adaptor: nh, d mang, hot plugability, tin cy khi mi trng thay i, 68 pin connector Devices: Flash, SRAM, modem, LAN (wire & wireless), disk, audio w DSP, GPS... 16 bit data path (PCMCIA 2.1/ PC Card Standard 5.0) 3.3 and/or 5 V Dng vi nhiu loi bus

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5.1.6. Led interface drive 8 x 7 Segment Common Cathode: disbuf: 8 byte cha m 7 seg cn hin th, N: counter Main Program: Burn LEDs, gm (1) Init: turnoff LEDs; N=0; (2) (disbuf+N) => 1st Latch; turn On LED[N]; delay(1); (3) Turnoff LED[N]; Inc N ; If N = 8 then N=0; (4) Goto(2) drive 8 x 8 matrix char box: disbuf: 8 byte cha font Main Program: Burn LEDs 1. Init: turnoff rows; n=0; 2. (disbuf+n) => LS164; shift afap; turn on row[n]; delay(1-1.5); 3. turnoff row[n]; Inc n ; If n = 8 then n=0; (4) Goto(2) Smooth shift left/ right? Color: 4/ 256 color LED duty cycle!

Hnh 5.10a. Text LCD Pannel

Hnh 5.10b. Cu trc ca Graphics LCD Panel

Hnh 5.10c. Tn hiu v gin thi gian ghi LCD panel 5.1.6. LCD panel interface Cng ngh LCD, hin text/ graphics phn di: 1 line x 16 character box 2 line x 16 character box 4 line x 20 character box (64 x 128) hoc (128 x 256) dot... font down loadable ASCII... upto 128 characters/ set APA: All Points Addressable Back lit, cng sut tiu th nh Dng cho cc h nh, mang xch, my o...
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5.1.7. Encoder

Dng ghp ni o lng dch chuyn c hc: chiu di, vn tc, gia tc, tc quay, nh v, robot Cng ngh vt liu t - nam chm vnh cu hoc quang - hng ngoi/ laser, hi resolution ADC... phn ly cao: 256 ... to 500 kc/t (counts/turn), chu shock (100G) Tc cao 10krpm, m men cn nh (vi 10-3 Nm) Output: cc xung lch 90O hoc RS 485 (byte, BCD, GrayCode formatted), truyn xa 1 km
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Manufacturers: Tamagawa Seiki, Hewlett-Packard...

Thyristor (SCR - Silicon Controlled Rectifier)

Hnh 5.12a. Step Motor

Hnh 5.12b. Symbolic Diagram of Step Motor

Hnh 5.12d. Cc s ni dy cho step motor 5.1.8. Hi power interface L cc mch ghp ni my tnh/ VXL vi cc thit b c in th cao/ dng in ln nh l nung [sy] in tr, l cao tn, motor (ac v dc) cng sut ln... iu khin thit b in xoay chiu (ac): Relay, [r le trung gian] hnh 5.13a: Dng Relay cch ly [v relay trung gian], iu khin cng sut ON-OFF (l in, motor) Triac, Solid State Relay hnh 5.13b: iu chnh cng sut v cp gy nhiu cho li in, phi c Line Filter iu khin thit b mt chiu (dc): Hnh 5.14.
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5.2. Serial in/out: 5.2.1. Khi nim Thng tin trong H VXL/ My tnh: byte Khi truyn 'xa': byte => dy bit, serialize; dy bit => byte, deserialize: gim thit b thu pht v ng truyn, gim chi ph, tc chm, M hnh: Hnh 5.11. Central System: CPU, mem, controllers, sys bus... Serial port: Symbols: UART/USART (Universal [Synchronous] Asynchronous Receiver Transmitter) SIO:Serial In/Out Port ACIA: Async. Communication Interface Adapter , MC 6850

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Hnh 5.21d. QAM:Quaternary Amplitude Modulation

Serial ports: Nhim v: Bin i byte <=> dy bt + cc bit khng mang tin (start/ stop/ parity...) v dy bt <=> byte, loi cc bit khng mang tin, bo li khi thu. Ghp ni vi h trung tm: cc bus/ tn hiu addr, data, control bng phng php Polling, Interrupt hoc DMA. Ghp ni vi ng truyn [via modem]: TxD, RxD Ghp ni modem: -RTS, -CTS, -DSR, -DTR, -CD, -RI V d: UART 8250, 16450, 16550A (Intel, NS...), USART 8251 Intel, ACIA 6850 Moto. MODEM: l thit b bin i tnh hiu logic TTL (0/1) thnh cc tn hiu vt l, ph hp vi mi trng truyn xa v ngc li, gm: Converter/ driver: Max 232/ ICL 232 (232 modem): TTL <=> RS-232, Single End: -3V .. -15 V <=> '1' +3V .. +15 V <=> '0' n gin, 100' @ 9600 bps, d b nhiu Thng dng ghp ni cc thit b thng minh trong CN (gn), th nghim, o lng, iu khin Maxim 485/ SN 75 116... (485/422 modem): Differential V(a) - V(b) > 100 mV <=> '1' v V(a) - V(b) < -100 mV <=> '0' 5000' @ 1Mbps, thc t c th truyn xa vi km. Thng dng trong cc x nghip cng nghip Current Sourcer: 0 v 20 mA [hoc 20 v 60 mA] Chu nhiu tt Truyn xa, ty thuc in tr R ng dy, Thng c cch ly quang hc. Hnh 5.21a. ASK: Amplitude Shift Keying

Khi nim truyn tin ng b v khng ng b: Thng tin thng c ng gi thnh cc gi tin. ng b: Trong 1 packet: byte byte, bit bit, khng c du hiu phn cch. Tc truyn do sender: clock (cng vi data) hoc ch xut hin vo thi im u trong gi tin (sync. character). Tc cao, kh, t l cc bit khng mang tin nh. Truyn tin khng ng b: Asynchronous Comm. Mi k t/byte u c 1 xung/sn ng b (sn xung ca start). Clock ca 2 pha thu v pht c th lch nhau 3-5%: V d: @ format 8,n,1; T: time of frame; t: time of bit, T lch cho php Tpht v Tthu. T < 1/2 t = 5%T. C khong 'trng' gia 2 characters, trng thi 1 - mark. T l cc bit khng mang tin ln (start, stop, parity), ln n 33% (v d 8,PE,2) n gin, d lp trnh, d ghp ni. c bit c chp nhn rng ri: thit b ngoi vi thng minh, o lng iu khin, modem...

Hnh 5.21b. FSK: Frequency Shift Keying

Hnh 5.22.Ba m hnh ng truyn: Simplex (a), Half duplex (b) v [full] duplex (c) DTMF: Dual Tone Multi Frequency, a tn, Mitel8880 Hnh 5.21c. PSK: Phase Shift Keying 5.2.2. Chun RS-232c/v24 EIA 1969, Electronics Industry Association, cho truyn tin khng ng b v truyn qua mng in thoi. Nhiu nhc im so vi cc chun khc: tc chm, khong cch gn, single end signal - d nhiu, lng bt khng mang tin ln... nhng...

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Rt thng dng, c trong nhiu cc thit b my tnh, my iu khin, my o ... v cc vi iu khin, GPS, Gyro Compass, PLC, Switching System... L ca ng trao i thng tin gia cc h VXL khng cng chun (s bit, b lnh, tc ...) 5.2.2.1. FORMAT of FRAME: 1 start bit = 0, 5/ 6/ 7/ 8 data bit, D0 - first, [Parity bit - PE/ PO], 1/ 1,5/ 2 stop bit = 1s

Hnh 5.23. Cu trc RS-232 Frame trn ng truyn 5.2.2.2. M hnh v cc tn hiu:

Cc tn hiu truyn tin: TxD - Transmit Data: Serial data out + bit khng mang tin RxD - Receive Data: Serial data in + bit khng mang tin Signal Ground: 0 Volt. Reference for Single End Signals (Null modem protocols, X-On & X-Off) Modem handshaking signals (Low active): -RTS - Request To Send, Out - DTE -CTS - Clear To Send, In -DTR - Data Terminal Ready, Out -DSR - Data Set Ready, In Line status: -RI - Ring Indication, In -[D]CD - [data] Carrier Detect, In 5.2.2.3. Mc tn hiu: Cc tn hiu RS232 c mc p: -3V .. -15V => mc logic 1, mark, so vi Gnd +3V .. +15V => mc logic 0, space Cc vi mch dng bin i: Motorola MC-1488 (TTL to 232) v MC-1489 (232 to TTL), 3 ngun cp :+5V, +12V, -12V MAX 232 - ICL 232: l RS232 'modem' ; Single Power Supply +5V. Bn trong c cc b i ngun: Doubler v Inverter => +10V v -10V, Hnh 5.25

Hnh 5.25. MAXIM 232 IC, DC/DC converter 5.2.2.4. Tc truyn tin: n v tnh l bps (bit per second) Cc tc RS-232 : 50, 75, 110, 150, 300, 600, 1.200, 2.400, 4.800 v 9.600 Thm: 19.200, 38.400, 57.600 v 115.200, Dng quartz 1.8432 MHz 16 chu k clock => truyn c 1 bit Thng trong cc cng truyn tin, tc c tnh theo: 1.8432 x 106 (Hz) Baud rate (bps) = ----------------------------16 (m x 256 + n) vi n : low divisor, trong m: hi divisor, V d: 9600bps => m=0, n=12 5.2.2.5. Khong cch : Ty thuc nhiu mi trng, cp truyn, nhng: @ 9600 bps, L < 100' @ 19.200 bps, L<50' 5.2.2.6. Connector: D shell 9 hoc 25 pin [DB9 hoc DB25] connector 5.2.3. PC RS-232 ports So called: RS 232C/ EIA Communication port Asynchronous [Async] port Serial port UART / Intel 8250, UART National Semiconductor 16450, 16550, 16550A Properties: Port Comm1 Comm2 Comm3 Comm4 BaseAddr 3F8h 2F8h 3E8h 2E8h IRQ 4 3 Option Option UART Intel 8250 , KT VXL - MTV CS interface: 8bit data, IRQ (for Trans, Rec, Modem & Errors), -CS, -RD, -WR v Reg Select lines. Modem Interface: -RTS, -CTS, -DTR, -DSR, -CD v -RI Control Registers (Line & Modem): nh format v ch hot ng. Divisor Latches: nh tc truyn (thu v pht) Status Registers (Line & Modem) c trng thi, Errors hot ng polling v Int. UART NS 16550A: FIFO buffers for Rec v Trans 16 byte, Hot ng: polling, interrupt [c thm] DMA
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Tham kho UART 16550A @ site: www.ns.com Hot ng ca comm port Setting: Chn cng/ format/ tc / mode Selecting Port: BaseAddr:= Comm2; {$2F8} Format of character: (Line Control Register - BA+3) Vd 9600, 8, N, 1: Port[BaseAddr+3]:= 3; {$2FB} Baud rate: Access: DLAB bit @ LCR, Low Div v Hi Div. Khi setting baudrate, DLAB=1, otherwise=0 Port[BaseAddr+3] := Port[BaseAddr+3] or $80; Port[BaseAddr+0] := 12; {Low divisor} Port[BaseAddr+1] := 0; { Hi divisor } Port[BaseAddr+3] := Port[BaseAddr+3] and $7F; Mode: Interrupt/ DMA? Hot ng Transmitting: Line Status Register LSR, BA+5 Sending 1 char: Port[BA+0]:= char_send; Sending 1 packet n byte. bit 5 (of LSR) = 1 => THRE (Trans Hold Reg Empty): For i:= 1 to n do Begin Repeat Until Port[BA+5] and $20 = $20; Port[BA+0]:= char[i] End; {khng cn kim tra TimeOut hoc li} Gi 1 packet dng Int?. Hot ng Receiving Line Status Register LSR, BA+5, cc bit/ c TT: b0 = 1 => data received, =0 khi CPU c Receice Buffer b1 = 1 => OE, OverrunErr b2 = 1 => ParityErr b3 = 1 => FramingErr b4 = 1 => BreakInt V ch TimeOut Th tc thu 1 packet c m t Hnh 5.26:

b3 : MODEM IRQ Interrupt Identification Register: BA+2, c Reg ny bit ngun ngt, c 4 mc u tin c nh, dng b1 v b2: xxxxx11x Highest Prio., 1 of 4 li thu xxxxx10x Thu xong 1 char/ byte xxxxx01x Pht xong 1 char/ byte xxxxx00x hoc ca 1 of 4 modem HSK. 5.2.4. Hayes modems Do Cng ty Hayes Microcomputer Product Inc. gii thiu vo u 80s, tc 300...2400bps, over telephone line C b lnh (command set) v tr li (response set), c dng nh cc lnh chun AT (standard modem). Tn hiu: TxD, RxD, Gnd, CD, RI. [Thm] DTR-DSR, [RTS-CTS] Ch hot ng: Command v data (online) Modes Command Mode: modem nhn lnh t my tnh hoc CS qua RS-232 port v thc hin - khng truyn tin. Khi thit lp xong kt ni vi remote modem => Online mode (data mode) v ch truyn tin.

Hnh 5.26. Lu Thu 1 packet qua Comm Port - Polling INTERRUPT SETTING IRQ 4 - Comm1, IRQ3 - Comm2. Enable Interrupt Register - IER, BA+1, 4 lowest bit. b0 : Thu xong 1 byte/ char b1 : Pht xong 1 byte/ char b2 : 1 of 4 Errors of Receive Action

b(i) = 1 => Enable; b(i) = 0 => Disable.

Hnh 5.27. Block diagram of Hayes Compatible Data-Fax Modem Chuyn t O sang C mode: Khi mt sng mang (remote modem has hungup) tr v command mode khng disconnecting i Guard time (default 1s) Escape command +++ Lnh gi t my tnh: software hoc g trc tip t bn phm qua RS-232 port Cc k t trong cu lnh gi ra theo 1 trong 2 formats: 7,PE,1 hoc 8,N,1 Khi truyn 110 bps => 2 stop bit Khi nhn command, modem gi v result code. Option: Digit code - for controlling modem by software Word code - for controlling modem by keyboard result codes: DIGIT Word Meaning 0 OK Cmmnd executed 1 CONNECT Connect @ 0..300bps 2 RING ring signal detected 3 NO CARRIER 4 ERROR error in cmmnd line 5 CONNECT 1200 6 NO DIALTONE
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7 8 10

BUSY NO ANSWER CONNECT 2400

Chng 6. Analog interfacing


In this Chapter: Analog Signal Interface Overview Analog Electronics Digital to Analog Converters Analog to Digital Converters DAS - SCADA - DCS 6.1. Analog signal interface overview: L hm ca 1 (hoc nhiu) bin c lp, i lng vt l theo thi gian: nh ting ni, nhit ... theo thi gian: A=f(t,h) Xut hin lin tc trong khong thi gian t0 - t1 Gi tr bin thin lin tc trong khong bin t A0 n A1 , c th a tr.

AT COMMAND SET Cc lnh bt u bng AT or at (not At or aT) modem nhn dng tc v format (ngoi tr 2 lnh '+++' v A/) v kt thc: Enter Command line: c th c hn 1 lnh, ch cn 1st c AT, cch nhau du ' ' khng qu 40 char/cmmnd line. Cc lnh v Option ATDT 8692463 dial using touch tone ATDP 8696125 pulse ATT/ ATP default tone/ pulse O end of C line, return O mode ; end of C line, stay C mode after executing @ wait for 5s hoc silent V d: ATDT 9,3456789 Kt ni t my trong tng i ATXn Hayes Smartmodem compatible Other Commands: ATE0/ 1 Disable/ Enable echo +++ Esc Char switch to command mode ATHn 0:On-Hook (hangup),1: Off-Hook ATLn 0/1/2/3 volume of speaker ATMn 0: speaker off, 1: on until DCD, 2: on ATNn 0: connect @ DTE rate, 1: auto rate negot. ATO return to O mode ATQn 0: result code En, 1: result code Dis ATVn 0: digit, 1: word ATZ hangup, reset to default settings A/ Repeat last command (re dial) Cc modem u c b lnh ring, Ref. User's Guide Man.

Trong thc t: Trong My tnh s, thng tin: Ri rc v thi gian Ri rc v gi tr => my tnh thu thp, cn phi 'ri rc ha' cc tn hiu v thi gian v gi tr, dng thit b chuyn i ADC, : X l, ct vo kho s liu Truyn gi i xa Ti to li hay tng hp tn hiu: dng thit b DAC

Hnh 6.02a. M hnh ghp ni tn hiu analog

Hnh 6.02-b. M hnh H o lng - iu khin s 6.2. Analog electronics: Operational Amplifiers - OpAmps
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Analog Switches & Analog Multiplexers Reference Voltage Sources Sample & Hold Conversion Errors ... 6.2.1. Opamp L vi mch khuch i, ni galvanic, x l t/h t 0Hz. Tn hiu gm: 2 chn tn hiu Inv. Inp v Non Inv. Input Chn Output Ngun cp: +Vcc, -Vcc( Gnd) Chnh Offset. C th c thm chn ni t b tn s

Hnh 6.05a. Analog Comparator

Hnh 6.05b

Hnh 6.05c

Hnh 6.05d

H603. Operational Amplifier (OpAmp) c im opamp X l tn hiu dc (0 Hz up) H s khuch i ln, t kilo... Mega... and even more... (GBW - Gain - band width Product, unit @ MHz) Tr vo ln vi k n 1012 , tr ra nh, 10s n 100s, tt cho cc mch ghp ni analog, phi hp tr khng.

Hnh 6.05e

Hnh 6.05f

Hnh 6.04. Thit b 2 'ca' Ngun cp di rng, 1 hoc 2 du: 3Vdc to 18Vdc Khuch Vi sai (Differential Amplifier), loi tr nhiu tt => CMRR (Common Mode Rejection Ratio h s kh nhiu ng pha ln) up to 120dB Band width/ Slew rate: Bng thng/ Tc tng in p ti a pha Output khi ca vo c bc nhy n v UOffset: Khi ca vo =0 m ca ra khc 0. in p tri theo thi gian v nhit => chnh Uoffset/ bias current ICs: Linear Monolithic: A741 (Fair Child), LM124s...(NS) Linear FET: TL 081/ 082/ 084 (TI), LF356/357/347..(NS) Linear Hybrid:LH0024/ 0032 (NS-Hi Slewrate) Instrumentation OpAmp: LM725/ LH0036/ 0038/ 0084 (NS)

Hnh 6.05g. Instrumentation Ampl.

Hnh 6.05h

Hnh 6.05i

Hnh 6.05j

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Hnh 6.05k

Hnh 6.05l. Mch lp li tn hiu

Hnh 6.05n. I/ U Converter - ghp ni DAC out 6.2.2. Analog switches & multiplexers: a. Switches Dng cp transistor FET b knh p v knh n => dn dng AC R(on) t 100 .. 1.5 k Off channel Leakage Current: 100 pA .. 1 nA => Khng dng kha tn hiu p qu thp Bin tn hiu: Vss<Us<Vdd Tn s ON/OFF : ..GHz ICs: CD 4052/ 53, LF11331

Tn s tn hiu : ... MHzGHz Dng in nh, c A => thng dng mch follower loi tr Ron ICs: CD 4051, 74HC4051 (TI), DG508A, 509A (Maxim) 6.2.3. Voltage reference - Uref L cc vi mch (super zener) to ra cc in p c n nh cao theo thi gian v theo nhit mi trng Gi tr in p theo thp phn (5/ 10,00Vdc) hay nh phn (5,12/ 10,24Vdc) H s tri: 3..5 ppm/OC Cng thc chuyn i A/D v D/A n bit: bn-12n-1 + bn-22 n-2 + ... + b12 1+b020 Uanalog = ----------------------------------------------------------- Uref (") 2n Cc vi mch: LH0070, LM199s (NS) 6.2.4. Sample & Hold (trch mu & gi) Dng trch mu ca tn hiu vo thi im c xung Sample v gi nguyn gi tr trong khong thi gian lu hn. Dng trong cc h thu thp s liu khi tc bin thin tn hiu cao (tng i) vi thi gian ADC chuyn i Thu hp ca s bt nh ca ADC - do thi gian chuyn i di (tens s - ms) thnh ca s bt nh ca S&H (tens ns..s) => nng cao chnh xc chuyn i A/D v nng cao tn s tn hiu. Thi gian trch mu: vi chc ns n vi s T gi (Chold): dng t c dng r rt nh Tc st p: mV/s, tu thuc t Guard Ring: k thut ch to mch gim thiu dng r

Hnh 6.06. Symbol of Analog SPDT switch Hnh 6.08. Synbolic Sample & Hold ICs: LF189s (NS); AD585 (Analog Device Inc.)

Hnh 6.07. Functional Block Diagram Analog MUX 6.2.2. Analog switch & multiplexer: b.MUX 2n switches ni chung 1 cc n bit chn knh => 2 n knh, 1 trong s 2 n knh c chn trong 1 thi im. Chc nng MUX v DeMUX C tn hiu Inhibit - cm tt c cc knh Bin tn hiu: Vss <U(s) < Vdd , Ch hin tng 'xuyn knh' (Cross-talk)
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Hnh 6.09. Biu chuyn i tn hiu w/o [w] S&H C tn hiu u(t). nh: im t1 => mu A1; t2 => mu A2... khi khi phc li s c ng cong gn ng vi ng ban u, ty thuc vo dy ca mu. Thc t: t1 => start ADC, t1+ c tn hiu EOC => mu thu c A*1 t2 => start ... mu A*2 ... khi khi phc c ng cong khc. Tc tn hiu bin thin cng ln => sai s Dng S&H:
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t1=> sample - start ADC, t2 => sample - start ADC...

Hnh 6.10. Tnh tn s hnh sin vi DAC 574 Case study: u(t)= 5+5*sin(t+) (V). ADC 12bit, 35s converssion time, U(ref) = 10,24V. Sai s lng t = 1/2 ULSB . Hi tn s tn hiu max - khng sai trong 2 trng hp w - w/o S&H. Sample time=100ns 6.2.5. Cc sai s chuyn i Sai s lng t: Sai s cng tnh - zero => chit p/ software, first Sai s nhn tnh - gain => chit p/ software Ngun chun Uref Cc mch khuch a, span, Full scale... Tn hiu bin thin nhanh Tn s ly mu chm. Ref K thut o lng - Prof. Dr. Phm Thng Hn

Hnh 6.20. Dual Slope Integration ADC

Hnh 6.21. Interfacing to the ICL - 7135 ADC Hnh 6.15. DAC Symbolic Diagram

Hnh 6.16. R-2R ladder DAC with I/U converter

Hnh 6.17. Interfacing to DAC Hnh 6.22. Nguyn l cu trc v hot ng ca SA ADC

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Chng 7. Micro controllers


7.1. Khi nim:8/ 16/ 32 bit 7.2. Multi Purpose ~ : Intel 8051, 80196 & Clones: Flash/EPROM, Data RAM, DI, DO, AI, AO, Serial (RS232), Timer/ Counter, RTC, WDT, EEROM, CMOS RAM, ISP/Jtag ... Motorola 68HC11 Families BASIC 386 EX 7.3. Special ~ : RISC: Atmel AVR-90 S 8535 Family, Mega AVR, Micro Chip PIC Family. DSP: Texas Instrument TMS 32 F 240

Ch 8. Device drivers (DD)


8.1. Khi nim: MSDN, A Little Device Driver Writer, cc m hnh I/O ca Microsoft 8.2. PC Layers: Next Page 8.3. DOS Device Drivers: BIOS, DOS Functions Writing DOS DD 8.4. Windows DD: MSDN: DLLs for Beginners DRV, DLL, DCU, VxD System's Win32 APIs & SPIs 8.2. PC Layers

Hnh 6.23. Interfacing to the ADC 0809 ns.com/product/interface/ad-da national semiconductor

Hnh 8.01. PC Layers (Courtesy IBM PC Institute) Hnh 6.24. Multi IO card: DI/ DO/ AI/ AO

Hnh 8.02. Key Code Queue

Kt thc mn hc
n mn hc/ Bi tp ln: Bt buc. C nhn, nhm n 3 ngi Hnh thc Bo co: khng qu 15 trang A4, tr dch ti liu, font ARIAL, khng cn ng ba nilon (gim nhim mt) Nu c sn phm => ng k lch demo Np trc khi thi, b/ v trc and/or sau thi Bi thi: Ch dng giy A4, vit 01 mt, ghim li v ghi s t. Khng vit nhiu li, khng chp u bi Trnh by: visual, flow chart; sch, k/h + 1 im Kt qu: Auto Answering, after 19h, tone dialling, 8696125/ 8683590

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