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Atchyuth Sonti

Main program for the Entire CARRY SAVE ADDER

entity carrysaveadder2 is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end carrysaveadder2;

architecture structural of carrysaveadder2 is

component fulladder is Port( a,b,cin:in std_logic; sum,carry:out std_logic);

end component;

component mux is Port( p,q,s: in std_logic; r:out std_logic); end component;

signal l,m,c:std_logic_vector (1 downto 0); signal tl,tm:std_logic_vector (1 downto 0); signal i,j,k:std_logic;

begin --'i' is the carry 0 for parellel fulladder set 0. --'j' is the carry 1 for parellel fulladder set 1. --'k' is the carry for the entire adder at the first full adder. i<='0'; j<='1'; k<='0';

--tl and tm are set of inputs to the multplexer out of which any one wiil be chosen depending upon the carry c(1). --l and m are set of carrry`s which will be driving the set of parellel set of full adders. --l(1) and m(1) are the carrys that are generated by the set of parellel adders here any one of them is chosen by the carry c(1). --the selection line for the mux is carry emerging from the second full adder c(1).

f1: fulladder port map(a(0),b(0),k,s(0),c(0)); f2: fulladder port map(a(1),b(1),c(0),s(1),c(1));

f3a: fulladder port map(a(2),b(2),i,tl(0),l(0)); f4a: fulladder port map(a(2),b(2),l(0),tl(1),l(1)); f3b: fulladder port map(a(2),b(2),j,tm(0),m(0)); f4b: fulladder port map(a(2),b(2),m(0),tm(1),m(1)); m1 : mux port map(tl(0),tm(0),c(1),s(2)); m2 : mux port map(tl(1),tm(1),c(1),s(3)); m3 : mux port map(l(1),m(1),c(1),cout);

end structural;

Sub program for the Full adder circuit.
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end fulladder;

architecture dataflow of fulladder is

begin sum<=a xor b xor cin; carry<=(a and b) or (b and cin) or (cin and a); end dataflow;

Sub Program for the MULTIPLEXER
library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity mux is Port ( p : in STD_LOGIC; q : in STD_LOGIC; s : in STD_LOGIC; r : out STD_LOGIC); end mux;

architecture Behavioral of mux is begin process(s) begin if (s='0') then r<=p; else r<=q; end if; end process; end Behavioral;

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