Version 3.

2
11/9/2010

NVIDIA CUDA™
NVIDIA CUDA C
Programming Guide






ii CUDA C Programming Guide Version 3.2

Changes from Version 3.1.1
 Simplified all the code samples that use cuParamSetv() to set a kernel
parameter of type CUdeviceptr since CUdeviceptr is now of same size and
alignment as void*, so there is no longer any need to go through an
interneditate void* variable.
 Added Section 3.2.4.1.4 on 16-bit floating-point textures.
 Added Section 3.2.4.4 on read/write coherency for texture and surface memory.
 Added more details about surface memory access to Section 3.2.4.2.
 Added more details to Section 3.2.6.5.
 Mentioned new stream synchronization function cudaStreamSynchronize()
in Section 3.2.6.5.2.
 Mentioned in Sections 3.2.7.2, 3.3.10.2, and 4.3 the new API calls to deal with
devices using NVIDIA SLI in AFR mode.
 Added Sections 3.2.9 and 3.3.12 about the call stack.
 Changed the type of the pitch variable in the second code sample of
Section 3.3.4 from unsigned int to size_t following the function
signature change of cuMemAllocPitch().
 Changed the type of the bytes variable in the last code sample of Section 3.3.4
from unsigned int to size_t following the function signature change of
cuModuleGetGlobal().
 Removed cuParamSetTexRef() from Section 3.3.7 as it is no longer
necessary.
 Updated Section 5.2.3, Table 5-1, and Section G.4.1 for devices of compute
capability 2.1.
 Added GeForce GTX 480M, GeForce GTX 470M, GeForce GTX 460M,
GeForce GTX 445M, GeForce GTX 435M, GeForce GTX 425M,
GeForce GTX 420M, GeForce GTX 415M, GeForce GTX 460,
GeForce GTS 450, GeForce GTX 465, GeForce GTX 580, Quadro 2000,
Quadro 600, Quadro 4000, Quadro 5000, Quadro 5000M, and Quadro 6000 to
Table A-1.
 Fixed sample code in Section B.2.3: array[] was declared as an array of char
causing a compiler error (“Unaligned memory accesses not supported”) when
casting array to a pointer of higher alignment requirement; declaring
array[] as an array of float fixes it.
 Mentioned in Section B.11 that any atomic operation can be implemented based
on atomic Compare And Swap.
 Added Section B.15 on the new malloc() and free() device functions.
 Moved the type casting functions to a separate section C.2.4.
 Fixed the maximum height of a 2D texture reference for devices of compute
capability 2.x (65535 instead of 65536) in Section G.1.



CUDA C Programming Guide Version 3.2 iii

 Fixed the maximum dimensions for surface references in Section G.1.
 Mentioned the new
cudaThreadSetCacheConfig()/cuCtxSetCacheConfig() API calls in
Section G.4.1.
 Mentioned in Section G.4.2 that global memory accesses that are cached in L2
only are serviced with 32-byte memory transactions.



iv CUDA C Programming Guide Version 3.2

Table of Contents
Chapter 1. Introduction ................................................................................... 1
1.1 From Graphics Processing to General-Purpose Parallel Computing ................... 1
1.2 CUDA™: a General-Purpose Parallel Computing Architecture .......................... 3
1.3 A Scalable Programming Model .................................................................... 4
1.4 Document’s Structure ................................................................................. 6
Chapter 2. Programming Model ....................................................................... 7
2.1 Kernels ...................................................................................................... 7
2.2 Thread Hierarchy ........................................................................................ 8
2.3 Memory Hierarchy .................................................................................... 10
2.4 Heterogeneous Programming .................................................................... 11
2.5 Compute Capability ................................................................................... 14
Chapter 3. Programming Interface ................................................................ 15
3.1 Compilation with NVCC ............................................................................. 15
3.1.1 Compilation Workflow ......................................................................... 16
3.1.2 Binary Compatibility ........................................................................... 16
3.1.3 PTX Compatibility ............................................................................... 16
3.1.4 Application Compatibility ..................................................................... 17
3.1.5 C/C++ Compatibility .......................................................................... 18
3.1.6 64-Bit Compatibility ............................................................................ 18
3.2 CUDA C ................................................................................................... 18
3.2.1 Device Memory .................................................................................. 19
3.2.2 Shared Memory ................................................................................. 21
3.2.3 Multiple Devices ................................................................................. 28
3.2.4 Texture and Surface Memory .............................................................. 29
3.2.4.1 Texture Memory .......................................................................... 29
3.2.4.2 Surface Memory .......................................................................... 34
3.2.4.3 CUDA Arrays ............................................................................... 36
3.2.4.4 Read/Write Coherency ................................................................. 36



CUDA C Programming Guide Version 3.2 v

3.2.5 Page-Locked Host Memory .................................................................. 36
3.2.5.1 Portable Memory ......................................................................... 37
3.2.5.2 Write-Combining Memory ............................................................. 37
3.2.5.3 Mapped Memory .......................................................................... 37
3.2.6 Asynchronous Concurrent Execution .................................................... 38
3.2.6.1 Concurrent Execution between Host and Device ............................. 38
3.2.6.2 Overlap of Data Transfer and Kernel Execution .............................. 38
3.2.6.3 Concurrent Kernel Execution ........................................................ 38
3.2.6.4 Concurrent Data Transfers ........................................................... 39
3.2.6.5 Stream ....................................................................................... 39
3.2.6.6 Event ......................................................................................... 41
3.2.6.7 Synchronous Calls ....................................................................... 42
3.2.7 Graphics Interoperability ..................................................................... 42
3.2.7.1 OpenGL Interoperability ............................................................... 43
3.2.7.2 Direct3D Interoperability .............................................................. 45
3.2.8 Error Handling ................................................................................... 51
3.2.9 Call Stack .......................................................................................... 52
3.3 Driver API ................................................................................................ 52
3.3.1 Context ............................................................................................. 54
3.3.2 Module .............................................................................................. 55
3.3.3 Kernel Execution ................................................................................ 56
3.3.4 Device Memory .................................................................................. 58
3.3.5 Shared Memory ................................................................................. 61
3.3.6 Multiple Devices ................................................................................. 62
3.3.7 Texture and Surface Memory .............................................................. 62
3.3.7.1 Texture Memory .......................................................................... 62
3.3.7.2 Surface Memory .......................................................................... 64
3.3.8 Page-Locked Host Memory .................................................................. 65
3.3.9 Asynchronous Concurrent Execution .................................................... 66
3.3.9.1 Stream ....................................................................................... 66
3.3.9.2 Event Management ...................................................................... 67
3.3.9.3 Synchronous Calls ....................................................................... 67
3.3.10 Graphics Interoperability ..................................................................... 67



vi CUDA C Programming Guide Version 3.2

3.3.10.1 OpenGL Interoperability ............................................................... 68
3.3.10.2 Direct3D Interoperability .............................................................. 70
3.3.11 Error Handling ................................................................................... 77
3.3.12 Call Stack .......................................................................................... 77
3.4 Interoperability between Runtime and Driver APIs ....................................... 77
3.5 Versioning and Compatibility...................................................................... 78
3.6 Compute Modes ....................................................................................... 79
3.7 Mode Switches ......................................................................................... 79
Chapter 4. Hardware Implementation ........................................................... 81
4.1 SIMT Architecture ..................................................................................... 81
4.2 Hardware Multithreading ........................................................................... 82
4.3 Multiple Devices ....................................................................................... 83
Chapter 5. Performance Guidelines ............................................................... 85
5.1 Overall Performance Optimization Strategies ............................................... 85
5.2 Maximize Utilization .................................................................................. 85
5.2.1 Application Level ................................................................................ 85
5.2.2 Device Level ...................................................................................... 86
5.2.3 Multiprocessor Level ........................................................................... 86
5.3 Maximize Memory Throughput ................................................................... 88
5.3.1 Data Transfer between Host and Device .............................................. 89
5.3.2 Device Memory Accesses .................................................................... 89
5.3.2.1 Global Memory ............................................................................ 90
5.3.2.2 Local Memory .............................................................................. 91
5.3.2.3 Shared Memory ........................................................................... 92
5.3.2.4 Constant Memory ........................................................................ 92
5.3.2.5 Texture and Surface Memory ........................................................ 93
5.4 Maximize Instruction Throughput ............................................................... 93
5.4.1 Arithmetic Instructions ....................................................................... 94
5.4.2 Control Flow Instructions .................................................................... 96
5.4.3 Synchronization Instruction ................................................................. 97
Appendix A. CUDA-Enabled GPUs .................................................................. 99
Appendix B. C Language Extensions ............................................................ 103
B.1 Function Type Qualifiers .......................................................................... 103



CUDA C Programming Guide Version 3.2 vii

B.1.1 __device__ ...................................................................................... 103
B.1.2 __global__ ...................................................................................... 103
B.1.3 __host__ ......................................................................................... 103
B.1.4 Restrictions ..................................................................................... 104
B.1.4.1 Functions Parameters ................................................................ 104
B.1.4.2 Variadic Functions ..................................................................... 104
B.1.4.3 Static Variables ......................................................................... 104
B.1.4.4 Function Pointers ....................................................................... 104
B.1.4.5 Recursion ................................................................................. 104
B.2 Variable Type Qualifiers .......................................................................... 105
B.2.1 __device__ ...................................................................................... 105
B.2.2 __constant__ ................................................................................... 105
B.2.3 __shared__ ..................................................................................... 105
B.2.4 Restrictions ..................................................................................... 106
B.2.4.1 Storage and Scope .................................................................... 106
B.2.4.2 Assignment ............................................................................... 106
B.2.4.3 Automatic Variable .................................................................... 106
B.2.4.4 Pointers .................................................................................... 107
B.2.5 volatile ............................................................................................ 107
B.3 Built-in Vector Types ............................................................................... 108
B.3.1 char1, uchar1, char2, uchar2, char3, uchar3, char4, uchar4, short1,
ushort1, short2, ushort2, short3, ushort3, short4, ushort4, int1, uint1, int2, uint2,
int3, uint3, int4, uint4, long1, ulong1, long2, ulong2, long3, ulong3, long4, ulong4,
longlong1, ulonglong1, longlong2, ulonglong2, float1, float2, float3, float4, double1,
double2 108
B.3.2 dim3 ............................................................................................... 109
B.4 Built-in Variables .................................................................................... 109
B.4.1 gridDim ........................................................................................... 109
B.4.2 blockIdx .......................................................................................... 109
B.4.3 blockDim ......................................................................................... 109
B.4.4 threadIdx ........................................................................................ 109
B.4.5 warpSize ......................................................................................... 110
B.4.6 Restrictions ..................................................................................... 110
B.5 Memory Fence Functions ......................................................................... 110



viii CUDA C Programming Guide Version 3.2

B.6 Synchronization Functions ....................................................................... 111
B.7 Mathematical Functions ........................................................................... 112
B.8 Texture Functions ................................................................................... 113
B.8.1 tex1Dfetch() .................................................................................... 113
B.8.2 tex1D() ........................................................................................... 114
B.8.3 tex2D() ........................................................................................... 114
B.8.4 tex3D() ........................................................................................... 114
B.9 Surface Functions ................................................................................... 114
B.9.1 surf1Dread() .................................................................................... 115
B.9.2 surf1Dwrite() ................................................................................... 115
B.9.3 surf2Dread() .................................................................................... 115
B.9.4 surf2Dwrite() ................................................................................... 115
B.10 Time Function ........................................................................................ 115
B.11 Atomic Functions .................................................................................... 116
B.11.1 Arithmetic Functions ......................................................................... 116
B.11.1.1 atomicAdd() .............................................................................. 116
B.11.1.2 atomicSub() .............................................................................. 117
B.11.1.3 atomicExch() ............................................................................. 117
B.11.1.4 atomicMin() .............................................................................. 117
B.11.1.5 atomicMax() .............................................................................. 117
B.11.1.6 atomicInc() ............................................................................... 117
B.11.1.7 atomicDec() .............................................................................. 118
B.11.1.8 atomicCAS() .............................................................................. 118
B.11.2 Bitwise Functions ............................................................................. 118
B.11.2.1 atomicAnd() .............................................................................. 118
B.11.2.2 atomicOr() ................................................................................ 118
B.11.2.3 atomicXor() ............................................................................... 118
B.12 Warp Vote Functions ............................................................................... 119
B.13 Profiler Counter Function ......................................................................... 119
B.14 Formatted Output ................................................................................... 119
B.14.1 Format Specifiers ............................................................................. 120
B.14.2 Limitations ...................................................................................... 120
B.14.3 Associated Host-Side API .................................................................. 121



CUDA C Programming Guide Version 3.2 ix

B.14.4 Examples ........................................................................................ 121
B.15 Dynamic Global Memory Allocation ........................................................... 122
B.15.1 Heap Memory Allocation ................................................................... 123
B.15.2 Interoperability with Host Memory API ............................................... 123
B.15.3 Examples ........................................................................................ 123
B.15.3.1 Per Thread Allocation ................................................................. 123
B.15.3.2 Per Thread Block Allocation ........................................................ 124
B.15.3.3 Allocation Persisting Between Kernel Launches ............................. 125
B.16 Execution Configuration .......................................................................... 126
B.17 Launch Bounds ....................................................................................... 127
Appendix C. Mathematical Functions ........................................................... 129
C.1 Standard Functions ................................................................................. 129
C.1.1 Single-Precision Floating-Point Functions ............................................ 129
C.1.2 Double-Precision Floating-Point Functions .......................................... 132
C.1.3 Integer Functions ............................................................................. 134
C.2 Intrinsic Functions .................................................................................. 134
C.2.1 Single-Precision Floating-Point Functions ............................................ 134
C.2.2 Double-Precision Floating-Point Functions .......................................... 136
C.2.3 Integer Functions ............................................................................. 136
C.2.4 Type Casting Functions ..................................................................... 137
Appendix D. C++ Language Constructs ....................................................... 139
D.1 Polymorphism ........................................................................................ 139
D.2 Default Parameters ................................................................................. 140
D.3 Operator Overloading.............................................................................. 140
D.4 Namespaces ........................................................................................... 141
D.5 Function Templates ................................................................................ 141
D.6 Classes .................................................................................................. 142
D.6.1 Example 1 Pixel Data Type................................................................ 142
D.6.2 Example 2 Functor Class ................................................................... 143
Appendix E. NVCC Specifics ......................................................................... 145
E.1 __noinline__ and __forceinline__ ............................................................. 145
E.2 #pragma unroll ...................................................................................... 145
E.3 __restrict__ ........................................................................................... 146



x CUDA C Programming Guide Version 3.2

Appendix F. Texture Fetching ...................................................................... 149
F.1 Nearest-Point Sampling ........................................................................... 150
F.2 Linear Filtering ....................................................................................... 150
F.3 Table Lookup ......................................................................................... 152
Appendix G. Compute Capabilities ............................................................... 153
G.1 Features and Technical Specifications ....................................................... 154
G.2 Floating-Point Standard ........................................................................... 155
G.3 Compute Capability 1.x ........................................................................... 157
G.3.1 Architecture ..................................................................................... 157
G.3.2 Global Memory ................................................................................ 158
G.3.2.1 Devices of Compute Capability 1.0 and 1.1 .................................. 158
G.3.2.2 Devices of Compute Capability 1.2 and 1.3 .................................. 158
G.3.3 Shared Memory ............................................................................... 159
G.3.3.1 32-Bit Strided Access ................................................................. 159
G.3.3.2 32-Bit Broadcast Access ............................................................. 160
G.3.3.3 8-Bit and 16-Bit Access .............................................................. 160
G.3.3.4 Larger Than 32-Bit Access .......................................................... 160
G.4 Compute Capability 2.x ........................................................................... 161
G.4.1 Architecture ..................................................................................... 161
G.4.2 Global Memory ................................................................................ 163
G.4.3 Shared Memory ............................................................................... 165
G.4.3.1 32-Bit Strided Access ................................................................. 165
G.4.3.2 Larger Than 32-Bit Access .......................................................... 165
G.4.4 Constant Memory ............................................................................. 166




CUDA C Programming Guide Version 3.2 xi

List of Figures
Figure 1-1. Floating-Point Operations per Second and Memory Bandwidth for the CPU
and GPU 2
Figure 1-2. The GPU Devotes More Transistors to Data Processing ............................ 3
Figure 1-3. CUDA is Designed to Support Various Languages or Application
Programming Interfaces .................................................................................... 4
Figure 1-4. Automatic Scalability ............................................................................ 5
Figure 2-1. Grid of Thread Blocks ........................................................................... 9
Figure 2-2. Memory Hierarchy .............................................................................. 11
Figure 2-3. Heterogeneous Programming .............................................................. 13
Figure 3-1. Matrix Multiplication without Shared Memory ........................................ 24
Figure 3-2. Matrix Multiplication with Shared Memory ............................................ 28
Figure 3-3. Library Context Management .............................................................. 55
Figure 3-4. The Driver API is Backward, but Not Forward Compatible ...................... 79

Figure F-1. Nearest-Point Sampling of a One-Dimensional Texture of Four Texels .. 150
Figure F-2. Linear Filtering of a One-Dimensional Texture of Four Texels in Clamp
Addressing Mode ........................................................................................... 151
Figure F-3. One-Dimensional Table Lookup Using Linear Filtering .......................... 152
Figure G-1. Examples of Global Memory Accesses by a Warp, 4-Byte Word per Thread,
and Associated Memory Transactions Based on Compute Capability .................. 164
Figure G-2 Examples of Strided Shared Memory Accesses for Devices of Compute
Capability 2.x ................................................................................................ 167
Figure G-3 Examples of Irregular and Colliding Shared Memory Accesses for Devices
of Compute Capability 2.x .............................................................................. 169







CUDA C Programming Guide Version 3.1 1

Chapter 1.
Introduction
1.1 From Graphics Processing to
General-Purpose Parallel Computing
Driven by the insatiable market demand for realtime, high-definition 3D graphics,
the programmable Graphic Processor Unit or GPU has evolved into a highly
parallel, multithreaded, manycore processor with tremendous computational
horsepower and very high memory bandwidth, as illustrated by Figure 1-1.
Chapter 1. Introduction


2 CUDA C Programming Guide Version 3.2


Figure 1-1. Floating-Point Operations per Second and
Memory Bandwidth for the CPU and GPU
Chapter 1. Introduction


CUDA C Programming Guide Version 3.2 3


The reason behind the discrepancy in floating-point capability between the CPU and
the GPU is that the GPU is specialized for compute-intensive, highly parallel
computation – exactly what graphics rendering is about – and therefore designed
such that more transistors are devoted to data processing rather than data caching
and flow control, as schematically illustrated by Figure 1-2.


Figure 1-2. The GPU Devotes More Transistors to Data
Processing

More specifically, the GPU is especially well-suited to address problems that can be
expressed as data-parallel computations – the same program is executed on many
data elements in parallel – with high arithmetic intensity – the ratio of arithmetic
operations to memory operations. Because the same program is executed for each
data element, there is a lower requirement for sophisticated flow control, and
because it is executed on many data elements and has high arithmetic intensity, the
memory access latency can be hidden with calculations instead of big data caches.
Data-parallel processing maps data elements to parallel processing threads. Many
applications that process large data sets can use a data-parallel programming model
to speed up the computations. In 3D rendering, large sets of pixels and vertices are
mapped to parallel threads. Similarly, image and media processing applications such
as post-processing of rendered images, video encoding and decoding, image scaling,
stereo vision, and pattern recognition can map image blocks and pixels to parallel
processing threads. In fact, many algorithms outside the field of image rendering
and processing are accelerated by data-parallel processing, from general signal
processing or physics simulation to computational finance or computational biology.
1.2 CUDA™: a General-Purpose Parallel
Computing Architecture
In November 2006, NVIDIA introduced CUDA™, a general purpose parallel
computing architecture – with a new parallel programming model and instruction
set architecture – that leverages the parallel compute engine in NVIDIA GPUs to
Cache
ALU
Control
ALU
ALU
ALU
DRAM
CPU
DRAM








GPU
Chapter 1. Introduction


4 CUDA C Programming Guide Version 3.2

solve many complex computational problems in a more efficient way than on a
CPU.
CUDA comes with a software environment that allows developers to use C as a
high-level programming language. As illustrated by Figure 1-3, other languages or
application programming interfaces are supported, such as CUDA FORTRAN,
OpenCL, and DirectCompute.

Figure 1-3. CUDA is Designed to Support Various Languages
or Application Programming Interfaces
1.3 A Scalable Programming Model
The advent of multicore CPUs and manycore GPUs means that mainstream
processor chips are now parallel systems. Furthermore, their parallelism continues
to scale with Moore‟s law. The challenge is to develop application software that
transparently scales its parallelism to leverage the increasing number of processor
cores, much as 3D graphics applications transparently scale their parallelism to
manycore GPUs with widely varying numbers of cores.
The CUDA parallel programming model is designed to overcome this challenge
while maintaining a low learning curve for programmers familiar with standard
programming languages such as C.
At its core are three key abstractions – a hierarchy of thread groups, shared
memories, and barrier synchronization – that are simply exposed to the programmer
as a minimal set of language extensions.
These abstractions provide fine-grained data parallelism and thread parallelism,
nested within coarse-grained data parallelism and task parallelism. They guide the
programmer to partition the problem into coarse sub-problems that can be solved
independently in parallel by blocks of threads, and each sub-problem into finer
pieces that can be solved cooperatively in parallel by all threads within the block.
This decomposition preserves language expressivity by allowing threads to
Chapter 1. Introduction


CUDA C Programming Guide Version 3.2 5

cooperate when solving each sub-problem, and at the same time enables automatic
scalability. Indeed, each block of threads can be scheduled on any of the available
processor cores, in any order, concurrently or sequentially, so that a compiled
CUDA program can execute on any number of processor cores as illustrated by
Figure 1-4, and only the runtime system needs to know the physical processor
count.
This scalable programming model allows the CUDA architecture to span a wide
market range by simply scaling the number of processors and memory partitions:
from the high-performance enthusiast GeForce GPUs and professional Quadro and
Tesla computing products to a variety of inexpensive, mainstream GeForce GPUs
(see Appendix A for a list of all CUDA-enabled GPUs).


A multithreaded program is partitioned into blocks of threads that execute independently from each
other, so that a GPU with more cores will automatically execute the program in less time than a GPU
with fewer cores.
Figure 1-4. Automatic Scalability

GPU with 2 Cores

Core 1 Core 0
GPU with 4 Cores

Core 1 Core 0 Core 3 Core 2
Block 5 Block 6
Multithreaded CUDA Program
Block 0 Block 1 Block 2 Block 3
Block 4 Block 5 Block 6 Block 7

Block 1 Block 0

Block 3 Block 2

Block 5 Block 4

Block 7 Block 6

Block 0 Block 1 Block 2 Block 3

Block 4 Block 5 Block 6 Block 7
Chapter 1. Introduction


6 CUDA C Programming Guide Version 3.2

1.4 Document’s Structure
This document is organized into the following chapters:
 Chapter 1 is a general introduction to CUDA.
 Chapter 2 outlines the CUDA programming model.
 Chapter 3 describes the programming interface.
 Chapter 4 describes the hardware implementation.
 Chapter 5 gives some guidance on how to achieve maximum performance.
 Appendix A lists all CUDA-enabled devices.
 Appendix B is a detailed description of all extensions to the C language.
 Appendix C lists the mathematical functions supported in CUDA.
 Appendix D lists the C++ constructs supported in device code.
 Appendix E lists the specific keywords and directives supported by nvcc.
 Appendix F gives more details on texture fetching.
 Appendix G gives the technical specifications of various devices, as well as
more architectural details.







CUDA C Programming Guide Version 3.1 7

Chapter 2.
Programming Model
This chapter introduces the main concepts behind the CUDA programming model
by outlining how they are exposed in C. An extensive description of CUDA C is
given in Section 3.2.
Full code for the vector addition example used in this chapter and the next can be
found in the vectorAdd SDK code sample.
2.1 Kernels
CUDA C extends C by allowing the programmer to define C functions, called
kernels, that, when called, are executed N times in parallel by N different CUDA
threads, as opposed to only once like regular C functions.
A kernel is defined using the __global__ declaration specifier and the number of
CUDA threads that execute that kernel for a given kernel call is specified using a
new <<<…>>> execution configuration syntax (see Appendix B.16). Each thread that
executes the kernel is given a unique thread ID that is accessible within the kernel
through the built-in threadIdx variable.
As an illustration, the following sample code adds two vectors A and B of size N
and stores the result into vector C:
// Kernel definition
__global__ void VecAdd(float* A, float* B, float* C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}

int main()
{
...
// Kernel invocation with N threads
VecAdd<<<1, N>>>(A, B, C);
}
Here, each of the N threads that execute VecAdd() performs one pair-wise
addition.
Chapter 2. Programming Model


8 CUDA C Programming Guide Version 3.2

2.2 Thread Hierarchy
For convenience, threadIdx is a 3-component vector, so that threads can be
identified using a one-dimensional, two-dimensional, or three-dimensional thread
index, forming a one-dimensional, two-dimensional, or three-dimensional thread
block. This provides a natural way to invoke computation across the elements in a
domain such as a vector, matrix, or volume.
The index of a thread and its thread ID relate to each other in a straightforward
way: For a one-dimensional block, they are the same; for a two-dimensional block
of size (Dx, Dy), the thread ID of a thread of index (x, y) is (x + y Dx); for a three-
dimensional block of size (Dx, Dy, Dz), the thread ID of a thread of index (x, y, z) is
(x + y Dx + z Dx Dy).
As an example, the following code adds two matrices A and B of size NxN and
stores the result into matrix C:
// Kernel definition
__global__ void MatAdd(float A[N][N], float B[N][N],
float C[N][N])
{
int i = threadIdx.x;
int j = threadIdx.y;
C[i][j] = A[i][j] + B[i][j];
}

int main()
{
...
// Kernel invocation with one block of N * N * 1 threads
int numBlocks = 1;
dim3 threadsPerBlock(N, N);
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
}
There is a limit to the number of threads per block, since all threads of a block are
expected to reside on the same processor core and must share the limited memory
resources of that core. On current GPUs, a thread block may contain up to 1024
threads.
However, a kernel can be executed by multiple equally-shaped thread blocks, so that
the total number of threads is equal to the number of threads per block times the
number of blocks.
Blocks are organized into a one-dimensional or two-dimensional grid of thread
blocks as illustrated by Figure 2-1. The number of thread blocks in a grid is usually
dictated by the size of the data being processed or the number of processors in the
system, which it can greatly exceed.

Chapter 2: Programming Model


CUDA C Programming Guide Version 3.2 9


Figure 2-1. Grid of Thread Blocks

The number of threads per block and the number of blocks per grid specified in the
<<<…>>> syntax can be of type int or dim3. Two-dimensional blocks or grids can
be specified as in the example above.
Each block within the grid can be identified by a one-dimensional or two-
dimensional index accessible within the kernel through the built-in blockIdx
variable. The dimension of the thread block is accessible within the kernel through
the built-in blockDim variable.
Extending the previous MatAdd() example to handle multiple blocks, the code
becomes as follows.
// Kernel definition
__global__ void MatAdd(float A[N][N], float B[N][N],
float C[N][N])
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
if (i < N && j < N)
C[i][j] = A[i][j] + B[i][j];
Grid
Block (1, 1)
Thread (0, 0) Thread (1, 0) Thread (2, 0) Thread (3, 0)
Thread (0, 1) Thread (1, 1) Thread (2, 1) Thread (3, 1)
Thread (0, 2) Thread (1, 2) Thread (2, 2) Thread (3, 2)
Block (2, 1) Block (1, 1) Block (0, 1)
Block (2, 0) Block (1, 0) Block (0, 0)
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10 CUDA C Programming Guide Version 3.2

}

int main()
{
...
// Kernel invocation
dim3 threadsPerBlock(16, 16);
dim3 numBlocks(N / threadsPerBlock.x, N / threadsPerBlock.y);
MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C);
}
A thread block size of 16x16 (256 threads), although arbitrary in this case, is a
common choice. The grid is created with enough blocks to have one thread per
matrix element as before. For simplicity, this example assumes that the number of
threads per grid in each dimension is evenly divisible by the number of threads per
block in that dimension, although that need not be the case.
Thread blocks are required to execute independently: It must be possible to execute
them in any order, in parallel or in series. This independence requirement allows
thread blocks to be scheduled in any order across any number of cores as illustrated
by Figure 1-4, enabling programmers to write code that scales with the number of
cores.
Threads within a block can cooperate by sharing data through some shared memory
and by synchronizing their execution to coordinate memory accesses. More
precisely, one can specify synchronization points in the kernel by calling the
__syncthreads() intrinsic function; __syncthreads() acts as a barrier at
which all threads in the block must wait before any is allowed to proceed.
Section 3.2.2 gives an example of using shared memory.
For efficient cooperation, the shared memory is expected to be a low-latency
memory near each processor core (much like an L1 cache) and __syncthreads()
is expected to be lightweight.
2.3 Memory Hierarchy
CUDA threads may access data from multiple memory spaces during their
execution as illustrated by Figure 2-2. Each thread has private local memory. Each
thread block has shared memory visible to all threads of the block and with the
same lifetime as the block. All threads have access to the same global memory.
There are also two additional read-only memory spaces accessible by all threads: the
constant and texture memory spaces. The global, constant, and texture memory
spaces are optimized for different memory usages (see Sections 5.3.2.1, 5.3.2.4, and
5.3.2.5). Texture memory also offers different addressing modes, as well as data
filtering, for some specific data formats (see Section 3.2.4).
The global, constant, and texture memory spaces are persistent across kernel
launches by the same application.
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CUDA C Programming Guide Version 3.2 11


Figure 2-2. Memory Hierarchy
2.4 Heterogeneous Programming
As illustrated by Figure 2-3, the CUDA programming model assumes that the
CUDA threads execute on a physically separate device that operates as a coprocessor
to the host running the C program. This is the case, for example, when the kernels
execute on a GPU and the rest of the C program executes on a CPU.














Global memory
Grid 0
Block (2, 1) Block (1, 1) Block (0, 1)
Block (2, 0) Block (1, 0) Block (0, 0)
Grid 1
Block (1, 1)
Block (1, 0)
Block (1, 2)
Block (0, 1)
Block (0, 0)
Block (0, 2)
Thread Block

Per-block shared
memory
Thread
Per-thread local
memory
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12 CUDA C Programming Guide Version 3.2

The CUDA programming model also assumes that both the host and the device
maintain their own separate memory spaces in DRAM, referred to as host memory and
device memory, respectively. Therefore, a program manages the global, constant, and
texture memory spaces visible to kernels through calls to the CUDA runtime
(described in Chapter 3). This includes device memory allocation and deallocation as
well as data transfer between host and device memory.
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CUDA C Programming Guide Version 3.2 13


Serial code executes on the host while parallel code executes on the device.
Figure 2-3. Heterogeneous Programming
Device
Grid 0
Block (2, 1) Block (1, 1) Block (0, 1)
Block (2, 0) Block (1, 0) Block (0, 0)
Host
C Program
Sequential
Execution

Serial code


Parallel kernel
Kernel0<<<>>>()








Serial code




Parallel kernel
Kernel1<<<>>>()



Host
Device
Grid 1
Block (1, 1)
Block (1, 0)
Block (1, 2)
Block (0, 1)
Block (0, 0)
Block (0, 2)
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14 CUDA C Programming Guide Version 3.2

2.5 Compute Capability
The compute capability of a device is defined by a major revision number and a minor
revision number.
Devices with the same major revision number are of the same core architecture. The
major revision number of devices based on the Fermi architecture is 2. Prior devices
are all of compute capability 1.x (Their major revision number is 1).
The minor revision number corresponds to an incremental improvement to the core
architecture, possibly including new features.
Appendix A lists of all CUDA-enabled devices along with their compute capability.
Appendix G gives the technical specifications of each compute capability.







CUDA C Programming Guide Version 3.1 15

Chapter 3.
Programming Interface
Two interfaces are currently supported to write CUDA programs: CUDA C and the
CUDA driver API. An application typically uses either one or the other, but it can
use both as described in Section 3.4.
CUDA C exposes the CUDA programming model as a minimal set of extensions to
the C language. Any source file that contains some of these extensions must be
compiled with nvcc as outlined in Section 3.1. These extensions allow
programmers to define a kernel as a C function and use some new syntax to specify
the grid and block dimension each time the function is called.
The CUDA driver API is a lower-level C API that provides functions to load
kernels as modules of CUDA binary or assembly code, to inspect their parameters,
and to launch them. Binary and assembly codes are usually obtained by compiling
kernels written in C.
CUDA C comes with a runtime API and both the runtime API and the driver API
provide functions to allocate and deallocate device memory, transfer data between
host memory and device memory, manage systems with multiple devices, etc.
The runtime API is built on top of the CUDA driver API. Initialization, context,
and module management are all implicit and resulting code is more concise.
In contrast, the CUDA driver API requires more code, is harder to program and
debug, but offers a better level of control and is language-independent since it
handles binary or assembly code.
Section 3.2 continues the description of CUDA C started in Chapter 2. It also
introduces concepts that are common to both CUDA C and the driver API: linear
memory, CUDA arrays, shared memory, texture memory, page-locked host
memory, device enumeration, asynchronous execution, interoperability with
graphics APIs. Section 3.3 assumes knowledge of these concepts and describes how
they are exposed by the driver API.
3.1 Compilation with NVCC
Kernels can be written using the CUDA instruction set architecture, called PTX,
which is described in the PTX reference manual. It is however usually more
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16 CUDA C Programming Guide Version 3.2

effective to use a high-level programming language such as C. In both cases, kernels
must be compiled into binary code by nvcc to execute on the device.
nvcc is a compiler driver that simplifies the process of compiling C or PTX code: It
provides simple and familiar command line options and executes them by invoking
the collection of tools that implement the different compilation stages. This section
gives an overview of nvcc workflow and command options. A complete
description can be found in the nvcc user manual.
3.1.1 Compilation Workflow
Source files compiled with nvcc can include a mix of host code (i.e. code that
executes on the host) and device code (i.e. code that executes on the device). nvcc‟s
basic workflow consists in separating device code from host code and compiling the
device code into an assembly form (PTX code) and/or binary form (cubin object).
The generated host code is output either as C code that is left to be compiled using
another tool or as object code directly by letting nvcc invoke the host compiler
during the last compilation stage.
Applications can then:
 Either load and execute the PTX code or cubin object on the device using the
CUDA driver API (see Section 3.3) and ignore the generated host code (if any);
 Or link to the generated host code; the generated host code includes the PTX
code and/or cubin object as a global initialized data array and a translation of the
<<<…>>> syntax introduced in Section 2.1 (and described in more details in
Section B.16) into the necessary CUDA C runtime function calls to load and
launch each compiled kernel.
Any PTX code loaded by an application at runtime is compiled further to binary
code by the device driver. This is called just-in-time compilation. Just-in-time
compilation increases application load time, but allow applications to benefit from
latest compiler improvements. It is also the only way for applications to run on
devices that did not exist at the time the application was compiled, as detailed in
Section 3.1.4.
3.1.2 Binary Compatibility
Binary code is architecture-specific. A cubin object is generated using the compiler
option –code that specifies the targeted architecture: For example, compiling with
–code=sm_13 produces binary code for devices of compute capability 1.3. Binary
compatibility is guaranteed from one minor revision to the next one, but not from
one minor revision to the previous one or across major revisions. In other words, a
cubin object generated for compute capability X.y is only guaranteed to execute on
devices of compute capability X.z where z≥y.
3.1.3 PTX Compatibility
Some PTX instructions are only supported on devices of higher compute
capabilities. For example, atomic instructions on global memory are only supported
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CUDA C Programming Guide Version 3.2 17

on devices of compute capability 1.1 and above; double-precision instructions are
only supported on devices of compute capability 1.3 and above. The –arch
compiler option specifies the compute capability that is assumed when compiling C
to PTX code. So, code that contains double-precision arithmetic, for example, must
be compiled with “-arch=sm_13” (or higher compute capability), otherwise
double-precision arithmetic will get demoted to single-precision arithmetic.
PTX code produced for some specific compute capability can always be compiled to
binary code of greater or equal compute capability.
3.1.4 Application Compatibility
To execute code on devices of specific compute capability, an application must load
binary or PTX code that is compatible with this compute capability as described in
Sections 3.1.2 and 3.1.3. In particular, to be able to execute code on future
architectures with higher compute capability – for which no binary code can be
generated yet –, an application must load PTX code that will be compiled just-in-
time for these devices.
Which PTX and binary code gets embedded in a CUDA C application is controlled
by the –arch and –code compiler options or the –gencode compiler option as
detailed in the nvcc user manual. For example,
nvcc x.cu
–gencode arch=compute_10,code=sm_10
–gencode arch=compute_11,code=\’compute_11,sm_11\’
embeds binary code compatible with compute capability 1.0 (first –gencode
option) and PTX and binary code compatible with compute capability 1.1 (second
-gencode option).
Host code is generated to automatically select at runtime the most appropriate code
to load and execute, which, in the above example, will be:
 1.0 binary code for devices with compute capability 1.0,
 1.1 binary code for devices with compute capability 1.1, 1.2, 1.3,
 binary code obtained by compiling 1.1 PTX code for devices with compute
capabilities 2.0 and higher.
x.cu can have an optimized code path that uses atomic operations, for example,
which are only supported in devices of compute capability 1.1 and higher. The
__CUDA_ARCH__ macro can be used to differentiate various code paths based on
compute capability. It is only defined for device code. When compiling with
“arch=compute_11” for example, __CUDA_ARCH__ is equal to 110.
Applications using the driver API must compile code to separate files and explicitly
load and execute the most appropriate file at runtime.
The nvcc user manual lists various shorthands for the –arch, –code, and
÷gencode compiler options. For example, “÷arch=sm_13” is a shorthand for
“÷arch=compute_13 ÷code=compute_13,sm_13” (which is the same as
“÷gencode arch=compute_13,code=\’compute_13,sm_13\’”).
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18 CUDA C Programming Guide Version 3.2

3.1.5 C/C++ Compatibility
The front end of the compiler processes CUDA source files according to C++
syntax rules. Full C++ is supported for the host code. However, only a subset of
C++ is fully supported for the device code as described in detail in Appendix D. As
a consequence of the use of C++ syntax rules, void pointers (e.g., returned by
malloc()) cannot be assigned to non-void pointers without a typecast.
nvcc also support specific keywords and directives detailed in Appendix E.
3.1.6 64-Bit Compatibility
The 64-bit version of nvcc compiles device code in 64-bit mode (i.e. pointers are
64-bit). Device code compiled in 64-bit mode is only supported with host code
compiled in 64-bit mode.
Similarly, the 32-bit version of nvcc compiles device code in 32-bit mode and
device code compiled in 32-bit mode is only supported with host code compiled in
32-bit mode.
The 32-bit version of nvcc can compile device code in 64-bit mode also using the
÷m64 compiler option.
The 64-bit version of nvcc can compile device code in 32-bit mode also using the
÷m32 compiler option.
3.2 CUDA C
CUDA C provides a simple path for users familiar with the C programming
language to easily write programs for execution by the device.
It consists of a minimal set of extensions to the C language and a runtime library.
The core language extensions have been introduced in Chapter 2. This section
continues with an introduction to the runtime. A complete description of all
extensions can be found in Appendix B and a complete description of the runtime
in the CUDA reference manual.
The runtime is implemented in the cudart dynamic library and all its entry points
are prefixed with cuda.
There is no explicit initialization function for the runtime; it initializes the first time
a runtime function is called (more specifically any function other than functions
from the device and version management sections of the reference manual). One
needs to keep this in mind when timing runtime function calls and when
interpreting the error code from the first call into the runtime.
Once the runtime has been initialized in a host thread, any resource (memory,
stream, event, etc.) allocated via some runtime function call in the host thread is
only valid within the context of the host thread. Therefore only runtime functions
calls made by the host thread (memory copies, kernel launches, …) can operate on
these resources. This is because a CUDA context (see Section 3.3.1) is created under
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CUDA C Programming Guide Version 3.2 19

the hood as part of initialization and made current to the host thread, and it cannot
be made current to any other host thread.
On system with multiple devices, kernels are executed on device 0 by default as
detailed in Section 3.2.3.
3.2.1 Device Memory
As mentioned in Section 2.4, the CUDA programming model assumes a system
composed of a host and a device, each with their own separate memory. Kernels
can only operate out of device memory, so the runtime provides functions to
allocate, deallocate, and copy device memory, as well as transfer data between host
memory and device memory.
Device memory can be allocated either as linear memory or as CUDA arrays.
CUDA arrays are opaque memory layouts optimized for texture fetching. They are
described in Section 3.2.4.
Linear memory exists on the device in a 32-bit address space for devices of compute
capability 1.x and 40-bit address space of devices of compute capability 2.x, so
separately allocated entities can reference one another via pointers, for example, in a
binary tree.
Linear memory is typically allocated using cudaMalloc() and freed using
cudaFree() and data transfer between host memory and device memory are
typically done using cudaMemcpy(). In the vector addition code sample of
Section 2.1, the vectors need to be copied from host memory to device memory:
// Device code
__global__ void VecAdd(float* A, float* B, float* C, int N)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < N)
C[i] = A[i] + B[i];
}

// Host code
int main()
{
int N = ...;
size_t size = N * sizeof(float);

// Allocate input vectors h_A and h_B in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);

// Initialize input vectors
...

// Allocate vectors in device memory
float* d_A;
cudaMalloc(&d_A, size);
float* d_B;
cudaMalloc(&d_B, size);
float* d_C;
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20 CUDA C Programming Guide Version 3.2

cudaMalloc(&d_C, size);

// Copy vectors from host memory to device memory
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);

// Invoke kernel
int threadsPerBlock = 256;
int blocksPerGrid =
(N + threadsPerBlock – 1) / threadsPerBlock;
VecAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);

// Copy result from device memory to host memory
// h_C contains the result in host memory
cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);

// Free device memory
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);

// Free host memory
...
}
Linear memory can also be allocated through cudaMallocPitch() and
cudaMalloc3D(). These functions are recommended for allocations of 2D or 3D
arrays as it makes sure that the allocation is appropriately padded to meet the
alignment requirements described in Section 5.3.2.1, therefore ensuring best
performance when accessing the row addresses or performing copies between 2D
arrays and other regions of device memory (using the cudaMemcpy2D() and
cudaMemcpy3D() functions). The returned pitch (or stride) must be used to access
array elements. The following code sample allocates a width×height 2D array of
floating-point values and shows how to loop over the array elements in device code:
// Host code
int width = 64, height = 64;
float* devPtr;
size_t pitch;
cudaMallocPitch(&devPtr, &pitch,
width * sizeof(float), height);
MyKernel<<<100, 512>>>(devPtr, pitch, width, height);

// Device code
__global__ void MyKernel(float* devPtr,
size_t pitch, int width, int height)
{
for (int r = 0; r < height; ++r) {
float* row = (float*)((char*)devPtr + r * pitch);
for (int c = 0; c < width; ++c) {
float element = row[c];
}
}
}
The following code sample allocates a width×height×depth 3D array of
floating-point values and shows how to loop over the array elements in device code:
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CUDA C Programming Guide Version 3.2 21

// Host code
int width = 64, height = 64, depth = 64;
cudaExtent extent = make_cudaExtent(width * sizeof(float),
height, depth);
cudaPitchedPtr devPitchedPtr;
cudaMalloc3D(&devPitchedPtr, extent);
MyKernel<<<100, 512>>>(devPitchedPtr, width, height, depth);

// Device code
__global__ void MyKernel(cudaPitchedPtr devPitchedPtr,
int width, int height, int depth)
{
char* devPtr = devPitchedPtr.ptr;
size_t pitch = devPitchedPtr.pitch;
size_t slicePitch = pitch * height;
for (int z = 0; z < depth; ++z) {
char* slice = devPtr + z * slicePitch;
for (int y = 0; y < height; ++y) {
float* row = (float*)(slice + y * pitch);
for (int x = 0; x < width; ++x) {
float element = row[x];
}
}
}
}
The reference manual lists all the various functions used to copy memory between
linear memory allocated with cudaMalloc(), linear memory allocated with
cudaMallocPitch() or cudaMalloc3D(), CUDA arrays, and memory
allocated for variables declared in global or constant memory space.
The following code sample illustrates various ways of accessing global variables via
the runtime API:
__constant__ float constData[256];
float data[256];
cudaMemcpyToSymbol(constData, data, sizeof(data));
cudaMemcpyFromSymbol(data, constData, sizeof(data));

__device__ float devData;
float value = 3.14f;
cudaMemcpyToSymbol(devData, &value, sizeof(float));

__device__ float* devPointer;
float* ptr;
cudaMalloc(&ptr, 256 * sizeof(float));
cudaMemcpyToSymbol(devPointer, &ptr, sizeof(ptr));
cudaGetSymbolAddress() is used to retrieve the address pointing to the
memory allocated for a variable declared in global memory space. The size of the
allocated memory is obtained through cudaGetSymbolSize().
3.2.2 Shared Memory
As detailed in Section B.2 shared memory is allocated using the __shared__
qualifier.
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22 CUDA C Programming Guide Version 3.2

Shared memory is expected to be much faster than global memory as mentioned in
Section 2.2 and detailed in Section 5.3.2.3. Any opportunity to replace global
memory accesses by shared memory accesses should therefore be exploited as
illustrated by the following matrix multiplication example.
The following code sample is a straightforward implementation of matrix
multiplication that does not take advantage of shared memory. Each thread reads
one row of A and one column of B and computes the corresponding element of C
as illustrated in Figure 3-1. A is therefore read B.width times from global memory
and B is read A.height times.
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;

// Thread block size
#define BLOCK_SIZE 16

// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);

// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width; d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size,
cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width; d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size,
cudaMemcpyHostToDevice);

// Allocate C in device memory
Matrix d_C;
d_C.width = C.width; d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);

// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

// Read C from device memory
cudaMemcpy(C.elements, Cd.elements, size,
cudaMemcpyDeviceToHost);
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CUDA C Programming Guide Version 3.2 23


// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}

// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e]
* B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}

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24 CUDA C Programming Guide Version 3.2


Figure 3-1. Matrix Multiplication without Shared Memory
The following code sample is an implementation of matrix multiplication that does
take advantage of shared memory. In this implementation, each thread block is
responsible for computing one square sub-matrix Csub of C and each thread within
the block is responsible for computing one element of Csub. As illustrated in Figure
3-2, Csub is equal to the product of two rectangular matrices: the sub-matrix of A of
dimension (A.width, block_size) that has the same line indices as Csub, and the sub-
matrix of B of dimension (block_size, A.width) that has the same column indices as
Csub. In order to fit into the device‟s resources, these two rectangular matrices are
divided into as many square matrices of dimension block_size as necessary and Csub is
computed as the sum of the products of these square matrices. Each of these
products is performed by first loading the two corresponding square matrices from
global memory to shared memory with one thread loading one element of each
matrix, and then by having each thread compute one element of the product. Each
thread accumulates the result of each of these products into a register and once
done writes the result to global memory.
A
B
C

B.width A.width
0
col
A
.
h
e
i
g
h
t

B
.
h
e
i
g
h
t

B
.
w
i
d
t
h
-
1

row
0
A.height-1
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CUDA C Programming Guide Version 3.2 25

By blocking the computation this way, we take advantage of fast shared memory
and save a lot of global memory bandwidth since A is only read (B.width / block_size)
times from global memory and B is read (A.height / block_size) times.
The Matrix type from the previous code sample is augmented with a stride field, so
that sub-matrices can be efficiently represented with the same type. __device__
functions (see Section B.1.1) are used to get and set elements and build any sub-
matrix from a matrix.
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.stride + col)
typedef struct {
int width;
int height;
int stride;
float* elements;
} Matrix;

// Get a matrix element
__device__ float GetElement(const Matrix A, int row, int col)
{
return A.elements[row * A.stride + col];
}

// Set a matrix element
__device__ void SetElement(Matrix A, int row, int col,
float value)
{
A.elements[row * A.stride + col] = value;
}

// Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is
// located col sub-matrices to the right and row sub-matrices down
// from the upper-left corner of A
__device__ Matrix GetSubMatrix(Matrix A, int row, int col)
{
Matrix Asub;
Asub.width = BLOCK_SIZE;
Asub.height = BLOCK_SIZE;
Asub.stride = A.stride;
Asub.elements = &A.elements[A.stride * BLOCK_SIZE * row
+ BLOCK_SIZE * col];
return Asub;
}

// Thread block size
#define BLOCK_SIZE 16

// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);

// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
// Load A and B to device memory
Matrix d_A;
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26 CUDA C Programming Guide Version 3.2

d_A.width = d_A.stride = A.width; d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size,
cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = d_B.stride = B.width; d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size,
cudaMemcpyHostToDevice);

// Allocate C in device memory
Matrix d_C;
d_C.width = d_C.stride = C.width; d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);

// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE);
dim3 dimGrid(B.width / dimBlock.x, A.height / dimBlock.y);
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);

// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size,
cudaMemcpyDeviceToHost);

// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}

// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C)
{
// Block row and column
int blockRow = blockIdx.y;
int blockCol = blockIdx.x;

// Each thread block computes one sub-matrix Csub of C
Matrix Csub = GetSubMatrix(C, blockRow, blockCol);

// Each thread computes one element of Csub
// by accumulating results into Cvalue
float Cvalue = 0;

// Thread row and column within Csub
int row = threadIdx.y;
int col = threadIdx.x;

// Loop over all the sub-matrices of A and B that are
// required to compute Csub
// Multiply each pair of sub-matrices together
// and accumulate the results
for (int m = 0; m < (A.width / BLOCK_SIZE); ++m) {

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// Get sub-matrix Asub of A
Matrix Asub = GetSubMatrix(A, blockRow, m);

// Get sub-matrix Bsub of B
Matrix Bsub = GetSubMatrix(B, m, blockCol);

// Shared memory used to store Asub and Bsub respectively
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];

// Load Asub and Bsub from device memory to shared memory
// Each thread loads one element of each sub-matrix
As[row][col] = GetElement(Asub, row, col);
Bs[row][col] = GetElement(Bsub, row, col);

// Synchronize to make sure the sub-matrices are loaded
// before starting the computation
__syncthreads();

// Multiply Asub and Bsub together
for (int e = 0; e < BLOCK_SIZE; ++e)
Cvalue += As[row][e] * Bs[e][col];

// Synchronize to make sure that the preceding
// computation is done before loading two new
// sub-matrices of A and B in the next iteration
__syncthreads();
}

// Write Csub to device memory
// Each thread writes one element
SetElement(Csub, row, col, Cvalue);
}
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28 CUDA C Programming Guide Version 3.2


Figure 3-2. Matrix Multiplication with Shared Memory
3.2.3 Multiple Devices
A host system can have multiple devices. These devices can be enumerated, their
properties can be queried, and one of them can be selected for kernel executions.
Several host threads can execute device code on the same device, but by design, a
host thread can execute device code on only one device at any given time. As a
consequence, multiple host threads are required to execute device code on multiple
devices. Also, any CUDA resources created through the runtime in one host thread
cannot be used by the runtime from another host thread.
The following code sample enumerates all devices in the system and retrieves their
properties. It also determines the number of CUDA-enabled devices.
int deviceCount;
cudaGetDeviceCount(&deviceCount);
int device;
for (device = 0; device < deviceCount; ++device) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
if (dev == 0) {
A

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BLOCK_SIZE BLOCK_SIZE
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if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n",
deviceCount);
}
}
By default, the device associated to the host thread is implicitly selected as device 0
as soon as a non-device management runtime function is called (see Section 3.6 for
exceptions). Any other device can be selected by calling cudaSetDevice() first.
After a device has been selected, either implicitly or explicitly, any subsequent
explicit call to cudaSetDevice() will fail up until cudaThreadExit() is called.
cudaThreadExit() cleans up all runtime-related resources associated with the
calling host thread. Any subsequent API call reinitializes the runtime.
3.2.4 Texture and Surface Memory
CUDA supports a subset of the texturing hardware that the GPU uses for graphics
to access texture and surface memory. Reading data from texture or surface memory
instead of global memory can have several performance benefits as described in
Section 5.3.2.5.
3.2.4.1 Texture Memory
Texture memory is read from kernels using device functions called texture fetches,
described in Section B.8. The first parameter of a texture fetch specifies an object
called a texture reference.
A texture reference defines which part of texture memory is fetched. As detailed in
Section 3.2.4.1.3, it must be bound through runtime functions to some region of
memory, called a texture, before it can be used by a kernel. Several distinct texture
references might be bound to the same texture or to textures that overlap in
memory.
A texture reference has several attributes. One of them is its dimensionality that
specifies whether the texture is addressed as a one-dimensional array using one
texture coordinate, a two-dimensional array using two texture coordinates, or a three-
dimensional array using three texture coordinates. Elements of the array are called
texels, short for “texture elements.”
Other attributes define the input and output data types of the texture fetch, as well
as how the input coordinates are interpreted and what processing should be done.
A texture can be any region of linear memory or a CUDA array (described in
Section 3.2.4.3).
Section G.1 lists the maximum texture width, height, and depth depending on the
compute capability of the device.
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30 CUDA C Programming Guide Version 3.2

3.2.4.1.1 Texture Reference Declaration
Some of the attributes of a texture reference are immutable and must be known at
compile time; they are specified when declaring the texture reference. A texture
reference is declared at file scope as a variable of type texture:
texture<Type, Dim, ReadMode> texRef;
where:
 Type specifies the type of data that is returned when fetching the texture; Type
is restricted to the basic integer and single-precision floating-point types and any
of the 1-, 2-, and 4-component vector types defined in Section B.3.1;
 Dim specifies the dimensionality of the texture reference and is equal to 1, 2, or
3; Dim is an optional argument which defaults to 1;
 ReadMode is equal to cudaReadModeNormalizedFloat or
cudaReadModeElementType; if it is cudaReadModeNormalizedFloat
and Type is a 16-bit or 8-bit integer type, the value is actually returned as
floating-point type and the full range of the integer type is mapped to [0.0, 1.0]
for unsigned integer type and [-1.0, 1.0] for signed integer type; for example, an
unsigned 8-bit texture element with the value 0xff reads as 1; if it is
cudaReadModeElementType, no conversion is performed; ReadMode is an
optional argument which defaults to cudaReadModeElementType.
A texture reference can only be declared as a static global variable and cannot be
passed as an argument to a function.
3.2.4.1.2 Runtime Texture Reference Attributes
The other attributes of a texture reference are mutable and can be changed at
runtime through the host runtime. They specify whether texture coordinates are
normalized or not, the addressing mode, and texture filtering, as detailed below.
By default, textures are referenced using floating-point coordinates in the range
[0, N) where N is the size of the texture in the dimension corresponding to the
coordinate. For example, a texture that is 64×32 in size will be referenced with
coordinates in the range [0, 63] and [0, 31] for the x and y dimensions, respectively.
Normalized texture coordinates cause the coordinates to be specified in the range
[0.0, 1.0) instead of [0, N), so the same 64×32 texture would be addressed by
normalized coordinates in the range [0, 1) in both the x and y dimensions.
Normalized texture coordinates are a natural fit to some applications‟ requirements,
if it is preferable for the texture coordinates to be independent of the texture size.
The addressing mode defines what happens when texture coordinates are out of
range. When using unnormalized texture coordinates, texture coordinates outside
the range [0, N) are clamped: Values below 0 are set to 0 and values greater or equal
to N are set to N-1. Clamping is also the default addressing mode when using
normalized texture coordinates: Values below 0.0 or above 1.0 are clamped to the
range [0.0, 1.0). For normalized coordinates, the “wrap” addressing mode also may
be specified. Wrap addressing is usually used when the texture contains a periodic
signal. It uses only the fractional part of the texture coordinate; for example, 1.25 is
treated the same as 0.25 and -1.25 is treated the same as 0.75.
Linear texture filtering may be done only for textures that are configured to return
floating-point data. It performs low-precision interpolation between neighboring
texels. When enabled, the texels surrounding a texture fetch location are read and
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the return value of the texture fetch is interpolated based on where the texture
coordinates fell between the texels. Simple linear interpolation is performed for one-
dimensional textures and bilinear interpolation is performed for two-dimensional
textures.
Appendix F gives more details on texture fetching.
3.2.4.1.3 Texture Binding
As explained in the reference manual, the runtime API has a low-level C-style
interface and a high-level C++-style interface. The texture type is defined in the
high-level API as a structure publicly derived from the textureReference type
defined in the low-level API as such:
struct textureReference {
int normalized;
enum cudaTextureFilterMode filterMode;
enum cudaTextureAddressMode addressMode[3];
struct cudaChannelFormatDesc channelDesc;
}
 normalized specifies whether texture coordinates are normalized or not; if it
is non-zero, all elements in the texture are addressed with texture coordinates in
the range [0,1] rather than in the range [0,width-1], [0,height-1], or
[0,depth-1] where width, height, and depth are the texture sizes;
 filterMode specifies the filtering mode, that is how the value returned when
fetching the texture is computed based on the input texture coordinates;
filterMode is equal to cudaFilterModePoint or
cudaFilterModeLinear; if it is cudaFilterModePoint, the returned
value is the texel whose texture coordinates are the closest to the input texture
coordinates; if it is cudaFilterModeLinear, the returned value is the linear
interpolation of the two (for a one-dimensional texture), four (for a
two-dimensional texture), or eight (for a three-dimensional texture) texels
whose texture coordinates are the closest to the input texture coordinates;
cudaFilterModeLinear is only valid for returned values of floating-point
type;
 addressMode specifies the addressing mode, that is how out-of-range texture
coordinates are handled; addressMode is an array of size three whose first,
second, and third elements specify the addressing mode for the first, second,
and third texture coordinates, respectively; the addressing mode is equal to
either cudaAddressModeClamp, in which case out-of-range texture
coordinates are clamped to the valid range, or cudaAddressModeWrap, in
which case out-of-range texture coordinates are wrapped to the valid range;
cudaAddressModeWrap is only supported for normalized texture
coordinates;
 channelDesc describes the format of the value that is returned when fetching
the texture; channelDesc is of the following type:
struct cudaChannelFormatDesc {
int x, y, z, w;
enum cudaChannelFormatKind f;
};
where x, y, z, and w are equal to the number of bits of each component of the
returned value and f is:
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32 CUDA C Programming Guide Version 3.2

 cudaChannelFormatKindSigned if these components are of signed
integer type,
 cudaChannelFormatKindUnsigned if they are of unsigned integer
type,
 cudaChannelFormatKindFloat if they are of floating point type.
normalized, addressMode, and filterMode may be directly modified in host
code.
Before a kernel can use a texture reference to read from texture memory, the texture
reference must be bound to a texture using cudaBindTexture() or
cudaBindTextureToArray(). cudaUnbindTexture() is used to unbind a
texture reference.
The following code samples bind a texture reference to linear memory pointed to by
devPtr:
 Using the low-level API:
texture<float, 2, cudaReadModeElementType> texRef;
textureReference* texRefPtr;
cudaGetTextureReference(&texRefPtr, “texRef”);
cudaChannelFormatDesc channelDesc =
cudaCreateChannelDesc<float>();
cudaBindTexture2D(0, texRefPtr, devPtr, &channelDesc,
width, height, pitch);
 Using the high-level API:
texture<float, 2, cudaReadModeElementType> texRef;
cudaChannelFormatDesc channelDesc =
cudaCreateChannelDesc<float>();
cudaBindTexture2D(0, texRef, devPtr, &channelDesc,
width, height, pitch);
The following code samples bind a texture reference to a CUDA array cuArray:
 Using the low-level API:
texture<float, 2, cudaReadModeElementType> texRef;
textureReference* texRefPtr;
cudaGetTextureReference(&texRefPtr, “texRef”);
cudaChannelFormatDesc channelDesc;
cudaGetChannelDesc(&channelDesc, cuArray);
cudaBindTextureToArray(texRef, cuArray, &channelDesc);
 Using the high-level API:
texture<float, 2, cudaReadModeElementType> texRef;
cudaBindTextureToArray(texRef, cuArray);
The format specified when binding a texture to a texture reference must match the
parameters specified when declaring the texture reference; otherwise, the results of
texture fetches are undefined.
The following code sample applies some simple transformation kernel to a
// 2D float texture
texture<float, 2, cudaReadModeElementType> texRef;

// Simple transformation kernel
__global__ void transformKernel(float* output,
int width, int height, float theta)
{
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// Calculate normalized texture coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;

float u = x / (float)width;
float v = y / (float)height;

// Transform coordinates
u -= 0.5f;
v -= 0.5f;
float tu = u * cosf(theta) – v * sinf(theta) + 0.5f;
float tv = v * cosf(theta) + u * sinf(theta) + 0.5f;

// Read from texture and write to global memory
output[y * width + x] = tex2D(texRef, tu, tv);
}

// Host code
int main()
{
// Allocate CUDA array in device memory
cudaChannelFormatDesc channelDesc =
cudaCreateChannelDesc(32, 0, 0, 0,
cudaChannelFormatKindFloat);
cudaArray* cuArray;
cudaMallocArray(&cuArray, &channelDesc, width, height);

// Copy to device memory some data located at address h_data
// in host memory
cudaMemcpyToArray(cuArray, 0, 0, h_data, size,
cudaMemcpyHostToDevice);

// Set texture parameters
texRef.addressMode[0] = cudaAddressModeWrap;
texRef.addressMode[1] = cudaAddressModeWrap;
texRef.filterMode = cudaFilterModeLinear;
texRef.normalized = true;

// Bind the array to the texture reference
cudaBindTextureToArray(texRef, cuArray, channelDesc);

// Allocate result of transformation in device memory
float* output;
cudaMalloc(&output, width * height * sizeof(float));

// Invoke kernel
dim3 dimBlock(16, 16);
dim3 dimGrid((width + dimBlock.x – 1) / dimBlock.x,
(height + dimBlock.y – 1) / dimBlock.y);
transformKernel<<<dimGrid, dimBlock>>>(output, width, height,
angle);

// Free device memory
cudaFreeArray(cuArray);
cudaFree(output);
}
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3.2.4.1.4 16-Bit Floating-Point Textures
The 16-bit floating-point or half format supported by CUDA arrays is the same as
the IEEE 754-2008 binary2 format.
CUDA C does not support a matching data type, but provides intrinsic functions to
convert to and from the 32-bit floating-point format via the unsigned short
type: __float2half(float) and __half2float(unsigned short). These
functions are only supported in device code. Equivalent functions for the host code
can be found in the OpenEXR library, for example.
16-bit floating-point components are promoted to 32 bit float during texture
fetching before any filtering is performed.
A channel description for the 16-bit floating-point format can be created by calling
one of the cudaCreateChannelDescHalf*() functions.
3.2.4.2 Surface Memory
A CUDA array (described in Section 3.2.4.3), created with the
cudaArraySurfaceLoadStore flag, can be read and written via a surface reference
using the functions described in Section B.9.
Section G.1 lists the maximum surface width, height, and depth depending on the
compute capability of the device.
3.2.4.2.1 Surface Reference Declaration
A surface reference is declared at file scope as a variable of type surface:
surface<void, Dim> surfRef;
where Dim specifies the dimensionality of the surface reference and is equal to 1 or
2; Dim is an optional argument which defaults to 1.
A surface reference can only be declared as a static global variable and cannot be
passed as an argument to a function.
3.2.4.2.2 Surface Binding
Before a kernel can use a surface reference to access a CUDA array, the surface
reference must be bound to the CUDA array using
cudaBindSurfaceToArray().
The following code samples bind a surface reference to a CUDA array cuArray:
 Using the low-level API:
surface<void, 2> surfRef;
surfaceReference* surfRefPtr;
cudaGetSurfaceReference(&surfRefPtr, “surfRef”);
cudaChannelFormatDesc channelDesc;
cudaGetChannelDesc(&channelDesc, cuArray);
cudaBindSurfaceToArray(surfRef, cuArray, &channelDesc);
 Using the high-level API:
surface<void, 2> surfRef;
cudaBindSurfaceToArray(surfRef, cuArray);
A CUDA array must be read and written using surface functions of matching
dimensionality and type and via a surface reference of matching dimensionality;
otherwise, the results of reading and writing the CUDA array are undefined.
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Unlike texture memory, surface memory uses byte addressing. This means that the
x-coordinate used to access a texture element via texture functions needs to be
multiplied by the byte size of the element to access the same element via a surface
function. For example, the element at texture coordinate x of a one-dimensional
floating-point CUDA array bound to a texture reference texRef and a surface
reference surfRef is read using tex1d(texRef, x) via texRef, but
surf1Dread(surfRef, 4*x) via surfRef. Similarly, the element at texture
coordinate x and y of a two-dimensional floating-point CUDA array bound to a
texture reference texRef and a surface reference surfRef is accessed using
tex2d(texRef, x, y) via texRef, but surf2Dread(surfRef, 4*x, y)
via surfRef (the byte offset of the y-coordinate is internally calculated from the
underlying line pitch of the CUDA array).
The following code sample applies some simple transformation kernel to a
// 2D surfaces
surface<void, 2> inputSurfRef;
surface<void, 2> outputSurfRef;

// Simple copy kernel
__global__ void copyKernel(int width, int height)
{
// Calculate surface coordinates
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;
if (x < width && y < height) {
uchar4 data;
// Read from input surface
surf2Dread(&data, inputSurfRef, x * 4, y);
// Write to output surface
surf2Dwrite(data, outputSurfRef, x * 4, y);
}
}

// Host code
int main()
{
// Allocate CUDA arrays in device memory
cudaChannelFormatDesc channelDesc =
cudaCreateChannelDesc(8, 8, 8, 8,
cudaChannelFormatKindUnsigned);
cudaArray* cuInputArray;
cudaMallocArray(&cuInputArray, &channelDesc, width, height,
cudaArraySurfaceLoadStore);
cudaArray* cuOutputArray;
cudaMallocArray(&cuOutputArray, &channelDesc, width, height,
cudaArraySurfaceLoadStore);

// Copy to device memory some data located at address h_data
// in host memory
cudaMemcpyToArray(cuInputArray, 0, 0, h_data, size,
cudaMemcpyHostToDevice);

// Bind the arrays to the surface references
cudaBindSurfaceToArray(inputSurfRef, cuInputArray);
cudaBindSurfaceToArray(outputSurfRef, cuOutputArray);
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// Invoke kernel
dim3 dimBlock(16, 16);
dim3 dimGrid((width + dimBlock.x – 1) / dimBlock.x,
(height + dimBlock.y – 1) / dimBlock.y);
copyKernel<<<dimGrid, dimBlock>>>(width, height);

// Free device memory
cudaFreeArray(cuInputArray);
cudaFreeArray(cuOutputArray);
}
3.2.4.3 CUDA Arrays
CUDA arrays are opaque memory layouts optimized for texture fetching. They are
one-dimensional, two-dimensional, or three-dimensional and composed of
elements, each of which has 1, 2 or 4 components that may be signed or unsigned
8-, 16- or 32-bit integers, 16-bit floats, or 32-bit floats. CUDA arrays are only
readable by kernels through texture fetching and may only be bound to texture
references with the same number of packed components.
3.2.4.4 Read/Write Coherency
The texture and surface memory is cached (see Section 5.3.2.5) and within the same
kernel call, the cache is not kept coherent with respect to global memory writes and
surface memory writes, so any texture fetch or surface read to an address that has
been written to via a global write or a surface write in the same kernel call returns
undefined data. In other words, a thread can safely read some texture or surface
memory location only if this memory location has been updated by a previous
kernel call or memory copy, but not if it has been previously updated by the same
thread or another thread from the same kernel call.
3.2.5 Page-Locked Host Memory
The runtime also provides functions to allocate and free page-locked (also known as
pinned) host memory – as opposed to regular pageable host memory allocated by
malloc(): cudaHostAlloc() and cudaFreeHost().
Using page-locked host memory has several benefits:
 Copies between page-locked host memory and device memory can be
performed concurrently with kernel execution for some devices as mentioned in
Section 3.2.6;
 On some devices, page-locked host memory can be mapped into the address
space of the device, eliminating the need to copy it to or from device memory
as detailed in Section 3.2.5.3;
 On systems with a front-side bus, bandwidth between host memory and device
memory is higher if host memory is allocated as page-locked and even higher if
in addition it is allocated as write-combining as described in Section 3.2.5.2.
Page-locked host memory is a scarce resource however, so allocations in page-
locked memory will start failing long before allocations in pageable memory. In
addition, by reducing the amount of physical memory available to the operating
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CUDA C Programming Guide Version 3.2 37

system for paging, allocating too much page-locked memory reduces overall system
performance.
The simple zero-copy SDK sample comes with a detailed document on the page-
locked memory APIs.
3.2.5.1 Portable Memory
A block of page-locked memory can be used by any host threads, but by default, the
benefits of using page-locked memory described above are only available for the
thread that allocates it. To make these advantages available to all threads, it needs to
be allocated by passing flag cudaHostAllocPortable to cudaHostAlloc().
3.2.5.2 Write-Combining Memory
By default page-locked host memory is allocated as cacheable. It can optionally be
allocated as write-combining instead by passing flag
cudaHostAllocWriteCombined to cudaHostAlloc(). Write-combining
memory frees up L1 and L2 cache resources, making more cache available to the
rest of the application. In addition, write-combining memory is not snooped during
transfers across the PCI Express bus, which can improve transfer performance by
up to 40%.
Reading from write-combining memory from the host is prohibitively slow, so
write-combining memory should in general be used for memory that the host only
writes to.
3.2.5.3 Mapped Memory
On devices of compute capability greater than 1.0, a block of page-locked host
memory can also be mapped into the address space of the device by passing flag
cudaHostAllocMapped to cudaHostAlloc(). Such a block has therefore two
addresses: one in host memory and one in device memory. The host memory
pointer is returned by cudaHostAlloc() and the device memory pointer can be
retrieved using cudaHostGetDevicePointer()and then used to access the
block from within a kernel.
Accessing host memory directly from within a kernel has several advantages:
 There is no need to allocate a block in device memory and copy data between
this block and the block in host memory; data transfers are implicitly performed
as needed by the kernel;
 There is no need to use streams (see Section 3.2.6.4) to overlap data transfers
with kernel execution; the kernel-originated data transfers automatically overlap
with kernel execution.
Since mapped page-locked memory is shared between host and device however, the
application must synchronize memory accesses using streams or events (see
Section 3.2.6) to avoid any potential read-after-write, write-after-read, or write-after-
write hazards.
A block of page-locked host memory can be allocated as both mapped and portable
(see Section 3.2.5.1), in which case each host thread that needs to map the block to
its device address space must call cudaHostGetDevicePointer() to retrieve a
device pointer, as device pointers will generally differ from one host thread to the
other.
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To be able to retrieve the device pointer to any mapped page-locked memory within
a given host thread, page-locked memory mapping must be enabled by calling
cudaSetDeviceFlags() with the cudaDeviceMapHost flag before any other
CUDA calls is performed by the thread. Otherwise,
cudaHostGetDevicePointer() will return an error.
cudaHostGetDevicePointer() also returns an error if the device does not
support mapped page-locked host memory.
Applications may query whether a device supports mapped page-locked host
memory or not by calling cudaGetDeviceProperties() and checking the
canMapHostMemory property.
Note that atomic functions (Section B.11) operating on mapped page-locked
memory are not atomic from the point of view of the host or other devices.
3.2.6 Asynchronous Concurrent Execution
3.2.6.1 Concurrent Execution between Host and Device
In order to facilitate concurrent execution between host and device, some function
calls are asynchronous: Control is returned to the host thread before the device has
completed the requested task. These are:
 Kernel launches;
 Device ÷ device memory copies;
 Host ÷ device memory copies of a memory block of 64 KB or less;
 Memory copies performed by functions that are suffixed with Async;
 Memory set function calls.
Programmers can globally disable asynchronous kernel launches for all CUDA
applications running on a system by setting the CUDA_LAUNCH_BLOCKING
environment variable to 1. This feature is provided for debugging purposes only and
should never be used as a way to make production software run reliably.
When an application is run via a CUDA debugger or profiler (cuda-gdb, CUDA
Visual Profiler, Parallel Nsight), all launches are synchronous.
3.2.6.2 Overlap of Data Transfer and Kernel Execution
Some devices of compute capability 1.1 and higher can perform copies between
page-locked host memory and device memory concurrently with kernel execution.
Applications may query this capability by calling cudaGetDeviceProperties()
and checking the deviceOverlap property. This capability is currently supported
only for memory copies that do not involve CUDA arrays or 2D arrays allocated
through cudaMallocPitch() (see Section 3.2.1).
3.2.6.3 Concurrent Kernel Execution
Some devices of compute capability 2.x can execute multiple kernels concurrently.
Applications may query this capability by calling cudaGetDeviceProperties()
and checking the concurrentKernels property.
The maximum number of kernel launches that a device can execute concurrently is
sixteen.
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A kernel from one CUDA context cannot execute concurrently with a kernel from
another CUDA context.
Kernels that use many textures or a large amount of local memory are less likely to
execute concurrently with other kernels.
3.2.6.4 Concurrent Data Transfers
Some devices of compute capability 2.x can perform a copy from page-locked host
memory to device memory concurrently with a copy from device memory to page-
locked host memory.
3.2.6.5 Stream
Applications manage concurrency through streams. A stream is a sequence of
commands that execute in order. Different streams, on the other hand, may execute
their commands out of order with respect to one another or concurrently; this
behavior is not guaranteed and should therefore not be relied upon for correctness
(e.g. inter-kernel communication is undefined).
3.2.6.5.1 Creation and Destruction
A stream is defined by creating a stream object and specifying it as the stream
parameter to a sequence of kernel launches and host ÷ device memory copies. The
following code sample creates two streams and allocates an array hostPtr of
float in page-locked memory.
cudaStream_t stream[2];
for (int i = 0; i < 2; ++i)
cudaStreamCreate(&stream[i]);
float* hostPtr;
cudaMallocHost(&hostPtr, 2 * size);
Each of these streams is defined by the following code sample as a sequence of one
memory copy from host to device, one kernel launch, and one memory copy from
device to host:
for (int i = 0; i < 2; ++i) {
cudaMemcpyAsync(inputDevPtr + i * size, hostPtr + i * size,
size, cudaMemcpyHostToDevice, stream[i]);
MyKernel<<<100, 512, 0, stream[i]>>>
(outputDevPtr + i * size, inputDevPtr + i * size, size);
cudaMemcpyAsync(hostPtr + i * size, outputDevPtr + i * size,
size, cudaMemcpyDeviceToHost, stream[i]);
}
Each stream copies its portion of input array hostPtr to array inputDevPtr in
device memory, processes inputDevPtr on the device by calling MyKernel(), and
copies the result outputDevPtr back to the same portion of hostPtr.
Section 3.2.6.5.4 describes how the streams overlap in this example depending on
the capability of the device. Note that hostPtr must point to page-locked host
memory for any overlap to occur.
Streams are released by calling cudaStreamDestroy().
for (int i = 0; i < 2; ++i)
cudaStreamDestroy(stream[i]);
cudaStreamDestroy() waits for all preceding commands in the given stream to
complete before destroying the stream and returning control to the host thread.
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3.2.6.5.2 Explicit Synchronization
There are various ways to explicitly synchronize streams with each other.
cudaThreadSynchronize() waits until all preceding commands in all streams have
completed.
cudaStreamSynchronize() takes a stream as a parameter and waits until all
preceding commands in the given stream have completed. It can be used to
synchronize the host with a specific stream, allowing other streams to continue
executing on the device.
cudaStreamWaitEvent() takes a stream and an event as parameters (see
Section 3.2.6.6 for a description of events) and makes all the commands added to
the given stream after the call to cudaStreamWaitEvent() delay their execution
until the given event has completed. The stream can be 0, in which case all the
commands added to any stream after the call to cudaStreamWaitEvent() wait on
the event.
cudaStreamQuery() provides applications with a way to know if all preceding
commands in a stream have completed.
To avoid unnecessary slowdowns, all these synchronization functions are usually
best used for timing purposes or to isolate a launch or memory copy that is failing.
3.2.6.5.3 Implicit Synchronization
Two commands from different streams cannot run concurrently if either one of the
following operations is issued in-between them by the host thread:
 a page-locked host memory allocation,
 a device memory allocation,
 a device memory set,
 a device ÷ device memory copy,
 any CUDA command to stream 0 (including kernel launches and host ÷ device
memory copies that do not specify any stream parameter),
 a switch between the L1/shared memory configurations described in
Section G.4.1.
For devices that support concurrent kernel execution, any operation that requires a
dependency check to see if a streamed kernel launch is complete:
 Can start executing only when all thread blocks of all prior kernel launches from
any stream in the CUDA context have started executing;
 Blocks all later kernel launches from any stream in the CUDA context until the
kernel launch being checked is complete.
Operations that require a dependency check include any other commands within the
same stream as the launch being checked and any call to cudaStreamQuery() on
that stream. Therefore, applications should follow these guidelines to improve their
potential for concurrent kernel execution:
 All independent operations should be issued before dependent operations,
 Synchronization of any kind should be delayed as long as possible.
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3.2.6.5.4 Overlapping Behavior
The amount of execution overlap between two streams depends on the order in
which the commands are issued to each stream and whether or not the device
supports overlap of data transfer and kernel execution (Section 3.2.6.2), concurrent
kernel execution (Section 3.2.6.3), and/or concurrent data transfers (Section 3.2.6.4).
For example, on devices that do not support concurrent data transfers, the two
streams of the code sample of Section 3.2.6.5.1 do not overlap at all because the
memory copy from host to device is issued to stream 1 after the memory copy from
device to host is issued to stream 0. If the code is rewritten the following way (and
assuming the device supports overlap of data transfer and kernel execution)
for (int i = 0; i < 2; ++i)
cudaMemcpyAsync(inputDevPtr + i * size, hostPtr + i * size,
size, cudaMemcpyHostToDevice, stream[i]);
for (int i = 0; i < 2; ++i)
MyKernel<<<100, 512, 0, stream[i]>>>
(outputDevPtr + i * size, inputDevPtr + i * size, size);
for (int i = 0; i < 2; ++i)
cudaMemcpyAsync(hostPtr + i * size, outputDevPtr + i * size,
size, cudaMemcpyDeviceToHost, stream[i]);
then the memory copy from host to device issued to stream 1 overlaps with the
kernel launch issued to stream 0.
On devices that do support concurrent data transfers, the two streams of the code
sample of Section 3.2.6.5.1 do overlap: The memory copy from host to device
issued to stream 1 overlaps with the memory copy from device to host issued to
stream 0 and even with the kernel launch issued to stream 0 (assuming the device
supports overlap of data transfer and kernel execution). However, the kernel
executions cannot possibly overlap because the kernel launch is issued to stream 1
after the memory copy from device to host is issued to stream 0, so it is blocked
until the kernel launch issued to stream 0 is complete as per Section 3.2.6.5.3. If the
code is rewritten as above, the kernel executions overlap (assuming the device
supports concurrent kernel execution) since the kernel launch is issued to stream 1
before the memory copy from device to host is issued to stream 0. In that case
however, the memory copy from device to host issued to stream 0 only overlaps
with the last thread blocks of the kernel launch issued to stream 1 as per
Section 3.2.6.5.3, which can represent a small portion of the total execution time of
the kernel.
3.2.6.6 Event
The runtime also provides a way to closely monitor the device‟s progress, as well as
perform accurate timing, by letting the application asynchronously record events at
any point in the program and query when these events are completed. An event has
completed when all tasks – or optionally, all commands in a given stream –
preceding the event have completed. Events in stream zero are completed after all
preceding task and commands in all streams are completed.
The following code sample creates two events:
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
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These events can be used to time the code sample of the previous section the
following way:
cudaEventRecord(start, 0);
for (int i = 0; i < 2; ++i) {
cudaMemcpyAsync(inputDev + i * size, inputHost + i * size,
size, cudaMemcpyHostToDevice, stream[i]);
MyKernel<<<100, 512, 0, stream[i]>>>
(outputDev + i * size, inputDev + i * size, size);
cudaMemcpyAsync(outputHost + i * size, outputDev + i * size,
size, cudaMemcpyDeviceToHost, stream[i]);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
float elapsedTime;
cudaEventElapsedTime(&elapsedTime, start, stop);
They are destroyed this way:
cudaEventDestroy(start);
cudaEventDestroy(stop);
3.2.6.7 Synchronous Calls
When a synchronous function is called, control is not returned to the host thread
before the device has completed the requested task. Whether the host thread will
then yield, block, or spin can be specified by calling cudaSetDeviceFlags()with
some specific flags (see reference manual for details) before any other CUDA calls is
performed by the host thread.
3.2.7 Graphics Interoperability
Some resources from OpenGL and Direct3D may be mapped into the address
space of CUDA, either to enable CUDA to read data written by OpenGL or
Direct3D, or to enable CUDA to write data for consumption by OpenGL or
Direct3D.
A resource must be registered to CUDA before it can be mapped using the
functions mentioned in Sections 3.2.7.1 and 3.2.7.2. These functions return a
pointer to a CUDA graphics resource of type struct cudaGraphicsResource.
Registering a resource is potentially high-overhead and therefore typically called only
once per resource. A CUDA graphics resource is unregistered using
cudaGraphicsUnregisterResource().
Once a resource is registered to CUDA, it can be mapped and unmapped as many
times as necessary using cudaGraphicsMapResources() and
cudaGraphicsUnmapResources().
cudaGraphicsResourceSetMapFlags() can be called to specify usage hints
(write-only, read-only) that the CUDA driver can use to optimize resource
management.
A mapped resource can be read from or written to by kernels using the device
memory address returned by cudaGraphicsResourceGetMappedPointer()
for buffers and cudaGraphicsSubResourceGetMappedArray() for CUDA
arrays.
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Accessing a resource through OpenGL or Direct3D while it is mapped to CUDA
produces undefined results.
Sections 3.2.7.1 and 3.2.7.2 give specifics for each graphics API and some code
samples.
3.2.7.1 OpenGL Interoperability
Interoperability with OpenGL requires that the CUDA device be specified by
cudaGLSetGLDevice() before any other runtime calls. Note that
cudaSetDevice()and cudaGLSetGLDevice() are mutually exclusive.
The OpenGL resources that may be mapped into the address space of CUDA are
OpenGL buffer, texture, and renderbuffer objects.
A buffer object is registered using cudaGraphicsGLRegisterBuffer(). In
CUDA, it appears as a device pointer and can therefore be read and written by
kernels or via cudaMemcpy() calls.
A texture or renderbuffer object is registered using
cudaGraphicsGLRegisterImage(). In CUDA, it appears as a CUDA array
and can therefore be bound to a texture reference and be read and written by
kernels or via cudaMemcpy2D() calls. cudaGraphicsGLRegisterImage()
supports all texture formats with 1, 2, or 4 components and an internal type of float
(e.g. GL_RGBA_FLOAT32) and unnormalized integer (e.g. GL_RGBA8UI). It does
not currently support normalized integer formats (e.g. GL_RGBA8). Please note that
since GL_RGBA8UI is an OpenGL 3.0 texture format, it can only be written by
shaders, not the fixed function pipeline.
The following code sample uses a kernel to dynamically modify a 2D
width x height grid of vertices stored in a vertex buffer object:
GLuint positionsVBO;
struct cudaGraphicsResource* positionsVBO_CUDA;

int main()
{
// Explicitly set device
cudaGLSetGLDevice(0);

// Initialize OpenGL and GLUT
...
glutDisplayFunc(display);

// Create buffer object and register it with CUDA
glGenBuffers(1, positionsVBO);
glBindBuffer(GL_ARRAY_BUFFER, &vbo);
unsigned int size = width * height * 4 * sizeof(float);
glBufferData(GL_ARRAY_BUFFER, size, 0, GL_DYNAMIC_DRAW);
glBindBuffer(GL_ARRAY_BUFFER, 0);
cudaGraphicsGLRegisterBuffer(&positionsVBO_CUDA,
positionsVBO,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
glutMainLoop();
}

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void display()
{
// Map buffer object for writing from CUDA
float4* positions;
cudaGraphicsMapResources(1, &positionsVBO_CUDA, 0);
size_t num_bytes;
cudaGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVBO_CUDA));

// Execute kernel
dim3 dimBlock(16, 16, 1);
dim3 dimGrid(width / dimBlock.x, height / dimBlock.y, 1);
createVertices<<<dimGrid, dimBlock>>>(positions, time,
width, height);

// Unmap buffer object
cudaGraphicsUnmapResources(1, &positionsVBO_CUDA, 0);

// Render from buffer object
glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
glBindBuffer(GL_ARRAY_BUFFER, positionsVBO);
glVertexPointer(4, GL_FLOAT, 0, 0);
glEnableClientState(GL_VERTEX_ARRAY);
glDrawArrays(GL_POINTS, 0, width * height);
glDisableClientState(GL_VERTEX_ARRAY);

// Swap buffers
glutSwapBuffers();
glutPostRedisplay();
}

void deleteVBO()
{
cudaGraphicsUnregisterResource(positionsVBO_CUDA);
glDeleteBuffers(1, &positionsVBO);
}

__global__ void createVertices(float4* positions, float time,
unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;

// Calculate uv coordinates
float u = x / (float)width;
float v = y / (float)height;
u = u * 2.0f - 1.0f;
v = v * 2.0f - 1.0f;

// calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u * freq + time)
* cosf(v * freq + time) * 0.5f;

// Write positions
positions[y * width + x] = make_float4(u, w, v, 1.0f);
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}
On Windows and for Quadro GPUs, cudaWGLGetDevice() can be used to
retrieve the CUDA device associated to the handle returned by
wglEnumGpusNV(). Quadro GPUs offer higher performance OpenGL
interoperability than GeForce and Tesla GPUs in a multi-GPU configuration where
OpenGL rendering is performed on the Quadro GPU and CUDA computations are
performed on other GPUs in the system.
3.2.7.2 Direct3D Interoperability
Direct3D interoperability is supported for Direct3D 9, Direct3D 10, and
Direct3D 11.
A CUDA context may interoperate with only one Direct3D device at a time and the
CUDA context and Direct3D device must be created on the same GPU. Moreover,
the Direct3D device must be created with the
D3DCREATE_HARDWARE_VERTEXPROCESSING flag.
Interoperability with Direct3D requires that the Direct3D device be specified by
cudaD3D9SetDirect3DDevice(), cudaD3D10SetDirect3DDevice() and
cudaD3D11SetDirect3DDevice(), before any other runtime calls.
cudaD3D9GetDevice(), cudaD3D10GetDevice(), and
cudaD3D11GetDevice() can be used to retrieve the CUDA device associated to
some adapter.
A set of calls is also available to allow the creation of CUDA devices with
interoperability with Direct3D devices that use NVIDIA SLI in AFR (Alternate
Frame Rendering) mode: cudaD3D[9|10|11]GetDevices(). A call to
cuD3D[9|10|11]GetDevices()can be used to obtain a list of CUDA device
handles that can be passed as the (optional) last parameter to
cudaD3D[9|10|11]SetDirect3DDevice().
The application has the choice to either create multiple CPU threads, each using a
different CUDA context, or a single CPU thread using multiple CUDA context.
Each of these CUDA contexts would be created using one of the CUDA device
handles returned by cudaD3D[9|10|11]GetDevices()).
If using a single CPU thread, the application relies on the interoperability between
CUDA driver and runtime APIs (Section 3.4), which allows it to call
cuCtxPushCurrent() and cuCtxPopCurrent()to change the CUDA context
active at a given time.
See Section 4.3 for general recommendations related to interoperability between
Direct3D devices using SLI and CUDA contexts.
The Direct3D resources that may be mapped into the address space of CUDA are
Direct3D buffers, textures, and surfaces. These resources are registered using
cudaGraphicsD3D9RegisterResource(),
cudaGraphicsD3D10RegisterResource(), and
cudaGraphicsD3D11RegisterResource().
The following code sample uses a kernel to dynamically modify a 2D
width x height grid of vertices stored in a vertex buffer object.
Direct3D 9 Version:
IDirect3D9* D3D;
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IDirect3DDevice9* device;
struct CUSTOMVERTEX {
FLOAT x, y, z;
DWORD color;
};
IDirect3DVertexBuffer9* positionsVB;
struct cudaGraphicsResource* positionsVB_CUDA;

int main()
{
// Initialize Direct3D
D3D = Direct3DCreate9(D3D_SDK_VERSION);

// Get a CUDA-enabled adapter
unsigned int adapter = 0;
for (; adapter < g_pD3D->GetAdapterCount(); adapter++) {
D3DADAPTER_IDENTIFIER9 adapterId;
g_pD3D->GetAdapterIdentifier(adapter, 0, &adapterId);
int dev;
if (cudaD3D9GetDevice(&dev, adapterId.DeviceName)
== cudaSuccess)
break;
}

// Create device
...
D3D->CreateDevice(adapter, D3DDEVTYPE_HAL, hWnd,
D3DCREATE_HARDWARE_VERTEXPROCESSING,
&params, &device);

// Register device with CUDA
cudaD3D9SetDirect3DDevice(device);

// Create vertex buffer and register it with CUDA
unsigned int size = width * height * sizeof(CUSTOMVERTEX);
device->CreateVertexBuffer(size, 0, D3DFVF_CUSTOMVERTEX,
D3DPOOL_DEFAULT, &positionsVB, 0);
cudaGraphicsD3D9RegisterResource(&positionsVB_CUDA,
positionsVB,
cudaGraphicsRegisterFlagsNone);
cudaGraphicsResourceSetMapFlags(positionsVB_CUDA,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
while (...) {
...
Render();
...
}
}

void Render()
{
// Map vertex buffer for writing from CUDA
float4* positions;
cudaGraphicsMapResources(1, &positionsVB_CUDA, 0);
size_t num_bytes;
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cudaGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVB_CUDA));

// Execute kernel
dim3 dimBlock(16, 16, 1);
dim3 dimGrid(width / dimBlock.x, height / dimBlock.y, 1);
createVertices<<<dimGrid, dimBlock>>>(positions, time,
width, height);

// Unmap vertex buffer
cudaGraphicsUnmapResources(1, &positionsVB_CUDA, 0);

// Draw and present
...
}

void releaseVB()
{
cudaGraphicsUnregisterResource(positionsVB_CUDA);
positionsVB->Release();
}

__global__ void createVertices(float4* positions, float time,
unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;

// Calculate uv coordinates
float u = x / (float)width;
float v = y / (float)height;
u = u * 2.0f - 1.0f;
v = v * 2.0f - 1.0f;

// Calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u * freq + time)
* cosf(v * freq + time) * 0.5f;

// Write positions
positions[y * width + x] =
make_float4(u, w, v, __int_as_float(0xff00ff00));
}
Direct3D 10 Version:
ID3D10Device* device;
struct CUSTOMVERTEX {
FLOAT x, y, z;
DWORD color;
};
ID3D10Buffer* positionsVB;
struct cudaGraphicsResource* positionsVB_CUDA;

int main()
{
// Get a CUDA-enabled adapter
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IDXGIFactory* factory;
CreateDXGIFactory(__uuidof(IDXGIFactory), (void**)&factory);
IDXGIAdapter* adapter = 0;
for (unsigned int i = 0; !adapter; ++i) {
if (FAILED(factory->EnumAdapters(i, &adapter))
break;
int dev;
if (cudaD3D10GetDevice(&dev, adapter) == cudaSuccess)
break;
adapter->Release();
}
factory->Release();

// Create swap chain and device
...
D3D10CreateDeviceAndSwapChain(adapter,
D3D10_DRIVER_TYPE_HARDWARE, 0,
D3D10_CREATE_DEVICE_DEBUG,
D3D10_SDK_VERSION,
&swapChainDesc, &swapChain,
&device);
adapter->Release();

// Register device with CUDA
cudaD3D10SetDirect3DDevice(device);

// Create vertex buffer and register it with CUDA
unsigned int size = width * height * sizeof(CUSTOMVERTEX);
D3D10_BUFFER_DESC bufferDesc;
bufferDesc.Usage = D3D10_USAGE_DEFAULT;
bufferDesc.ByteWidth = size;
bufferDesc.BindFlags = D3D10_BIND_VERTEX_BUFFER;
bufferDesc.CPUAccessFlags = 0;
bufferDesc.MiscFlags = 0;
device->CreateBuffer(&bufferDesc, 0, &positionsVB);
cudaGraphicsD3D10RegisterResource(&positionsVB_CUDA,
positionsVB,
cudaGraphicsRegisterFlagsNone);
cudaGraphicsResourceSetMapFlags(positionsVB_CUDA,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
while (...) {
...
Render();
...
}
}

void Render()
{
// Map vertex buffer for writing from CUDA
float4* positions;
cudaGraphicsMapResources(1, &positionsVB_CUDA, 0);
size_t num_bytes;
cudaGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
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positionsVB_CUDA));

// Execute kernel
dim3 dimBlock(16, 16, 1);
dim3 dimGrid(width / dimBlock.x, height / dimBlock.y, 1);
createVertices<<<dimGrid, dimBlock>>>(positions, time,
width, height);

// Unmap vertex buffer
cudaGraphicsUnmapResources(1, &positionsVB_CUDA, 0);

// Draw and present
...
}

void releaseVB()
{
cudaGraphicsUnregisterResource(positionsVB_CUDA);
positionsVB->Release();
}

__global__ void createVertices(float4* positions, float time,
unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;

// Calculate uv coordinates
float u = x / (float)width;
float v = y / (float)height;
u = u * 2.0f - 1.0f;
v = v * 2.0f - 1.0f;

// Calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u * freq + time)
* cosf(v * freq + time) * 0.5f;

// Write positions
positions[y * width + x] =
make_float4(u, w, v, __int_as_float(0xff00ff00));
}
Direct3D 11 Version:
ID3D11Device* device;
struct CUSTOMVERTEX {
FLOAT x, y, z;
DWORD color;
};
ID3D11Buffer* positionsVB;
struct cudaGraphicsResource* positionsVB_CUDA;

int main()
{
// Get a CUDA-enabled adapter
IDXGIFactory* factory;
CreateDXGIFactory(__uuidof(IDXGIFactory), (void**)&factory);
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IDXGIAdapter* adapter = 0;
for (unsigned int i = 0; !adapter; ++i) {
if (FAILED(factory->EnumAdapters(i, &adapter))
break;
int dev;
if (cudaD3D11GetDevice(&dev, adapter) == cudaSuccess)
break;
adapter->Release();
}
factory->Release();

// Create swap chain and device
...
sFnPtr_D3D11CreateDeviceAndSwapChain(adapter,
D3D11_DRIVER_TYPE_HARDWARE,
0,
D3D11_CREATE_DEVICE_DEBUG,
featureLevels, 3,
D3D11_SDK_VERSION,
&swapChainDesc, &swapChain,
&device,
&featureLevel,
&deviceContext);
adapter->Release();

// Register device with CUDA
cudaD3D11SetDirect3DDevice(device);

// Create vertex buffer and register it with CUDA
unsigned int size = width * height * sizeof(CUSTOMVERTEX);
D3D11_BUFFER_DESC bufferDesc;
bufferDesc.Usage = D3D11_USAGE_DEFAULT;
bufferDesc.ByteWidth = size;
bufferDesc.BindFlags = D3D11_BIND_VERTEX_BUFFER;
bufferDesc.CPUAccessFlags = 0;
bufferDesc.MiscFlags = 0;
device->CreateBuffer(&bufferDesc, 0, &positionsVB);
cudaGraphicsD3D11RegisterResource(&positionsVB_CUDA,
positionsVB,
cudaGraphicsRegisterFlagsNone);
cudaGraphicsResourceSetMapFlags(positionsVB_CUDA,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
while (...) {
...
Render();
...
}
}

void Render()
{
// Map vertex buffer for writing from CUDA
float4* positions;
cudaGraphicsMapResources(1, &positionsVB_CUDA, 0);
size_t num_bytes;
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cudaGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVB_CUDA));

// Execute kernel
dim3 dimBlock(16, 16, 1);
dim3 dimGrid(width / dimBlock.x, height / dimBlock.y, 1);
createVertices<<<dimGrid, dimBlock>>>(positions, time,
width, height);

// Unmap vertex buffer
cudaGraphicsUnmapResources(1, &positionsVB_CUDA, 0);

// Draw and present
...
}

void releaseVB()
{
cudaGraphicsUnregisterResource(positionsVB_CUDA);
positionsVB->Release();
}

__global__ void createVertices(float4* positions, float time,
unsigned int width, unsigned int height)
{
unsigned int x = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y * blockDim.y + threadIdx.y;

// Calculate uv coordinates
float u = x / (float)width;
float v = y / (float)height;
u = u * 2.0f - 1.0f;
v = v * 2.0f - 1.0f;

// Calculate simple sine wave pattern
float freq = 4.0f;
float w = sinf(u * freq + time)
* cosf(v * freq + time) * 0.5f;

// Write positions
positions[y * width + x] =
make_float4(u, w, v, __int_as_float(0xff00ff00));
}
3.2.8 Error Handling
All runtime functions return an error code, but for an asynchronous function (see
Section 3.2.6), this error code cannot possibly report any of the asynchronous errors
that could occur on the device since the function returns before the device has
completed the task; the error code only reports errors that occur on the host prior
to executing the task, typically related to parameter validation; if an asynchronous
error occurs, it will be reported by some subsequent unrelated runtime function call.
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The only way to check for asynchronous errors just after some asynchronous
function call is therefore to synchronize just after the call by calling
cudaThreadSynchronize() (or by using any other synchronization
mechanisms described in Section 3.2.6) and checking the error code returned by
cudaThreadSynchronize().
The runtime maintains an error variable for each host thread that is initialized to
cudaSuccess and is overwritten by the error code every time an error occurs (be
it a parameter validation error or an asynchronous error).
cudaPeekAtLastError() returns this variable. cudaGetLastError() returns
this variable and resets it to cudaSuccess.
Kernel launches do not return any error code, so cudaPeekAtLastError() or
cudaGetLastError() must be called just after the kernel launch to retrieve any
pre-launch errors. To ensure that any error returned by
cudaPeekAtLastError() or cudaGetLastError() does not originate from
calls prior to the kernel launch, one has to make sure that the runtime error variable
is set to cudaSuccess just before the kernel launch, for example, by calling
cudaGetLastError() just before the kernel launch. Kernel launches are
asynchronous, so to check for asynchronous errors, the application must
synchronize in-between the kernel launch and the call to
cudaPeekAtLastError() or cudaGetLastError().
Note that cudaErrorNotReady that may be returned by cudaStreamQuery()
and cudaEventQuery() is not considered an error and is therefore not reported
by cudaPeekAtLastError() or cudaGetLastError().
3.2.9 Call Stack
On devices of compute capability 2.x, the size of the call stack can be queried using
cudaThreadGetLimit() and set using cudaThreadSetLimit().
When the call stack overflows, the kernel call fails with a stack overflow error if the
application is run via a CUDA debugger (cuda-gdb, Parallel Nsight) or an
unspecified launch error, otherwise.
3.3 Driver API
The driver API is a handle-based, imperative API: Most objects are referenced by
opaque handles that may be specified to functions to manipulate the objects.
The objects available in the driver API are summarized in Table 3-1.
Table 3-1. Objects Available in the CUDA Driver API
Object Handle Description
Device CUdevice CUDA-enabled device
Context CUcontext Roughly equivalent to a CPU process
Module CUmodule Roughly equivalent to a dynamic library
Function CUfunction Kernel
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Heap memory CUdeviceptr Pointer to device memory
CUDA array CUarray Opaque container for one-dimensional or two-dimensional
data on the device, readable via texture or surface
references
Texture reference CUtexref Object that describes how to interpret texture memory data
Surface reference CUsurfref Object that describes how to read or write CUDA arrays
The driver API is implemented in the nvcuda dynamic library and all its entry
points are prefixed with cu.
The driver API must be initialized with cuInit() before any function from the
driver API is called. A CUDA context must then be created that is attached to a
specific device and made current to the calling host thread as detailed in
Section 3.3.1.
Within a CUDA context, kernels are explicitly loaded as PTX or binary objects by
the host code as described in Section 3.3.2. Kernels written in C must therefore be
compiled separately into PTX or binary objects. Kernels are launched using API
entry points as described in Section 3.3.3.
Any application that wants to run on future device architectures must load PTX, not
binary code. This is because binary code is architecture-specific and therefore
incompatible with future architectures, whereas PTX code is compiled to binary
code at load time by the driver.
Here is the host code of the sample from Section 2.1 written using the driver API:
int main()
{
int N = ...;
size_t size = N * sizeof(float);

// Allocate input vectors h_A and h_B in host memory
float* h_A = (float*)malloc(size);
float* h_B = (float*)malloc(size);

// Initialize input vectors
...

// Initialize
cuInit(0);

// Get number of devices supporting CUDA
int deviceCount = 0;
cuDeviceGetCount(&deviceCount);
if (deviceCount == 0) {
printf("There is no device supporting CUDA.\n");
exit (0);
}

// Get handle for device 0
CUdevice cuDevice;
cuDeviceGet(&cuDevice, 0);

// Create context
CUcontext cuContext;
cuCtxCreate(&cuContext, 0, cuDevice);
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// Create module from binary file
CUmodule cuModule;
cuModuleLoad(&cuModule, “VecAdd.ptx”);

// Allocate vectors in device memory
CUdeviceptr d_A;
cuMemAlloc(&d_A, size);
CUdeviceptr d_B;
cuMemAlloc(&d_B, size);
CUdeviceptr d_C;
cuMemAlloc(&d_C, size);

// Copy vectors from host memory to device memory
cuMemcpyHtoD(d_A, h_A, size);
cuMemcpyHtoD(d_B, h_B, size);

// Get function handle from module
CUfunction vecAdd;
cuModuleGetFunction(&vecAdd, cuModule, "VecAdd");

// Invoke kernel
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(d_A));
cuParamSetv(vecAdd, offset, &d_A, sizeof(d_A));
offset += sizeof(d_A);
ALIGN_UP(offset, __alignof(d_B));
cuParamSetv(vecAdd, offset, &d_B, sizeof(d_B));
offset += sizeof(d_B);
ALIGN_UP(offset, __alignof(d_C));
cuParamSetv(vecAdd, offset, &d_C, sizeof(d_C));
offset += sizeof(d_C);
ALIGN_UP(offset, __alignof(N));
cuParamSeti(vecAdd, offset, N);
offset += sizeof(N);
cuParamSetSize(vecAdd, offset);
int threadsPerBlock = 256;
int blocksPerGrid =
(N + threadsPerBlock – 1) / threadsPerBlock;
cuFuncSetBlockShape(vecAdd, threadsPerBlock, 1, 1);
cuLaunchGrid(vecAdd, blocksPerGrid, 1);

...
}
Full code can be found in the vectorAddDrv SDK code sample.
3.3.1 Context
A CUDA context is analogous to a CPU process. All resources and actions
performed within the driver API are encapsulated inside a CUDA context, and the
system automatically cleans up these resources when the context is destroyed.
Besides objects such as modules and texture or surface references, each context has
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its own distinct 32-bit address space. As a result, CUdeviceptr values from
different contexts reference different memory locations.
A host thread may have only one device context current at a time. When a context is
created with cuCtxCreate(), it is made current to the calling host thread. CUDA
functions that operate in a context (most functions that do not involve device
enumeration or context management) will return
CUDA_ERROR_INVALID_CONTEXT if a valid context is not current to the thread.
Each host thread has a stack of current contexts. cuCtxCreate() pushes the new
context onto the top of the stack. cuCtxPopCurrent() may be called to detach
the context from the host thread. The context is then "floating" and may be pushed
as the current context for any host thread. cuCtxPopCurrent() also restores the
previous current context, if any.
A usage count is also maintained for each context. cuCtxCreate() creates a
context with a usage count of 1. cuCtxAttach() increments the usage count and
cuCtxDetach() decrements it. A context is destroyed when the usage count goes
to 0 when calling cuCtxDetach() or cuCtxDestroy().
Usage count facilitates interoperability between third party authored code operating
in the same context. For example, if three libraries are loaded to use the same
context, each library would call cuCtxAttach() to increment the usage count and
cuCtxDetach() to decrement the usage count when the library is done using the
context. For most libraries, it is expected that the application will have created a
context before loading or initializing the library; that way, the application can create
the context using its own heuristics, and the library simply operates on the context
handed to it. Libraries that wish to create their own contexts – unbeknownst to their
API clients who may or may not have created contexts of their own – would use
cuCtxPushCurrent() and cuCtxPopCurrent() as illustrated in Figure 3-3.

Figure 3-3. Library Context Management
3.3.2 Module
Modules are dynamically loadable packages of device code and data, akin to DLLs in
Windows, that are output by nvcc (see Section 3.1). The names for all symbols,
including functions, global variables, and texture or surface references, are
Library Initialization Call
cuCtxCreate()
Initialize
context
cuCtxPopCurrent()
Library Call
cuCtxPushCurrent()
Use
context
cuCtxPopCurrent()
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maintained at module scope so that modules written by independent third parties
may interoperate in the same CUDA context.
This code sample loads a module and retrieves a handle to some kernel:
CUmodule cuModule;
cuModuleLoad(&cuModule, “myModule.ptx”);
CUfunction myKernel;
cuModuleGetFunction(&myKernel, cuModule, “MyKernel”);
This code sample compiles and loads a new module from PTX code and parses
compilation errors:
#define ERROR_BUFFER_SIZE 100
CUmodule cuModule;
CUjit_option options[3];
void* values[3];
char* PTXCode = “some PTX code”;
options[0] = CU_ASM_ERROR_LOG_BUFFER;
values[0] = (void*)malloc(ERROR_BUFFER_SIZE);
options[1] = CU_ASM_ERROR_LOG_BUFFER_SIZE_BYTES;
values[1] = (void*)ERROR_BUFFER_SIZE;
options[2] = CU_ASM_TARGET_FROM_CUCONTEXT;
values[2] = 0;
cuModuleLoadDataEx(&cuModule, PTXCode, 3, options, values);
for (int i = 0; i < values[1]; ++i) {
// Parse error string here
}
3.3.3 Kernel Execution
cuFuncSetBlockShape() sets the number of threads per block for a given
function, and how their threadIDs are assigned.
cuFuncSetSharedSize() sets the size of shared memory for the function.
The cuParam*() family of functions is used to specify the parameters that will be
provided to the kernel the next time cuLaunchGrid() or cuLaunch() is
invoked to launch the kernel.
The second argument of each of the cuParam*() functions specifies the offset of
the parameter in the parameter stack. This offset must match the alignment
requirement for the parameter type in device code.
Alignment requirements in device code for the built-in vector types are listed in
Table B-1. For all other basic types, the alignment requirement in device code
matches the alignment requirement in host code and can therefore be obtained
using __alignof(). The only exception is when the host compiler aligns double
and long long (and long on a 64-bit system) on a one-word boundary instead of
a two-word boundary (for example, using gcc‟s compilation flag -mno-align-
double) since in device code these types are always aligned on a two-word
boundary.
CUdeviceptr is an integer, but represents a pointer, so its alignment requirement
is __alignof(void*).
The following code sample uses a macro to adjust the offset of each parameter to
meet its alignment requirement.
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#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;

int i;
ALIGN_UP(offset, __alignof(i));
cuParamSeti(cuFunction, offset, i);
offset += sizeof(i);

float4 f4;
ALIGN_UP(offset, 16); // float4‟s alignment is 16
cuParamSetv(cuFunction, offset, &f4, sizeof(f4));
offset += sizeof(f4);

char c;
ALIGN_UP(offset, __alignof(c));
cuParamSeti(cuFunction, offset, c);
offset += sizeof(c);

float f;
ALIGN_UP(offset, __alignof(f));
cuParamSetf(cuFunction, offset, f);
offset += sizeof(f);

CUdeviceptr dptr;
ALIGN_UP(offset, __alignof(dptr));
cuParamSetv(cuFunction, offset, &dptr, sizeof(dptr));
offset += sizeof(dptr);

float2 f2;
ALIGN_UP(offset, 8); // float2‟s alignment is 8
cuParamSetv(cuFunction, offset, &f2, sizeof(f2));
offset += sizeof(f2);

cuParamSetSize(cuFunction, offset);

cuFuncSetBlockShape(cuFunction, blockWidth, blockHeight, 1);
cuLaunchGrid(cuFunction, gridWidth, gridHeight);
The alignment requirement of a structure is equal to the maximum of the alignment
requirements of its fields. The alignment requirement of a structure that contains
built-in vector types, CUdeviceptr, or non-aligned double and long long,
might therefore differ between device code and host code. Such a structure might
also be padded differently. The following structure, for example, is not padded at all
in host code, but it is padded in device code with 12 bytes after field f since the
alignment requirement for field f4 is 16.
typedef struct {
float f;
float4 f4;
} myStruct;
Any parameter of type myStruct must therefore be passed using separate calls to
cuParam*(), such as:
myStruct s;
int offset = 0;

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cuParamSetv(cuFunction, offset, &s.f, sizeof(s.f));
offset += sizeof(s.f);

ALIGN_UP(offset, 16); // float4‟s alignment is 16
cuParamSetv(cuFunction, offset, &s.f4, sizeof(s.f4));
offset += sizeof(s.f4);
3.3.4 Device Memory
Linear memory is allocated using cuMemAlloc() or cuMemAllocPitch() and
freed using cuMemFree().
Here is the host code of the sample from Section 3.2.1 written using the driver API:
// Host code
int main()
{
// Initialize
if (cuInit(0) != CUDA_SUCCESS)
exit (0);

// Get number of devices supporting CUDA
int deviceCount = 0;
cuDeviceGetCount(&deviceCount);
if (deviceCount == 0) {
printf("There is no device supporting CUDA.\n");
exit (0);
}

// Get handle for device 0
CUdevice cuDevice = 0;
cuDeviceGet(&cuDevice, 0);

// Create context
CUcontext cuContext;
cuCtxCreate(&cuContext, 0, cuDevice);

// Create module from binary file
CUmodule cuModule;
cuModuleLoad(&cuModule, “VecAdd.ptx”);

// Get function handle from module
CUfunction vecAdd;
cuModuleGetFunction(&vecAdd, cuModule, "VecAdd");

// Allocate vectors in device memory
size_t size = N * sizeof(float);
CUdeviceptr d_A;
cuMemAlloc(&d_A, size);
CUdeviceptr d_B;
cuMemAlloc(&d_B, size);
CUdeviceptr d_C;
cuMemAlloc(&d_C, size);

// Copy vectors from host memory to device memory
// h_A and h_B are input vectors stored in host memory
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cuMemcpyHtoD(d_A, h_A, size);
cuMemcpyHtoD(d_B, h_B, size);

// Invoke kernel
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(d_A));
cuParamSetv(vecAdd, offset, &d_A, sizeof(d_A));
offset += sizeof(d_A);
ALIGN_UP(offset, __alignof(d_B));
cuParamSetv(vecAdd, offset, &d_B, sizeof(d_B));
offset += sizeof(d_B);
ALIGN_UP(offset, __alignof(d_C));
cuParamSetv(vecAdd, offset, &d_C, sizeof(d_C));
offset += sizeof(d_C);
cuParamSetSize(VecAdd, offset);
int threadsPerBlock = 256;
int blocksPerGrid =
(N + threadsPerBlock – 1) / threadsPerBlock;
cuFuncSetBlockShape(vecAdd, threadsPerBlock, 1, 1);
cuLaunchGrid(VecAdd, blocksPerGrid, 1);

// Copy result from device memory to host memory
// h_C contains the result in host memory
cuMemcpyDtoH(h_C, d_C, size);

// Free device memory
cuMemFree(d_A);
cuMemFree(d_B);
cuMemFree(d_C);
}
Linear memory can also be allocated through cuMemAllocPitch(). This function
is recommended for allocations of 2D arrays as it makes sure that the allocation is
appropriately padded to meet the alignment requirements described in
Section 5.3.2.1, therefore ensuring best performance when accessing the row
addresses or performing copies between 2D arrays and other regions of device
memory (using the cuMemcpy2D()). The returned pitch (or stride) must be used to
access array elements. The following code sample allocates a width×height 2D
array of floating-point values and shows how to loop over the array elements in
device code:
// Host code (assuming cuModule has been loaded)
CUdeviceptr devPtr;
size_t pitch;
cuMemAllocPitch(&devPtr, &pitch,
width * sizeof(float), height, 4);
CUfunction myKernel;
cuModuleGetFunction(&myKernel, cuModule, “MyKernel”);
cuParamSetv(myKernel, 0, &devPtr, sizeof(devPtr));
cuParamSetSize(myKernel, sizeof(devPtr));
cuFuncSetBlockShape(myKernel, 512, 1, 1);
cuLaunchGrid(myKernel, 100, 1);

// Device code
__global__ void MyKernel(float* devPtr)
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{
for (int r = 0; r < height; ++r) {
float* row = (float*)((char*)devPtr + r * pitch);
for (int c = 0; c < width; ++c) {
float element = row[c];
}
}
}
The following code sample allocates a width×height CUDA array of one 32-bit
floating-point component:
CUDA_ARRAY_DESCRIPTOR desc;
desc.Format = CU_AD_FORMAT_FLOAT;
desc.NumChannels = 1;
desc.Width = width;
desc.Height = height;
CUarray cuArray;
cuArrayCreate(&cuArray, &desc);
The reference manual lists all the various functions used to copy memory between
linear memory allocated with cuMemAlloc(), linear memory allocated with
cuMemAllocPitch(), and CUDA arrays.
The following code sample copies the 2D array to the CUDA array allocated in the
previous code samples:
CUDA_MEMCPY2D copyParam;
memset(&copyParam, 0, sizeof(copyParam));
copyParam.dstMemoryType = CU_MEMORYTYPE_ARRAY;
copyParam.dstArray = cuArray;
copyParam.srcMemoryType = CU_MEMORYTYPE_DEVICE;
copyParam.srcDevice = devPtr;
copyParam.srcPitch = pitch;
copyParam.WidthInBytes = width * sizeof(float);
copyParam.Height = height;
cuMemcpy2D(&copyParam);
The following code sample illustrates various ways of accessing global variables via
the driver API:
CUdeviceptr devPtr;
size_t bytes;

__constant__ float constData[256];
float data[256];
cuModuleGetGlobal(&devPtr, &bytes, cuModule, “constData”);
cuMemcpyHtoD(devPtr, data, bytes);
cuMemcpyDtoH(data, devPtr, bytes);

__device__ float devData;
float value = 3.14f;
cuModuleGetGlobal(&devPtr, &bytes, cuModule, “devData”);
cuMemcpyHtoD(devPtr, &value, sizeof(float));

__device__ float* devPointer;
CUdeviceptr ptr;
cuMemAlloc(&ptr, 256 * sizeof(float));
cuModuleGetGlobal(&devPtr, &bytes, cuModule, “devPointer”);
cuMemcpyHtoD(devPtr, &ptr, sizeof(ptr));
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3.3.5 Shared Memory
The following code sample is the driver version of the host code of the sample from
Section 3.2.2.
In this sample, shared memory is statically allocated within the kernel as opposed to
allocated at runtime through cuFuncSetSharedSize().
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.stride + col)
typedef struct {
int width;
int height;
int stride;
float* elements;
} Matrix;

// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
CUdeviceptr elements;
// Load A and B to device memory
Matrix d_A;
d_A.width = d_A.stride = A.width; d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cuMemAlloc(&elements, size);
cuMemcpyHtoD(elements, A.elements, size);
d_A.elements = (float*)elements;

Matrix d_B;
d_B.width = d_B.stride = B.width; d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cuMemAlloc(elements, size);
cuMemcpyHtoD(elements, B.elements, size);
d_B.elements = (float*)elements;

// Allocate C in device memory
Matrix d_C;
d_C.width = d_C.stride = C.width; d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cuMemAlloc(&elements, size);
d_C.elements = (float*)elements;

// Invoke kernel (assuming cuModule has been loaded)
CUfunction matMulKernel;
cuModuleGetFunction(&matMulKernel, cuModule, "MatMulKernel");
int offset = 0;
cuParamSetv(matMulKernel, offset, &d_A, sizeof(d_A));
offset += sizeof(d_A);
cuParamSetv(matMulKernel, offset, &d_B, sizeof(d_B));
offset += sizeof(d_B);
cuParamSetv(matMulKernel, offset, &d_C, sizeof(d_C));
offset += sizeof(d_C);
cuParamSetSize(matMulKernel, offset);
cuFuncSetBlockShape(matMulKernel, BLOCK_SIZE, BLOCK_SIZE, 1);
cuLaunchGrid(matMulKernel,
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B.width / dimBlock.x, A.height / dimBlock.y);

// Read C from device memory
cuMemcpyDtoH(C.elements, (CUdeviceptr)d_C.elements, size);

// Free device memory
cuMemFree((CUdeviceptr)d_A.elements);
cuMemFree((CUdeviceptr)d_B.elements);
cuMemFree((CUdeviceptr)d_C.elements);
}
3.3.6 Multiple Devices
cuDeviceGetCount() and cuDeviceGet() provide a way to enumerate the
devices present in the system and other functions (described in the reference
manual) to retrieve their properties:
int deviceCount;
cuDeviceGetCount(&deviceCount);
int device;
for (int device = 0; device < deviceCount; ++device) {
CUdevice cuDevice;
cuDeviceGet(&cuDevice, device);
int major, minor;
cuDeviceComputeCapability(&major, &minor, cuDevice);
}
3.3.7 Texture and Surface Memory
3.3.7.1 Texture Memory
Texure binding is done using cuTexRefSetAddress() for linear memory and
cuTexRefSetArray() for CUDA arrays.
If a module cuModule contains some texture reference texRef defined as
texture<float, 2, cudaReadModeElementType> texRef;
the following code sample retrieves texRef„s handle:
CUtexref cuTexRef;
cuModuleGetTexRef(&cuTexRef, cuModule, “texRef”);
The following code sample binds texRef to some linear memory pointed to by
devPtr:
CUDA_ARRAY_DESCRIPTOR desc;
cuTexRefSetAddress2D(cuTexRef, &desc, devPtr, pitch);
The following code samples bind texRef to a CUDA array cuArray:
cuTexRefSetArray(cuTexRef, cuArray, CU_TRSA_OVERRIDE_FORMAT);
The reference manual lists various functions used to set address mode, filter mode,
format, and other flags for some texture reference. The format specified when
binding a texture to a texture reference must match the parameters specified when
declaring the texture reference; otherwise, the results of texture fetches are
undefined.
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The following code sample is the driver version of the host code of the sample from
Section 3.2.4.1.3.
// Host code
int main()
{
// Allocate CUDA array in device memory
CUarray cuArray;
CUDA_ARRAY_DESCRIPTOR desc;
desc.Format = CU_AD_FORMAT_FLOAT;
desc.NumChannels = 1;
desc.Width = width;
desc.Height = height;
cuArrayCreate(&cuArray, &desc);

// Copy to device memory some data located at address h_data
// in host memory
CUDA_MEMCPY2D copyParam;
memset(&copyParam, 0, sizeof(copyParam));
copyParam.dstMemoryType = CU_MEMORYTYPE_ARRAY;
copyParam.dstArray = cuArray;
copyParam.srcMemoryType = CU_MEMORYTYPE_HOST;
copyParam.srcHost = h_data;
copyParam.srcPitch = width * sizeof(float);
copyParam.WidthInBytes = copyParam.srcPitch;
copyParam.Height = height;
cuMemcpy2D(&copyParam);

// Set texture parameters
CUtexref texRef;
cuModuleGetTexRef(&texRef, cuModule, "texRef"));
cuTexRefSetAddressMode(texRef, 0, CU_TR_ADDRESS_MODE_WRAP);
cuTexRefSetAddressMode(texRef, 1, CU_TR_ADDRESS_MODE_WRAP);
cuTexRefSetFilterMode(texRef, CU_TR_FILTER_MODE_LINEAR);
cuTexRefSetFlags(texRef, CU_TRSF_NORMALIZED_COORDINATES);
cuTexRefSetFormat(texRef, CU_AD_FORMAT_FLOAT, 1);

// Bind the array to the texture reference
cuTexRefSetArray(texRef, cuArray, CU_TRSA_OVERRIDE_FORMAT);

// Allocate result of transformation in device memory
CUdeviceptr output;
cuMemAlloc(&output, width * height * sizeof(float));

// Invoke kernel (assuming cuModule has been loaded)
CUfunction transformKernel;
cuModuleGetFunction(&transformKernel,
cuModule, "transformKernel");
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(output));
cuParamSetv(transformKernel, offset, &output, sizeof(output));
offset += sizeof(output);
ALIGN_UP(offset, __alignof(width));
cuParamSeti(transformKernel, offset, width);
offset += sizeof(width);
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ALIGN_UP(offset, __alignof(height));
cuParamSeti(transformKernel, offset, height);
offset += sizeof(height);
ALIGN_UP(offset, __alignof(angle));
cuParamSetf(transformKernel, offset, angle);
offset += sizeof(angle);
cuParamSetSize(transformKernel, offset));
cuFuncSetBlockShape(transformKernel, 16, 16, 1);
cuLaunchGrid(transformKernel,
(width + dimBlock.x – 1) / dimBlock.x,
(height + dimBlock.y – 1) / dimBlock.y);

// Free device memory
cuArrayDestroy(cuArray);
cuMemFree(output);
}
3.3.7.2 Surface Memory
Surface binding is done using cuSurfRefSetArray() for CUDA arrays.
If a module cuModule contains some surface reference surfRef defined as
surface<void, 2> surfRef;
the following code sample retrieves surfRef„s handle:
CUsurfref cuSurfRef;
cuModuleGetSurfRef(&cuSurfRef, cuModule, “surfRef”);
The following code samples bind surfRef to a CUDA array cuArray:
cuSurfRefSetArray(cuSurfRef, cuArray, CU_SRSA_USE_ARRAY_FORMAT);
The following code sample is the driver version of the host code of the sample from
Section 3.2.4.1.4.
// Host code
int main()
{
// Allocate CUDA arrays in device memory
CUDA_ARRAY_DESCRIPTOR desc;
desc.Format = CU_AD_FORMAT_UNSIGNED_INT8;
desc.NumChannels = 4;
desc.Width = width;
desc.Height = height;
CUarray cuInputArray;
cuArrayCreate(&cuInputArray, &desc);
CUarray cuOutputArray;
cuArrayCreate(&cuOutputArray, &desc);

// Copy to device memory some data located at address h_data
// in host memory
CUDA_MEMCPY2D copyParam;
memset(&copyParam, 0, sizeof(copyParam));
copyParam.dstMemoryType = CU_MEMORYTYPE_ARRAY;
copyParam.dstArray = cuInputArray;
copyParam.srcMemoryType = CU_MEMORYTYPE_HOST;
copyParam.srcHost = h_data;
copyParam.srcPitch = width * sizeof(float);
copyParam.WidthInBytes = copyParam.srcPitch;
copyParam.Height = height;
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cuMemcpy2D(&copyParam);

// Bind the arrays to the surface references
cuSurfRefSetArray(inputSurfRef, cuInputArray,
CU_SRSA_USE_ARRAY_FORMAT);
cuSurfRefSetArray(outputSurfRef, cuOutputArray,
CU_SRSA_USE_ARRAY_FORMAT);

// Invoke kernel (assuming cuModule has been loaded)
CUfunction copyKernel;
cuModuleGetFunction(&copyKernel,
cuModule, "copyKernel");
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(width));
cuParamSeti(copyKernel, offset, width);
offset += sizeof(width);
ALIGN_UP(offset, __alignof(height));
cuParamSeti(copyKernel, offset, height);
offset += sizeof(height);
cuParamSetSize(copyKernel, offset));
cuFuncSetBlockShape(copyKernel, 16, 16, 1);
cuLaunchGrid(copyKernel,
(width + dimBlock.x – 1) / dimBlock.x,
(height + dimBlock.y – 1) / dimBlock.y);

// Free device memory
cuArrayDestroy(cuInputArray);
cuArrayDestroy(cuOutputArray);
}
3.3.8 Page-Locked Host Memory
Page-locked host memory can be allocated using cuMemHostAlloc() with
optional mutually non-exclusive flags:
 CU_MEMHOSTALLOC_PORTABLE to allocate memory that is portable across
CUDA contexts (see Section 3.2.5.1);
 CU_MEMHOSTALLOC_WRITECOMBINED to allocate memory as write-
combining (see Section 3.2.5.2);
 CU_MEMHOSTALLOC_DEVICEMAP to allocate mapped page-locked memory
(see Section 3.2.5.3).
Page-locked host memory is freed using cuMemFreeHost().
Page-locked memory mapping is enabled for a CUDA context by creating the
context with the CU_CTX_MAP_HOST flag and device pointers to mapped page-
locked memory are retrieved using cuMemHostGetDevicePointer().
Applications may query whether a device supports mapped page-locked host
memory or not by checking the
CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY attribute using
cuDeviceGetAttribute().
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3.3.9 Asynchronous Concurrent Execution
Applications may query if a device can perform copies between page-locked host
memory and device memory concurrently with kernel execution by checking the
CU_DEVICE_ATTRIBUTE_GPU_OVERLAP attribute using
cuDeviceGetAttribute().
Applications may query if a device supports multiple kernels running concurrently
by checking the CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS attribute using
cuDeviceGetAttribute().
3.3.9.1 Stream
The driver API provides functions similar to the runtime API to manage streams.
The following code sample is the driver version of the code sample from
Section 3.2.6.4.
CUstream stream[2];
for (int i = 0; i < 2; ++i)
cuStreamCreate(&stream[i], 0);
float* hostPtr;
cuMemAllocHost(&hostPtr, 2 * size);

for (int i = 0; i < 2; ++i)
cuMemcpyHtoDAsync(inputDevPtr + i * size, hostPtr + i * size,
size, stream[i]);
for (int i = 0; i < 2; ++i) {
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(outputDevPtr));
cuParamSetv(cuFunction, offset,
&outputDevPtr, sizeof(outputDevPtr));
offset += sizeof(outputDevPtr);
ALIGN_UP(offset, __alignof(inputDevPtr));
cuParamSetv(cuFunction, offset,
&inputDevPtr, sizeof(inputDevPtr));
offset += sizeof(inputDevPtr);
ALIGN_UP(offset, __alignof(size));
cuParamSeti(cuFunction, offset, size);
offset += sizeof(int);
cuParamSetSize(cuFunction, offset);
cuFuncSetBlockShape(cuFunction, 512, 1, 1);
cuLaunchGridAsync(cuFunction, 100, 1, stream[i]);
}
for (int i = 0; i < 2; ++i)
cuMemcpyDtoHAsync(hostPtr + i * size, outputDevPtr + i * size,
size, stream[i]);
cuCtxSynchronize();

for (int i = 0; i < 2; ++i)
cuStreamDestroy(&stream[i]);
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3.3.9.2 Event Management
The driver API provides functions similar to the runtime API to manage events.
The following code sample is the driver version of the code sample from
Section 3.2.6.6.
CUevent start, stop;
cuEventCreate(&start);
cuEventCreate(&stop);

cuEventRecord(start, 0);
for (int i = 0; i < 2; ++i)
cuMemcpyHtoDAsync(inputDevPtr + i * size, hostPtr + i * size,
size, stream[i]);
for (int i = 0; i < 2; ++i) {
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(outputDevPtr));
cuParamSetv(cuFunction, offset,
&outputDevPtr, sizeof(outputDevPtr));
offset += sizeof(outputDevPtr);
ALIGN_UP(offset, __alignof(inputDevPtr));
cuParamSetv(cuFunction, offset,
&inputDevPtr, sizeof(inputDevPtr));
offset += sizeof(inputDevPtr);
ALIGN_UP(offset, __alignof(size));
cuParamSeti(cuFunction, offset, size);
offset += sizeof(size);
cuParamSetSize(cuFunction, offset);
cuFuncSetBlockShape(cuFunction, 512, 1, 1);
cuLaunchGridAsync(cuFunction, 100, 1, stream[i]);
}
for (int i = 0; i < 2; ++i)
cuMemcpyDtoHAsync(hostPtr + i * size, outputDevPtr + i * size,
size, stream[i]);
cuEventRecord(stop, 0);
cuEventSynchronize(stop);
float elapsedTime;
cuEventElapsedTime(&elapsedTime, start, stop);
They are destroyed this way:
cuEventDestroy(start);
cuEventDestroy(stop);
3.3.9.3 Synchronous Calls
Whether the host thread will yield, block, or spin on a synchronous function call can
be specified by calling cuCtxCreate() with some specific flags as described in the
reference manual.
3.3.10 Graphics Interoperability
The driver API provides functions similar to the runtime API to manage graphics
interoperability.
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A resource must be registered to CUDA before it can be mapped using the
functions mentioned in Sections 3.3.10.1 and 3.3.10.2. These functions return a
CUDA graphics resource of type CUgraphicsResource. Registering a resource is
potentially high-overhead and therefore typically called only once per resource. A
CUDA graphics resource is unregistered using
cuGraphicsUnregisterResource().
Once a resource is registered to CUDA, it can be mapped and unmapped as many
times as necessary using cuGraphicsMapResources() and
cuGraphicsUnmapResources(). cuGraphicsResourceSetMapFlags()
can be called to specify usage hints (write-only, read-only) that the CUDA driver can
use to optimize resource management.
A mapped resource can be read from or written to by kernels using the device
memory address returned by cuGraphicsResourceGetMappedPointer() for
buffers and cuGraphicsSubResourceGetMappedArray() for CUDA arrays.
Accessing a resource through OpenGL or Direct3D while it is mapped to CUDA
produces undefined results.
Sections 3.3.10.1 and 3.3.10.2 give specifics for each graphics API and some code
samples.
3.3.10.1 OpenGL Interoperability
Interoperability with OpenGL requires that the CUDA context be specifically
created using cuGLCtxCreate() instead of cuCtxCreate().
The OpenGL resources that may be mapped into the address space of CUDA are
OpenGL buffer, texture, and renderbuffer objects. A buffer object is registered
using cuGraphicsGLRegisterBuffer(). A texture or renderbuffer object is
registered using cuGraphicsGLRegisterImage(). The same restrictions
described in Section 3.2.7.1 apply.
The following code sample is the driver version of the code sample from
Section 3.2.7.1.
CUfunction createVertices;
GLuint positionsVBO;
struct cudaGraphicsResource* positionsVBO_CUDA;

int main()
{
// Initialize driver API
...

// Get handle for device 0
CUdevice cuDevice = 0;
cuDeviceGet(&cuDevice, 0);

// Create context
CUcontext cuContext;
cuGLCtxCreate(&cuContext, 0, cuDevice);

// Create module from binary file
CUmodule cuModule;
cuModuleLoad(&cuModule, “createVertices.ptx”);

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// Get function handle from module
cuModuleGetFunction(&createVertices,
cuModule, "createVertices");

// Initialize OpenGL and GLUT
...
glutDisplayFunc(display);

// Create buffer object and register it with CUDA
glGenBuffers(1, positionsVBO);
glBindBuffer(GL_ARRAY_BUFFER, &vbo);
unsigned int size = width * height * 4 * sizeof(float);
glBufferData(GL_ARRAY_BUFFER, size, 0, GL_DYNAMIC_DRAW);
glBindBuffer(GL_ARRAY_BUFFER, 0);
cuGraphicsGLRegisterBuffer(&positionsVBO_CUDA,
positionsVBO,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
glutMainLoop();
}

void display()
{
// Map OpenGL buffer object for writing from CUDA
CUdeviceptr positions;
cuGraphicsMapResources(1, &positionsVBO_CUDA, 0);
size_t num_bytes;
cuGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVBO_CUDA));

// Execute kernel
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(positions));
cuParamSetv(createVertices, offset,
&positions, sizeof(positions));
offset += sizeof(positions);
ALIGN_UP(offset, __alignof(time));
cuParamSetf(createVertices, offset, time);
offset += sizeof(time);
ALIGN_UP(offset, __alignof(width));
cuParamSeti(createVertices, offset, width);
offset += sizeof(width);
ALIGN_UP(offset, __alignof(height));
cuParamSeti(createVertices, offset, height);
offset += sizeof(height);
cuParamSetSize(createVertices, offset);
int threadsPerBlock = 16;
cuFuncSetBlockShape(createVertices,
threadsPerBlock, threadsPerBlock, 1);
cuLaunchGrid(createVertices,
width / threadsPerBlock, height / threadsPerBlock);

// Unmap buffer object
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cuGraphicsUnmapResources(1, &positionsVBO_CUDA, 0);

// Render from buffer object
glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT);
glBindBuffer(GL_ARRAY_BUFFER, positionsVBO);
glVertexPointer(4, GL_FLOAT, 0, 0);
glEnableClientState(GL_VERTEX_ARRAY);
glDrawArrays(GL_POINTS, 0, width * height);
glDisableClientState(GL_VERTEX_ARRAY);

// Swap buffers
glutSwapBuffers();
glutPostRedisplay();
}

void deleteVBO()
{
cuGraphicsUnregisterResource(positionsVBO_CUDA);
glDeleteBuffers(1, &positionsVBO);
}
On Windows and for Quadro GPUs, cuWGLGetDevice() can be used to retrieve
the CUDA device associated to the handle returned by wglEnumGpusNV().
3.3.10.2 Direct3D Interoperability
Interoperability with Direct3D requires that the Direct3D device be specified when
the CUDA context is created. This is done by creating the CUDA context using
cuD3D9CtxCreate() or cuD3D9CtxCreateOnDevice() (resp.
cuD3D10CtxCreate()or cuD3D10CtxCreateOnDevice() and
cuD3D11CtxCreate()or cuD3D11CtxCreateOnDevice()) instead of
cuCtxCreate().
Two sets of calls are also available to allow the creation of CUDA devices with
interoperability with Direct3D devices that use NVIDIA SLI in AFR (Alternate
Frame Rendering) mode. These two new sets of calls are
cuD3D[9|10|11]CtxCreateOnDevice() and
cuD3D[9|10|11]GetDevices(). A call to
cuD3D[9|10|11]GetDevices()should be used to obtain a list of CUDA device
handles that can be passed as the last parameter to
cuD3D[9|10|11]CtxCreateOnDevice().
Applications that intend to support interoperability between Direct3D devices in
SLI configurations and CUDA should be written to only use these calls instead of
the cuD3D[9|10|11]CtxCreate() calls. In addition, they can call
cuCtxPushCurrent() and cuCtxPopCurrent()to change the CUDA context
active at a given time.
See Section 4.3 for general recommendations related to interoperability between
Direct3D devices using SLI and CUDA contexts.
The Direct3D resources that may be mapped into the address space of CUDA are
Direct3D buffers, textures, and surfaces. These resources are registered using
cuGraphicsD3D9RegisterResource(),
cuGraphicsD3D10RegisterResource(), and
cuGraphicsD3D11RegisterResource().
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The following code sample is the driver version of the host code of the sample from
Section 3.2.7.2.
Direct3D 9 Version:
IDirect3D9* D3D;
IDirect3DDevice9 device;
struct CUSTOMVERTEX {
FLOAT x, y, z;
DWORD color;
};
IDirect3DVertexBuffer9* positionsVB;
struct cudaGraphicsResource* positionsVB_CUDA;

int main()
{
// Initialize Direct3D
D3D = Direct3DCreate9(D3D_SDK_VERSION);

// Get a CUDA-enabled adapter
unsigned int adapter = 0;
for (; adapter < g_pD3D->GetAdapterCount(); adapter++) {
D3DADAPTER_IDENTIFIER9 adapterId;
g_pD3D->GetAdapterIdentifier(adapter, 0, &adapterId);
int dev;
if (cuD3D9GetDevice(&dev, adapterId.DeviceName)
== cudaSuccess)
break;
}

// Create device
...
D3D->CreateDevice(adapter, D3DDEVTYPE_HAL, hWnd,
D3DCREATE_HARDWARE_VERTEXPROCESSING,
&params, &device);

// Initialize driver API
...

// Create context
CUdevice cuDevice;
CUcontext cuContext;
cuD3D9CtxCreate(&cuContext, &cuDevice, 0, device);

// Create module from binary file
CUmodule cuModule;
cuModuleLoad(&cuModule, “createVertices.ptx”);

// Get function handle from module
cuModuleGetFunction(&createVertices,
cuModule, "createVertices");

// Create vertex buffer and register it with CUDA
unsigned int size = width * height * sizeof(CUSTOMVERTEX);
device->CreateVertexBuffer(size, 0, D3DFVF_CUSTOMVERTEX,
D3DPOOL_DEFAULT, &positionsVB, 0);
cuGraphicsD3D9RegisterResource(&positionsVB_CUDA,
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72 CUDA C Programming Guide Version 3.2

positionsVB,
cudaGraphicsRegisterFlagsNone);
cuGraphicsResourceSetMapFlags(positionsVB_CUDA,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
while (...) {
...
Render();
...
}
}

void Render()
{
// Map vertex buffer for writing from CUDA
float4* positions;
cuGraphicsMapResources(1, &positionsVB_CUDA, 0);
size_t num_bytes;
cuGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVB_CUDA));

// Execute kernel
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(positions));
cuParamSetv(createVertices, offset,
&positions, sizeof(positions));
offset += sizeof(positions);
ALIGN_UP(offset, __alignof(time));
cuParamSetf(createVertices, offset, time);
offset += sizeof(time);
ALIGN_UP(offset, __alignof(width));
cuParamSeti(createVertices, offset, width);
offset += sizeof(width);
ALIGN_UP(offset, __alignof(height));
cuParamSeti(createVertices, offset, height);
offset += sizeof(height);
cuParamSetSize(createVertices, offset);
int threadsPerBlock = 16;
cuFuncSetBlockShape(createVertices,
threadsPerBlock, threadsPerBlock, 1);
cuLaunchGrid(createVertices,
width / threadsPerBlock, height / threadsPerBlock);

// Unmap vertex buffer
cuGraphicsUnmapResources(1, &positionsVB_CUDA, 0);

// Draw and present
...
}

void releaseVB()
{
cuGraphicsUnregisterResource(positionsVB_CUDA);
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positionsVB->Release();
}
Direct3D 10 Version:
ID3D10Device* device;
struct CUSTOMVERTEX {
FLOAT x, y, z;
DWORD color;
};
ID3D10Buffer* positionsVB;
struct cudaGraphicsResource* positionsVB_CUDA;

int main()
{
// Get a CUDA-enabled adapter
IDXGIFactory* factory;
CreateDXGIFactory(__uuidof(IDXGIFactory), (void**)&factory);
IDXGIAdapter* adapter = 0;
for (unsigned int i = 0; !adapter; ++i) {
if (FAILED(factory->EnumAdapters(i, &adapter))
break;
int dev;
if (cuD3D10GetDevice(&dev, adapter) == cudaSuccess)
break;
adapter->Release();
}
factory->Release();

// Create swap chain and device
...
D3D10CreateDeviceAndSwapChain(adapter,
D3D10_DRIVER_TYPE_HARDWARE, 0,
D3D10_CREATE_DEVICE_DEBUG,
D3D10_SDK_VERSION,
&swapChainDesc &swapChain,
&device);
adapter->Release();

// Initialize driver API
...

// Create context
CUdevice cuDevice;
CUcontext cuContext;
cuD3D10CtxCreate(&cuContext, &cuDevice, 0, device);

// Create module from binary file
CUmodule cuModule;
cuModuleLoad(&cuModule, “createVertices.ptx”);

// Get function handle from module
cuModuleGetFunction(&createVertices,
cuModule, "createVertices");

// Create vertex buffer and register it with CUDA
unsigned int size = width * height * sizeof(CUSTOMVERTEX);
D3D10_BUFFER_DESC bufferDesc;
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74 CUDA C Programming Guide Version 3.2

bufferDesc.Usage = D3D10_USAGE_DEFAULT;
bufferDesc.ByteWidth = size;
bufferDesc.BindFlags = D3D10_BIND_VERTEX_BUFFER;
bufferDesc.CPUAccessFlags = 0;
bufferDesc.MiscFlags = 0;
device->CreateBuffer(&bufferDesc, 0, &positionsVB);
cuGraphicsD3D10RegisterResource(&positionsVB_CUDA,
positionsVB,
cudaGraphicsRegisterFlagsNone);
cuGraphicsResourceSetMapFlags(positionsVB_CUDA,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
while (...) {
...
Render();
...
}
}

void Render()
{
// Map vertex buffer for writing from CUDA
float4* positions;
cuGraphicsMapResources(1, &positionsVB_CUDA, 0);
size_t num_bytes;
cuGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVB_CUDA));

// Execute kernel
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(positions));
cuParamSetv(createVertices, offset,
&positions, sizeof(positions));
offset += sizeof(positions);
ALIGN_UP(offset, __alignof(time));
cuParamSetf(createVertices, offset, time);
offset += sizeof(time);
ALIGN_UP(offset, __alignof(width));
cuParamSeti(createVertices, offset, width);
offset += sizeof(width);
ALIGN_UP(offset, __alignof(height));
cuParamSeti(createVertices, offset, height);
offset += sizeof(height);
cuParamSetSize(createVertices, offset);
int threadsPerBlock = 16;
cuFuncSetBlockShape(createVertices,
threadsPerBlock, threadsPerBlock, 1);
cuLaunchGrid(createVertices,
width / threadsPerBlock, height / threadsPerBlock);

// Unmap vertex buffer
cuGraphicsUnmapResources(1, &positionsVB_CUDA, 0);

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// Draw and present
...
}

void releaseVB()
{
cuGraphicsUnregisterResource(positionsVB_CUDA);
positionsVB->Release();
}
Direct3D 11 Version:
ID3D11Device* device;
struct CUSTOMVERTEX {
FLOAT x, y, z;
DWORD color;
};
ID3D11Buffer* positionsVB;
struct cudaGraphicsResource* positionsVB_CUDA;

int main()
{
// Get a CUDA-enabled adapter
IDXGIFactory* factory;
CreateDXGIFactory(__uuidof(IDXGIFactory), (void**)&factory);
IDXGIAdapter* adapter = 0;
for (unsigned int i = 0; !adapter; ++i) {
if (FAILED(factory->EnumAdapters(i, &adapter))
break;
int dev;
if (cuD3D11GetDevice(&dev, adapter) == cudaSuccess)
break;
adapter->Release();
}
factory->Release();

// Create swap chain and device
...
sFnPtr_D3D11CreateDeviceAndSwapChain(adapter,
D3D11_DRIVER_TYPE_HARDWARE,
0,
D3D11_CREATE_DEVICE_DEBUG,
featureLevels, 3,
D3D11_SDK_VERSION,
&swapChainDesc, &swapChain,
&device,
&featureLevel,
&deviceContext);
adapter->Release();

// Initialize driver API
...

// Create context
CUdevice cuDevice;
CUcontext cuContext;
cuD3D11CtxCreate(&cuContext, &cuDevice, 0, device);

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// Create module from binary file
CUmodule cuModule;
cuModuleLoad(&cuModule, “createVertices.ptx”);

// Get function handle from module
cuModuleGetFunction(&createVertices,
cuModule, "createVertices");

// Create vertex buffer and register it with CUDA
unsigned int size = width * height * sizeof(CUSTOMVERTEX);
D3D11_BUFFER_DESC bufferDesc;
bufferDesc.Usage = D3D11_USAGE_DEFAULT;
bufferDesc.ByteWidth = size;
bufferDesc.BindFlags = D3D10_BIND_VERTEX_BUFFER;
bufferDesc.CPUAccessFlags = 0;
bufferDesc.MiscFlags = 0;
device->CreateBuffer(&bufferDesc, 0, &positionsVB);
cuGraphicsD3D11RegisterResource(&positionsVB_CUDA,
positionsVB,
cudaGraphicsRegisterFlagsNone);
cuGraphicsResourceSetMapFlags(positionsVB_CUDA,
cudaGraphicsMapFlagsWriteDiscard);

// Launch rendering loop
while (...) {
...
Render();
...
}
}

void Render()
{
// Map vertex buffer for writing from CUDA
float4* positions;
cuGraphicsMapResources(1, &positionsVB_CUDA, 0);
size_t num_bytes;
cuGraphicsResourceGetMappedPointer((void**)&positions,
&num_bytes,
positionsVB_CUDA));

// Execute kernel
#define ALIGN_UP(offset, alignment) \
(offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1)
int offset = 0;
ALIGN_UP(offset, __alignof(positions));
cuParamSetv(createVertices, offset,
&positions, sizeof(positions));
offset += sizeof(positions);
ALIGN_UP(offset, __alignof(time));
cuParamSetf(createVertices, offset, time);
offset += sizeof(time);
ALIGN_UP(offset, __alignof(width));
cuParamSeti(createVertices, offset, width);
offset += sizeof(width);
ALIGN_UP(offset, __alignof(height));
cuParamSeti(createVertices, offset, height);
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offset += sizeof(height);
cuParamSetSize(createVertices, offset);
int threadsPerBlock = 16;
cuFuncSetBlockShape(createVertices,
threadsPerBlock, threadsPerBlock, 1);
cuLaunchGrid(createVertices,
width / threadsPerBlock, height / threadsPerBlock);

// Unmap vertex buffer
cuGraphicsUnmapResources(1, &positionsVB_CUDA, 0);

// Draw and present
...
}

void releaseVB()
{
cuGraphicsUnregisterResource(positionsVB_CUDA);
positionsVB->Release();
}
3.3.11 Error Handling
All driver functions return an error code, but for an asynchronous function (see
Section 3.2.6), this error code cannot possibly report any of the asynchronous errors
that could occur on the device since the function returns before the device has
completed the task; the error code only reports errors that occur on the host prior
to executing the task, typically related to parameter validation; if an asynchronous
error occurs, it will be reported by some subsequent unrelated runtime function call.
The only way to check for asynchronous errors just after some asynchronous
function call is therefore to synchronize just after the call by calling
cuCtxSynchronize() (or by using any other synchronization mechanisms
described in Section 3.3.9) and checking the error code returned by
cuCtxSynchronize().
3.3.12 Call Stack
On devices of compute capability 2.x, the size of the call stack can be queried using
cuCtxGetLimit() and set using cuCtxSetLimit().
3.4 Interoperability between Runtime and Driver
APIs
An application can mix runtime API code with driver API code.
If a context is created and made current via the driver API, subsequent runtime calls
will pick up this context instead of creating a new one.
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If the runtime is initialized (implicitly as mentioned in Section 3.2),
cuCtxAttach() can be used to retrieve the context created during initialization.
This context can be used by subsequent driver API calls.
Device memory can be allocated and freed using either API. CUdeviceptr can be
cast to regular pointers and vice-versa:
CUdeviceptr devPtr;
float* d_data;

// Allocation using driver API
cuMemAlloc(&devPtr, size);
d_data = (float*)devPtr;

// Allocation using runtime API
cudaMalloc(&d_data, size);
devPtr = (CUdeviceptr)d_data;
In particular, this means that applications written using the driver API can invoke
libraries written using the runtime API (such as CUFFT, CUBLAS, …).
All functions from the device and version management sections of the reference
manual can be used interchangeably.
3.5 Versioning and Compatibility
There are two version numbers that developers should care about when developing
a CUDA application: The compute capability that describes the general
specifications and features of the compute device (see Section 2.5) and the version
of the CUDA driver API that describes the features supported by the driver API
and runtime.
The version of the driver API is defined in the driver header file as
CUDA_VERSION. It allows developers to check whether their application requires a
newer driver than the one currently installed. This is important, because the driver
API is backward compatible, meaning that applications, plug-ins, and libraries
(including the C runtime) compiled against a particular version of the driver API will
continue to work on subsequent driver releases as illustrated in Figure 3-4. The
driver API is not forward compatible, which means that applications, plug-ins, and
libraries (including the C runtime) compiled against a particular version of the driver
API will not work on previous versions of the driver.
It is important to note that mixing and matching versions is not supported;
specifically:
 All applications, plug-ins, and libraries on a system must use the same version of
the CUDA driver API, since only one version of the CUDA driver can be
installed on a system.
 All plug-ins and libraries used by an application must use the same version of
the runtime.
 All plug-ins and libraries used by an application must use the same version of
any libraries that use the runtime (such as CUFFT, CUBLAS, …).

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1.0
Driver
Apps,
Libs &
Plug-ins
1.1
Driver
Apps,
Libs &
Plug-ins
2.0
Driver
Apps,
Libs &
Plug-ins
Compatible Incompatible
...
...

Figure 3-4. The Driver API is Backward, but Not Forward
Compatible
3.6 Compute Modes
On Tesla solutions running Linux, one can set any device in a system in one of the
three following modes using NVIDIA‟s System Management Interface (nvidia-smi),
which is a tool distributed as part of the Linux driver:
 Default compute mode: Multiple host threads can use the device (by calling
cudaSetDevice() on this device, when using the runtime API, or by making
current a context associated to the device, when using the driver API) at the
same time.
 Exclusive compute mode: Only one host thread can use the device at any given
time.
 Prohibited compute mode: No host thread can use the device.
This means, in particular, that a host thread using the runtime API without explicitly
calling cudaSetDevice() might be associated with a device other than device 0 if
device 0 turns out to be in prohibited compute mode or in exclusive compute mode
and used by another host thread. cudaSetValidDevices() can be used to set a
device from a prioritized list of devices.
Applications may query the compute mode of a device by calling
cudaGetDeviceProperties() and checking the computeMode property or
checking the CU_DEVICE_COMPUTE_MODE attribute using
cuDeviceGetAttribute().
3.7 Mode Switches
GPUs dedicate some DRAM memory to the so-called primary surface, which is used
to refresh the display device whose output is viewed by the user. When users initiate
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a mode switch of the display by changing the resolution or bit depth of the display
(using NVIDIA control panel or the Display control panel on Windows), the
amount of memory needed for the primary surface changes. For example, if the user
changes the display resolution from 1280x1024x32-bit to 1600x1200x32-bit, the
system must dedicate 7.68 MB to the primary surface rather than 5.24 MB. (Full-
screen graphics applications running with anti-aliasing enabled may require much
more display memory for the primary surface.) On Windows, other events that may
initiate display mode switches include launching a full-screen DirectX application,
hitting Alt+Tab to task switch away from a full-screen DirectX application, or
hitting Ctrl+Alt+Del to lock the computer.
If a mode switch increases the amount of memory needed for the primary surface,
the system may have to cannibalize memory allocations dedicated to CUDA
applications. Therefore, a mode switch results in any call to the CUDA runtime to
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Chapter 4.
Hardware Implementation
The CUDA architecture is built around a scalable array of multithreaded Streaming
Multiprocessors (SMs). When a CUDA program on the host CPU invokes a kernel
grid, the blocks of the grid are enumerated and distributed to multiprocessors with
available execution capacity. The threads of a thread block execute concurrently on
one multiprocessor, and multiple thread blocks can execute concurrently on one
multiprocessor. As thread blocks terminate, new blocks are launched on the vacated
multiprocessors.
A multiprocessor is designed to execute hundreds of threads concurrently. To
manage such a large amount of threads, it employs a unique architecture called
SIMT (Single-Instruction, Multiple-Thread) that is described in Section 4.1. To maximize
utilization of its functional units, it leverages thread-level parallelism by using
hardware multithreading as detailed in Section 4.2, more so than instruction-level
parallelism within a single thread (instructions are pipelined, but unlike CPU cores
they are executed in order and there is no branch prediction and no speculative
execution).
Sections 4.1 and 4.2 describe the architecture features of the streaming
multiprocessor that are common to all devices. Sections G.3.1 and G.4.1 provide the
specifics for devices of compute capabilities 1.x and 2.x, respectively.
4.1 SIMT Architecture
The multiprocessor creates, manages, schedules, and executes threads in groups of
32 parallel threads called warps. Individual threads composing a warp start together
at the same program address, but they have their own instruction address counter
and register state and are therefore free to branch and execute independently. The
term warp originates from weaving, the first parallel thread technology. A half-warp is
either the first or second half of a warp. A quarter-warp is either the first, second,
third, or fourth quarter of a warp.
When a multiprocessor is given one or more thread blocks to execute, it partitions
them into warps that get scheduled by a warp scheduler for execution. The way a block
is partitioned into warps is always the same; each warp contains threads of
consecutive, increasing thread IDs with the first warp containing thread 0.
Section 2.2 describes how thread IDs relate to thread indices in the block.
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A warp executes one common instruction at a time, so full efficiency is realized
when all 32 threads of a warp agree on their execution path. If threads of a warp
diverge via a data-dependent conditional branch, the warp serially executes each
branch path taken, disabling threads that are not on that path, and when all paths
complete, the threads converge back to the same execution path. Branch divergence
occurs only within a warp; different warps execute independently regardless of
whether they are executing common or disjoint code paths.
The SIMT architecture is akin to SIMD (Single Instruction, Multiple Data) vector
organizations in that a single instruction controls multiple processing elements. A
key difference is that SIMD vector organizations expose the SIMD width to the
software, whereas SIMT instructions specify the execution and branching behavior
of a single thread. In contrast with SIMD vector machines, SIMT enables
programmers to write thread-level parallel code for independent, scalar threads, as
well as data-parallel code for coordinated threads. For the purposes of correctness,
the programmer can essentially ignore the SIMT behavior; however, substantial
performance improvements can be realized by taking care that the code seldom
requires threads in a warp to diverge. In practice, this is analogous to the role of
cache lines in traditional code: Cache line size can be safely ignored when designing
for correctness but must be considered in the code structure when designing for
peak performance. Vector architectures, on the other hand, require the software to
coalesce loads into vectors and manage divergence manually.
If a non-atomic instruction executed by a warp writes to the same location in global
or shared memory for more than one of the threads of the warp, the number of
serialized writes that occur to that location varies depending on the compute
capability of the device (see Sections G.3.2, G.3.3, G.4.2, and G.4.3) and which
thread performs the final write is undefined.
If an atomic instruction (see Section B.11) executed by a warp reads, modifies, and
writes to the same location in global memory for more than one of the threads of
the warp, each read, modify, write to that location occurs and they are all serialized,
but the order in which they occur is undefined.
4.2 Hardware Multithreading
The execution context (program counters, registers, etc) for each warp processed by
a multiprocessor is maintained on-chip during the entire lifetime of the warp.
Switching from one execution context to another therefore has no cost, and at every
instruction issue time, a warp scheduler selects a warp that has threads ready to
execute its next instruction (active threads) and issues the instruction to those threads.
In particular, each multiprocessor has a set of 32-bit registers that are partitioned
among the warps, and a parallel data cache or shared memory that is partitioned among
the thread blocks.
The number of blocks and warps that can reside and be processed together on the
multiprocessor for a given kernel depends on the amount of registers and shared
memory used by the kernel and the amount of registers and shared memory
available on the multiprocessor. There are also a maximum number of resident
blocks and a maximum number of resident warps per multiprocessor. These limits
as well the amount of registers and shared memory available on the multiprocessor
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are a function of the compute capability of the device and are given in Appendix G.
If there are not enough registers or shared memory available per multiprocessor to
process at least one block, the kernel will fail to launch.
The total number of warps Wblock in a block is as follows:
) 1 , (
size
block
W
T
ceil W =
 T is the number of threads per block,
 Wsize is the warp size, which is equal to 32,
 ceil(x, y) is equal to x rounded up to the nearest multiple of y.
The total number of registers Rblock allocated for a block is as follows:
For devices of compute capability 1.x:
) , ) , ( (
T k size W block block
G R W G W ceil ceil R × × =

For devices of compute capability 2.x:
block T size k block
W G W R ceil R × × = ) , (
 GW is the warp allocation granularity, equal to 2 (compute capability 1.x only),
 Rk is the number of registers used by the kernel,
 GT is the thread allocation granularity, equal to 256 for devices of compute
capability 1.0 and 1.1, and 512 for devices of compute capability 1.2 and 1.3,
and 64 for devices of compute capability 2.x.
The total amount of shared memory Sblock in bytes allocated for a block is as follows:
) , (
S k block
G S ceil S =
 Sk is the amount of shared memory used by the kernel in bytes,
 GS is the shared memory allocation granularity, which is equal to 512 for devices
of compute capability 1.x and 128 for devices of compute capability 2.x.
4.3 Multiple Devices
In a system with multiple GPUs, all CUDA-enabled GPUs are accessible via the
CUDA driver and runtime as separate devices. There are however special
considerations as described below when the system is in SLI mode.
First, an allocation in one CUDA device on one GPU will consume memory on
other GPUs that are part of the SLI configuration of the Direct3D device. Because
of this, allocations may fail earlier than otherwise expected.
Second, applications have to create multiple CUDA contexts, one for each GPU in
the SLI configuration and deal with the fact that a different GPU is used for
rendering by the Direct3D device at every frame. The application can use the
cuD3D[9|10|11]GetDevices() set of calls to identify the CUDA device
handle(s) for the GPU(s) that are performing the rendering in the current and next
frame. Given this information the application will typically map Direct3D resources
to the CUDA context corresponding to the CUDA device returned by
cuD3D[9|10|11]GetDevices() when the deviceList parameter is set to
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CU_D3D10_DEVICE_LIST_CURRENT_FRAME. See Sections 3.2.7.2 and 3.3.10.2
for details on how to use CUDA-Direct3D interoperability.







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Chapter 5.
Performance Guidelines
5.1 Overall Performance Optimization Strategies
Performance optimization revolves around three basic strategies:
 Maximize parallel execution to achieve maximum utilization;
 Optimize memory usage to achieve maximum memory throughput;
 Optimize instruction usage to achieve maximum instruction throughput.
Which strategies will yield the best performance gain for a particular portion of an
application depends on the performance limiters for that portion; optimizing
instruction usage of a kernel that is mostly limited by memory accesses will not yield
any significant performance gain, for example. Optimization efforts should
therefore be constantly directed by measuring and monitoring the performance
limiters, for example using the CUDA profiler. Also, comparing the floating-point
operation throughput or memory throughput – whichever makes more sense – of a
particular kernel to the corresponding peak theoretical throughput of the device
indicates how much room for improvement there is for the kernel.
5.2 Maximize Utilization
To maximize utilization the application should be structured in a way that it exposes
as much parallelism as possible and efficiently maps this parallelism to the various
components of the system to keep them busy most of the time.
5.2.1 Application Level
At a high level, the application should maximize parallel execution between the host,
the devices, and the bus connecting the host to the devices, by using asynchronous
functions calls and streams as described in Section 3.2.6. It should assign to each
processor the type of work it does best: serial workloads to the host; parallel
workloads to the devices.
For the parallel workloads, at points in the algorithm where parallelism is broken
because some threads need to synchronize in order to share data with each other,
there are two cases: Either these threads belong to the same block, in which case
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they should use __syncthreads() and share data through shared memory within
the same kernel invocation, or they belong to different blocks, in which case they
must share data through global memory using two separate kernel invocations, one
for writing to and one for reading from global memory. The second case is much
less optimal since it adds the overhead of extra kernel invocations and global
memory traffic. Its occurrence should therefore be minimized by mapping the
algorithm to the CUDA programming model in such a way that the computations
that require inter-thread communication are performed within a single thread block
as much as possible.
5.2.2 Device Level
At a lower level, the application should maximize parallel execution between the
multiprocessors of a device.
For devices of compute capability 1.x, only one kernel can execute on a device at
one time, so the kernel should be launched with at least as many thread blocks as
there are multiprocessors in the device.
For devices of compute capability 2.x, multiple kernels can execute concurrently on
a device, so maximum utilization can also be achieved by using streams to enable
enough kernels to execute concurrently as described in Section 3.2.6.
5.2.3 Multiprocessor Level
At an even lower level, the application should maximize parallel execution between
the various functional units within a multiprocessor.
As described in Section 4.2, a GPU multiprocessor relies on thread-level parallelism
to maximize utilization of its functional units. Utilization is therefore directly linked
to the number of resident warps. At every instruction issue time, a warp scheduler
selects a warp that is ready to execute its next instruction, if any, and issues the
instruction to the active threads of the warp. The number of clock cycles it takes for
a warp to be ready to execute its next instruction is called the latency, and full
utilization is achieved when all warp schedulers always have some instruction to
issue for some warp at every clock cycle during that latency period, or in other
words, when latency is completely “hidden”. The number of instructions required to
hide a latency of L clock cycles depends on the respective throughputs of these
instructions (see Section 5.4.1 for the throughputs of various arithmetic
instructions); assuming maximum throughput for all instructions, it is:
 L/4 (rounded up to nearest integer) for devices of compute capability 1.x since
a multiprocessor issues one instruction per warp over 4 clock cycles, as
mentioned in Section G.3.1,
 L (rounded up to nearest integer) for devices of compute capability 2.0 since a
multiprocessor issues one instruction per warp over 2 clock cycles for 2 warps
at a time, as mentioned in Section G.4.1,
 2L (rounded up to nearest integer) for devices of compute capability 2.1 since a
multiprocessor issues a pair of instructions per warp over 2 clock cycles for 2
warps at a time, as mentioned in Section G.4.1.
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For devices of compute capability 2.0, the two instructions issued every other cycle
are for two different warps. For devices of compute capability 2.1, the four
instructions issued every other cycle are two pairs for two different warps, each pair
being for the same warp.
The most common reason a warp is not ready to execute its next instruction is that
the instruction‟s input operands are not yet available.
If all input operands are registers, latency is caused by register dependencies, i.e.
some of the input operands are written by some previous instruction(s) whose
execution has not completed yet. In the case of a back-to-back register dependency
(i.e. some input operand is written by the previous instruction), the latency is equal
to the execution time of the previous instruction and the warp scheduler must
schedule instructions for different warps during that time. Execution time varies
depending on the instruction, but it is typically about 22 clock cycles, which
translates to 6 warps for devices of compute capability 1.x and 22 warps for devices
of compute capability 2.x.
If some input operand resides in off-chip memory, the latency is much higher: 400
to 800 clock cycles. The number of warps required to keep the warp schedulers busy
during such high latency periods depends on the kernel code; in general, more warps
are required if the ratio of the number of instructions with no off-chip memory
operands (i.e. arithmetic instructions most of the time) to the number of
instructions with off-chip memory operands is low (this ratio is commonly called
the arithmetic intensity of the program). If this ratio is 15, for example, then to hide
latencies of about 600 clock cycles, about 10 warps are required for devices of
compute capability 1.x and about 40 for devices of compute capability 2.x.
Another reason a warp is not ready to execute its next instruction is that it is waiting
at some memory fence (Section B.5) or synchronization point (Section B.6). A
synchronization point can force the multiprocessor to idle as more and more warps
wait for other warps in the same block to complete execution of instructions prior
to the synchronization point. Having multiple resident blocks per multiprocessor
can help reduce idling in this case, as warps from different blocks do not need to
wait for each other at synchronization points.
The number of blocks and warps residing on each multiprocessor for a given kernel
call depends on the execution configuration of the call (Section B.16), the memory
resources of the multiprocessor, and the resource requirements of the kernel as
described in Section 4.2. To assist programmers in choosing thread block size based
on register and shared memory requirements, the CUDA Software Development
Kit provides a spreadsheet, called the CUDA Occupancy Calculator, where
occupancy is defined as the ratio of the number of resident warps to the maximum
number of resident warps (given in Appendix G for various compute capabilities).
Register, local, shared, and constant memory usages are reported by the compiler
when compiling with the --ptxas-options=-v option.
The total amount of shared memory required for a block is equal to the sum of the
amount of statically allocated shared memory, the amount of dynamically allocated
shared memory, and for devices of compute capability 1.x, the amount of shared
memory used to pass the kernel‟s arguments (see Section B.1.4).
The number of registers used by a kernel can have a significant impact on the
number of resident warps. For example, for devices of compute capability 1.2, if a
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kernel uses 16 registers and each block has 512 threads and requires very little
shared memory, then two blocks (i.e. 32 warps) can reside on the multiprocessor
since they require 2x512x16 registers, which exactly matches the number of registers
available on the multiprocessor. But as soon as the kernel uses one more register,
only one block (i.e. 16 warps) can be resident since two blocks would require
2x512x17 registers, which are more registers than are available on the
multiprocessor. Therefore, the compiler attempts to minimize register usage while
keeping register spilling (see Section 5.3.2.2) and the number of instructions to a
minimum. Register usage can be controlled using the -maxrregcount compiler
option or launch bounds as described in Section B.17.
Each double variable (on devices that supports native double precision, i.e. devices
of compute capability 1.2 and higher) and each long long variable uses two
registers. However, devices of compute capability 1.2 and higher have at least twice
as many registers per multiprocessor as devices with lower compute capability.
The effect of execution configuration on performance for a given kernel call
generally depends on the kernel code. Experimentation is therefore recommended.
Applications can also parameterize execution configurations based on register file
size and shared memory size, which depends on the compute capability of the
device, as well as on the number of multiprocessors and memory bandwidth of the
device, all of which can be queried using the runtime or driver API (see reference
manual).
The number of threads per block should be chosen as a multiple of the warp size to
avoid wasting computing resources with under-populated warps as much as
possible.
5.3 Maximize Memory Throughput
The first step in maximizing overall memory throughput for the application is to
minimize data transfers with low bandwidth.
That means minimizing data transfers between the host and the device, as detailed
in Section 5.3.1, since these have much lower bandwidth than data transfers
between global memory and the device.
That also means minimizing data transfers between global memory and the device
by maximizing use of on-chip memory: shared memory and caches (i.e. L1/L2
caches available on devices of compute capability 2.x, texture cache and constant
cache available on all devices).
Shared memory is equivalent to a user-managed cache: The application explicitly
allocates and accesses it. As illustrated in Section 3.2.2, a typical programming
pattern is to stage data coming from device memory into shared memory; in other
words, to have each thread of a block:
 Load data from device memory to shared memory,
 Synchronize with all the other threads of the block so that each thread can
safely read shared memory locations that were populated by different threads,
 Process the data in shared memory,
 Synchronize again if necessary to make sure that shared memory has been
updated with the results,
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 Write the results back to device memory.
For some applications (e.g. for which global memory accesses are data-dependent), a
traditional hardware-managed cache is more appropriate to exploit data locality. As
mentioned in Section G.4.1, for devices of compute capability 2.x, the same on-chip
memory is used for both L1 and shared memory, and how much of it is dedicated to
L1 versus shared memory is configurable for each kernel call.
The throughput of memory accesses by a kernel can vary by an order of magnitude
depending on access pattern for each type of memory. The next step in maximizing
memory throughput is therefore to organize memory accesses as optimally as
possible based on the optimal memory access patterns described in Sections 5.3.2.1,
5.3.2.3, 5.3.2.4, and 5.3.2.5. This optimization is especially important for global
memory accesses as global memory bandwidth is low, so non-optimal global
memory accesses have a higher impact on performance.
5.3.1 Data Transfer between Host and Device
Applications should strive to minimize data transfer between the host and the
device. One way to accomplish this is to move more code from the host to the
device, even if that means running kernels with low parallelism computations.
Intermediate data structures may be created in device memory, operated on by the
device, and destroyed without ever being mapped by the host or copied to host
memory.
Also, because of the overhead associated with each transfer, batching many small
transfers into a single large transfer always performs better than making each
transfer separately.
On systems with a front-side bus, higher performance for data transfers between
host and device is achieved by using page-locked host memory as described in
Section 3.2.4.1.4.
In addition, when using mapped page-locked memory (Section 3.2.5.3), there is no
need to allocate any device memory and explicitly copy data between device and
host memory. Data transfers are implicitly performed each time the kernel accesses
the mapped memory. For maximum performance, these memory accesses must be
coalesced as with accesses to global memory (see Section 5.3.2.1). Assuming that
they are and that the mapped memory is read or written only once, using mapped
page-locked memory instead of explicit copies between device and host memory can
be a win for performance.
On integrated systems where device memory and host memory are physically the
same, any copy between host and device memory is superfluous and mapped page-
locked memory should be used instead. Applications may query whether a device is
integrated or not by calling cudaGetDeviceProperties() and checking the
integrated property or checking the CU_DEVICE_ATTRIBUTE_INTEGRATED
attribute using cuDeviceGetAttribute().
5.3.2 Device Memory Accesses
An instruction that accesses addressable memory (i.e. global, local, shared, constant,
or texture memory) might need to be re-issued multiple times depending on the
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distribution of the memory addresses across the threads within the warp. How the
distribution affects the instruction throughput this way is specific to each type of
memory and described in the following sections. For example, for global memory,
as a general rule, the more scattered the addresses are, the more reduced the
throughput is.
5.3.2.1 Global Memory
Global memory resides in device memory and device memory is accessed via 32-,
64-, or 128-byte memory transactions. These memory transactions must be naturally
aligned: Only the 32-, 64-, or 128-byte segments of device memory that are aligned
to their size (i.e. whose first address is a multiple of their size) can be read or written
by memory transactions.
When a warp executes an instruction that accesses global memory, it coalesces the
memory accesses of the threads within the warp into one or more of these memory
transactions depending on the size of the word accessed by each thread and the
distribution of the memory addresses across the threads. In general, the more
transactions are necessary, the more unused words are transferred in addition to the
words accessed by the threads, reducing the instruction throughput accordingly. For
example, if a 32-byte memory transaction is generated for each thread‟s 4-byte
access, throughput is divided by 8.
How many transactions are necessary and how throughput is ultimately affected
varies with the compute capability of the device. For devices of compute capability
1.0 and 1.1, the requirements on the distribution of the addresses across the threads
to get any coalescing at all are very strict. They are much more relaxed for devices of
higher compute capabilities. For devices of compute capability 2.x, the memory
transactions are cached, so data locality is exploited to reduce impact on throughput.
Sections G.3.2 and G.4.2 give more details on how global memory accesses are
handled for various compute capabilities.
To maximize global memory throughput, it is therefore important to maximize
coalescing by:
 Following the most optimal access patterns based on Sections G.3.2 and G.4.2,
 Using data types that meet the size and alignment requirement detailed in
Section 5.3.2.1.1,
 Padding data in some cases, for example, when accessing a two-dimensional
array as described in Section 5.3.2.1.2.
5.3.2.1.1 Size and Alignment Requirement
Global memory instructions support reading or writing words of size equal to 1, 2,
4, 8, or 16 bytes. Any access (via a variable or a pointer) to data residing in global
memory compiles to a single global memory instruction if and only if the size of the
data type is 1, 2, 4, 8, or 16 bytes and the data is naturally aligned (i.e. its address is a
multiple of that size).
If this size and alignment requirement is not fulfilled, the access compiles to
multiple instructions with interleaved access patterns that prevent these instructions
from fully coalescing. It is therefore recommended to use types that meet this
requirement for data that resides in global memory.
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The alignment requirement is automatically fulfilled for the built-in types of
Section B.3.1 like float2 or float4.
For structures, the size and alignment requirements can be enforced by the compiler
using the alignment specifiers __align__(8) or __align__(16), such as
struct __align__(8) {
float x;
float y;
};
or
struct __align__(16) {
float x;
float y;
float z;
};
Any address of a variable residing in global memory or returned by one of the
memory allocation routines from the driver or runtime API is always aligned to at
least 256 bytes.
Reading non-naturally aligned 8-byte or 16-byte words produces incorrect results
(off by a few words), so special care must be taken to maintain alignment of the
starting address of any value or array of values of these types. A typical case where
this might be easily overlooked is when using some custom global memory
allocation scheme, whereby the allocations of multiple arrays (with multiple calls to
cudaMalloc() or cuMemAlloc()) is replaced by the allocation of a single large
block of memory partitioned into multiple arrays, in which case the starting address
of each array is offset from the block‟s starting address.
5.3.2.1.2 Two-Dimensional Arrays
A common global memory access pattern is when each thread of index (tx,ty)
uses the following address to access one element of a 2D array of width width,
located at address BaseAddress of type type* (where type meets the
requirement described in Section 5.3.2.1.1):
BaseAddress + width * ty + tx
For these accesses to be fully coalesced, both the width of the thread block and the
width of the array must be a multiple of the warp size (or only half the warp size for
devices of compute capability 1.x).
In particular, this means that an array whose width is not a multiple of this size will
be accessed much more efficiently if it is actually allocated with a width rounded up
to the closest multiple of this size and its rows padded accordingly. The
cudaMallocPitch() and cuMemAllocPitch() functions and associated
memory copy functions described in the reference manual enable programmers to
write non-hardware-dependent code to allocate arrays that conform to these
constraints.
5.3.2.2 Local Memory
Local memory accesses only occur for some automatic variables as mentioned in
Section B.2.4. Automatic variables that the compiler is likely to place in local
memory are:
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 Arrays for which it cannot determine that they are indexed with constant
quantities,
 Large structures or arrays that would consume too much register space,
 Any variable if the kernel uses more registers than available (this is also known
as register spilling).
Inspection of the PTX assembly code (obtained by compiling with the –ptx or
-keep option) will tell if a variable has been placed in local memory during the first
compilation phases as it will be declared using the .local mnemonic and accessed
using the ld.local and st.local mnemonics. Even if it has not, subsequent
compilation phases might still decide otherwise though if they find it consumes too
much register space for the targeted architecture: Inspection of the cubin object
using cuobjdump will tell if this is the case. Also, the compiler reports total local
memory usage per kernel (lmem) when compiling with the --ptxas-options=-v
option. Note that some mathematical functions have implementation paths that
might access local memory.
The local memory space resides in device memory, so local memory accesses have
same high latency and low bandwidth as global memory accesses and are subject to
the same requirements for memory coalescing as described in Section 5.3.2.1. Local
memory is however organized such that consecutive 32-bit words are accessed by
consecutive thread IDs. Accesses are therefore fully coalesced as long as all threads
in a warp access the same relative address (e.g. same index in an array variable, same
member in a structure variable).
On devices of compute capability 2.x, local memory accesses are always cached in
L1 and L2 in the same way as global memory accesses (see Section G.4.2).
5.3.2.3 Shared Memory
Because it is on-chip, the shared memory space is much faster than the local and
global memory spaces. In fact, for all threads of a warp, accessing shared memory is
fast as long as there are no bank conflicts between the threads, as detailed below.
To achieve high bandwidth, shared memory is divided into equally-sized memory
modules, called banks, which can be accessed simultaneously. Any memory read or
write request made of n addresses that fall in n distinct memory banks can therefore
be serviced simultaneously, yielding an overall bandwidth that is n times as high as
the bandwidth of a single module.
However, if two addresses of a memory request fall in the same memory bank, there
is a bank conflict and the access has to be serialized. The hardware splits a memory
request with bank conflicts into as many separate conflict-free requests as necessary,
decreasing throughput by a factor equal to the number of separate memory requests.
If the number of separate memory requests is n, the initial memory request is said to
cause n-way bank conflicts.
To get maximum performance, it is therefore important to understand how memory
addresses map to memory banks in order to schedule the memory requests so as to
minimize bank conflicts. This is described in Sections G.3.3 and G.4.3 for devices of
compute capability 1.x and 2.x, respectively.
5.3.2.4 Constant Memory
The constant memory space resides in device memory and is cached in the constant
cache mentioned in Sections G.3.1 and G.4.1.
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For devices of compute capability 1.x, a constant memory request for a warp is first
split into two requests, one for each half-warp, that are issued independently.
A request is then split into as many separate requests as there are different memory
addresses in the initial request, decreasing throughput by a factor equal to the
number of separate requests.
The resulting requests are then serviced at the throughput of the constant cache in
case of a cache hit, or at the throughput of device memory otherwise.
5.3.2.5 Texture and Surface Memory
The texture and surface memory spaces reside in device memory and are cached in
texture cache, so a texture fetch or surface read costs one memory read from device
memory only on a cache miss, otherwise it just costs one read from texture cache.
The texture cache is optimized for 2D spatial locality, so threads of the same warp
that read texture or surface addresses that are close together in 2D will achieve best
performance. Also, it is designed for streaming fetches with a constant latency; a
cache hit reduces DRAM bandwidth demand but not fetch latency.
Reading device memory through texture or surface fetching present some benefits
that can make it an advantageous alternative to reading device memory from global
or constant memory:
 If the memory reads do not follow the access patterns that global or constant
memory reads must respect to get good performance (see Sections 5.3.2.1 and
5.3.2.4), higher bandwidth can be achieved providing that there is locality in the
texture fetches or surface reads (this is less likely for devices of compute
capability 2.x given that global memory reads are cached on these devices);
 Addressing calculations are performed outside the kernel by dedicated units;
 Packed data may be broadcast to separate variables in a single operation;
 8-bit and 16-bit integer input data may be optionally converted to 32-bit
floating-point values in the range [0.0, 1.0] or [-1.0, 1.0] (see Section 3.2.4.1.1).
5.4 Maximize Instruction Throughput
To maximize instruction throughput the application should:
 Minimize the use of arithmetic instructions with low throughput; this includes
trading precision for speed when it does not affect the end result, such as using
intrinsic instead of regular functions (intrinsic functions are listed in
Section C.2), single-precision instead of double-precision, or flushing
denormalized numbers to zero;
 Minimize divergent warps caused by control flow instructions as detailed in
Section 5.4.2;
 Reduce the number of instructions, for example, by optimizing out
synchronization points whenever possible as described in Section 5.4.3 or by
using restricted pointers as described in Section E.3.
In this section, throughputs are given in number of operations per clock cycle per
multiprocessor. For a warp size of 32, one instruction results in 32 operations.
Therefore, if T is the number of operations per clock cycle, the instruction
throughput is one instruction every 32/T clock cycles.
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All throughputs are for one multiprocessor. They must be multiplied by the number
of multiprocessors in the device to get throughput for the whole device.
5.4.1 Arithmetic Instructions
Table 5-1 gives the throughputs of the arithmetic instructions that are natively
supported in hardware for devices of various compute capabilities.
Table 5-1. Throughput of Native Arithmetic Instructions
(Operations per Clock Cycle per Multiprocessor)
Compute
Capability 1.x
Compute
Capability 2.0
Compute
Capability 2.1
32-bit floating-point
add, multiply, multiply-add
8 32 48
64-bit floating-point
add, multiply, multiply-add
1 16 4
32-bit integer
add, logical operation
8 32 48
32-bit integer
shift, compare
8 16 16
32-bit integer
multiply, multiply-add, sum of
absolute difference
Multiple
instructions
16 16
24-bit integer multiply
(__[u]mul24)
8
Multiple
instructions
Multiple
instructions
32-bit floating-point
reciprocal, reciprocal square
root,
base-2 logarithm (__log2f),
base-2 exponential (exp2f),
sine (__sinf), cosine
(__cosf)
2 4 8
Type conversions 8 16 16

Other instructions and functions are implemented on top of the native instructions.
The implementation may be different for devices of compute capability 1.x and
devices of compute capability 2.x, and the number of native instructions after
compilation may fluctuate with every compiler version. For complicated functions,
there can be multiple code paths depending on input. cuobjdump can be used to
inspect a particular implementation in a cubin object.
The implementation of some functions are readily available on the CUDA header
files (math_functions.h, device_functions.h, …).
In general, code compiled with -ftz=true (denormalized numbers are flushed to
zero) tends to have higher performance than code compiled with -ftz=false.
Similarly, code compiled with -prec-div=false (less precise division) tends to
have higher performance code than code compiled with -prec-div=true, and
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code compiled with -prec-sqrt=false (less precise square root) tends to have
higher performance than code compiled with -prec-sqrt=true. The nvcc user
manual describes these compilation flags in more details.
Single-Precision Floating-Point Addition and Multiplication Intrinsics
__fadd_r[d,u], __fmul_r[d,u], and __fmaf_r[n,z,d,u] (see
Section C.2.1) compile to tens of instructions for devices of compute capability 1.x,
but map to a single native instruction for devices of compute capability 2.x.
Single-Precision Floating-Point Division
__fdividef(x, y) (see Section C.2.1) provides faster single-precision floating-
point division than the division operator.
Single-Precision Floating-Point Reciprocal Square Root
To preserve IEEE-754 semantics the compiler can optimize 1.0/sqrtf() into
rsqrtf() only when both reciprocal and square root are approximate, (i.e. with
-prec-div=false and -prec-sqrt=false). It is therefore recommended to
invoke rsqrtf() directly where desired.
Single-Precision Floating-Point Square Root
Single-precision floating-point square root is implemented as a reciprocal square
root followed by a reciprocal instead of a reciprocal square root followed by a
multiplication so that it gives correct results for 0 and infinity. Therefore, its
throughput is 1 operation per clock cycle for devices of compute capability 1.x and
2 operations per clock cycle for devices of compute capability 2.x.
Sine and Cosine
sinf(x), cosf(x), tanf(x), sincosf(x), and corresponding double-
precision instructions are much more expensive and even more so if the argument x
is large in magnitude.
More precisely, the argument reduction code (see math_functions.h for
implementation) comprises two code paths referred to as the fast path and the slow
path, respectively.
The fast path is used for arguments sufficiently small in magnitude and essentially
consists of a few multiply-add operations. The slow path is used for arguments large
in magnitude and consists of lengthy computations required to achieve correct
results over the entire argument range.
At present, the argument reduction code for the trigonometric functions selects the
fast path for arguments whose magnitude is less than 48039.0f for the single-
precision functions, and less than 2147483648.0 for the double-precision functions.
As the slow path requires more registers than the fast path, an attempt has been
made to reduce register pressure in the slow path by storing some intermediate
variables in local memory, which may affect performance because of local memory
high latency and bandwidth (see Section 5.3.2.2). At present, 28 bytes of local
memory are used by single-precision functions, and 44 bytes are used by double-
precision functions. However, the exact amount is subject to change.
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Due to the lengthy computations and use of local memory in the slow path, the
throughput of these trigonometric functions is lower by one order of magnitude
when the slow path reduction is required as opposed to the fast path reduction.
Integer Arithmetic
On devices of compute capability 1.x, 32-bit integer multiplication is implemented
using multiple instructions as it is not natively supported. 24-bit integer
multiplication is natively supported however via the __[u]mul24 intrinsic (see
Section C.2.3). Using __[u]mul24 instead of the 32-bit multiplication operator
whenever possible usually improves performance for instruction bound kernels. It
can have the opposite effect however in cases where the use of __[u]mul24
inhibits compiler optimizations.
On devices of compute capability 2.x, 32-bit integer multiplication is natively
supported, but 24-bit integer multiplication is not. __[u]mul24 is therefore
implemented using multiple instructions and should not be used.
Integer division and modulo operation are costly: tens of instructions on devices of
compute capability 1.x, below 20 instructions on devices of compute capability 2.x.
They can be replaced with bitwise operations in some cases: If n is a power of 2,
(i/n) is equivalent to (i>>log2(n)) and (i%n) is equivalent to (i&(n-1));
the compiler will perform these conversions if n is literal.
__brev, __brevll, __popc, and __popcll (see Section C.2.3) compile to tens
of instructions for devices of compute capability 1.x, but __brev and __popc map
to a single instruction for devices of compute capability 2.x and __brevll and
__popcll to just a few.
__clz, __clzll, __ffs, and __ffsll (see Section C.2.3) compile to fewer
instructions for devices of compute capability 2.x than for devices of compute
capability 1.x.
Type Conversion
Sometimes, the compiler must insert conversion instructions, introducing additional
execution cycles. This is the case for:
 Functions operating on variables of type char or short whose operands
generally need to be converted to int,
 Double-precision floating-point constants (i.e. those constants defined without
any type suffix) used as input to single-precision floating-point computations (as
mandated by C/C++ standards).
This last case can be avoided by using single-precision floating-point constants,
defined with an f suffix such as 3.141592653589793f, 1.0f, 0.5f.
5.4.2 Control Flow Instructions
Any flow control instruction (if, switch, do, for, while) can significantly
impact the effective instruction throughput by causing threads of the same warp to
diverge (i.e. to follow different execution paths). If this happens, the different
executions paths have to be serialized, increasing the total number of instructions
executed for this warp. When all the different execution paths have completed, the
threads converge back to the same execution path.
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To obtain best performance in cases where the control flow depends on the thread
ID, the controlling condition should be written so as to minimize the number of
divergent warps. This is possible because the distribution of the warps across the
block is deterministic as mentioned in Section 4.1. A trivial example is when the
controlling condition only depends on (threadIdx / warpSize) where
warpSize is the warp size. In this case, no warp diverges since the controlling
condition is perfectly aligned with the warps.
Sometimes, the compiler may unroll loops or it may optimize out if or switch
statements by using branch predication instead, as detailed below. In these cases, no
warp can ever diverge. The programmer can also control loop unrolling using the
#pragma unroll directive (see Section E.2).
When using branch predication none of the instructions whose execution depends
on the controlling condition gets skipped. Instead, each of them is associated with a
per-thread condition code or predicate that is set to true or false based on the
controlling condition and although each of these instructions gets scheduled for
execution, only the instructions with a true predicate are actually executed.
Instructions with a false predicate do not write results, and also do not evaluate
addresses or read operands.
The compiler replaces a branch instruction with predicated instructions only if the
number of instructions controlled by the branch condition is less or equal to a
certain threshold: If the compiler determines that the condition is likely to produce
many divergent warps, this threshold is 7, otherwise it is 4.
5.4.3 Synchronization Instruction
Throughput for __syncthreads() is 8 operations per clock cycle for devices of
compute capability 1.x and 16 operations per clock cycle for devices of compute
capability 2.x.
Note that __syncthreads() can impact performance by forcing the
multiprocessor to idle as detailed in Section 5.2.3.
Because a warp executes one common instruction at a time, threads within a warp
are implicitly synchronized and this can sometimes be used to omit
__syncthreads() for better performance.
In the following code sample, for example, both calls to __syncthreads() are
required to get the expected result (i.e. result[i] = 2 * myArray[i] for
i > 0). Without synchronization, any of the two references to myArray[tid]
could return either 2 or the value initially stored in myArray, depending on whether
the memory read occurs before or after the memory write from
myArray[tid + 1] = 2.
// myArray is an array of integers located in global or shared
// memory
__global__ void MyKernel(int* result) {
int tid = threadIdx.x;
...
int ref1 = myArray[tid];
__syncthreads();
myArray[tid + 1] = 2;
__syncthreads();
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int ref2 = myArray[tid];
result[tid] = ref1 * ref2;
...
}
However, in the following slightly modified code sample, threads are guaranteed to
belong to the same warp, so that there is no need for any __syncthreads().
// myArray is an array of integers located in global or shared
// memory
__global__ void MyKernel(int* result) {
int tid = threadIdx.x;
...
if (tid < warpSize) {
int ref1 = myArray[tid];
myArray[tid + 1] = 2;
int ref2 = myArray[tid];
result[tid] = ref1 * ref2;
}
...
}
Simply removing the __syncthreads() is not enough however; myArray must
also be declared as volatile as described in Section B.2.5.







CUDA C Programming Guide Version 3.1 99

Appendix A.
CUDA-Enabled GPUs
Table A-1 lists all CUDA-enabled devices with their compute capability, number of
multiprocessors, and number of CUDA cores.
These, as well as the clock frequency and the total amount of device memory, can
be queried using the runtime or driver API (see reference manual).
Table A-1. CUDA-Enabled Devices with Compute Capability,
Number of Multiprocessors, and Number of CUDA
Cores
Compute
Capability
Number of
Multiprocessors
Number of
CUDA Cores
GeForce GTX 460 2.1 7 336
GeForce GTX 470M 2.1 6 288
GeForce GTS 450, GTX 460M 2.1 4 192
GeForce GT 445M 2.1 3 144
GeForce GT 435M, GT 425M,
GT 420M
2.1 2 96
GeForce GT 415M 2.1 1 48
GeForce GTX 580 2.0 16 512
GeForce GTX 480 2.0 15 480
GeForce GTX 470 2.0 14 448
GeForce GTX 465, GTX 480M 2.0 11 352
GeForce GTX 295 1.3 2x30 2x240
GeForce GTX 285, GTX 280,
GTX 275
1.3 30 240
GeForce GTX 260 1.3 24 192
GeForce 9800 GX2 1.1 2x16 2x128
GeForce GTS 250, GTS 150,
9800 GTX, 9800 GTX+,
8800 GTS 512, GTX 285M,
GTX 280M
1.1 16 128
GeForce 8800 Ultra, 8800 GTX 1.0 16 128
GeForce 9800 GT, 8800 GT,
GTX 260M, 9800M GTX
1.1 14 112
Appendix A. CUDA-Enabled GPUs


100 CUDA C Programming Guide Version 3.2

Compute
Capability
Number of
Multiprocessors
Number of
CUDA Cores
GeForce GT 240, GTS 360M,
GTS 350M
1.2 12 96
GeForce GT 130, 9600 GSO,
8800 GS, 8800M GTX, GTS 260M,
GTS 250M, 9800M GT
1.1 12 96
GeForce 8800 GTS 1.0 12 96
GeForce GT 335M 1.2 9 72
GeForce 9600 GT, 8800M GTS,
9800M GTS
1.1 8 64
GeForce GT 220, GT 330M,
GT 325M, GT 240M
1.2 6 48
GeForce 9700M GT, GT 230M 1.1 6 48
GeForce GT 120, 9500 GT,
8600 GTS, 8600 GT, 9700M GT,
9650M GS, 9600M GT, 9600M GS,
9500M GS, 8700M GT, 8600M GT,
8600M GS
1.1 4 32
GeForce 210, 310M, 305M 1.2 2 16
GeForce G100, 8500 GT, 8400 GS,
8400M GT, 9500M G, 9300M G,
8400M GS, 9400 mGPU,
9300 mGPU, 8300 mGPU,
8200 mGPU, 8100 mGPU, G210M,
G110M
1.1 2 16
GeForce 9300M GS, 9200M GS,
9100M G, 8400M G, G105M
1.1 1 8
Tesla C2050 2.0 14 448
Tesla S1070 1.3 4x30 4x240
Tesla C1060 1.3 30 240
Tesla S870 1.0 4x16 4x128
Tesla D870 1.0 2x16 2x128
Tesla C870 1.0 16 128
Quadro 2000 2.1 4 192
Quadro 600 2.1 2 96
Quadro 6000 2.0 14 448
Quadro 5000 2.0 11 352
Quadro 5000M 2.0 10 320
Quadro 4000 2.0 8 256
Quadro Plex 2200 D2 1.3 2x30 2x240
Quadro Plex 2100 D4 1.1 4x14 4x112
Quadro Plex 2100 Model S4 1.0 4x16 4x128
Quadro Plex 1000 Model IV 1.0 2x16 2x128
Quadro FX 5800 1.3 30 240
Quadro FX 4800 1.3 24 192
Quadro FX 4700 X2 1.1 2x14 2x112
Quadro FX 3700M, FX 3800M 1.1 16 128
Quadro FX 5600 1.0 16 128
Appendix A. CUDA-Enabled GPUs


CUDA C Programming Guide Version 3.2 101

Compute
Capability
Number of
Multiprocessors
Number of
CUDA Cores
Quadro FX 3700 1.1 14 112
Quadro FX 2800M 1.1 12 96
Quadro FX 4600 1.0 12 96
Quadro FX 1800M 1.2 9 72
Quadro FX 3600M 1.1 8 64
Quadro FX 880M, NVS 5100M 1.2 6 48
Quadro FX 2700M 1.1 6 48
Quadro FX 1700, FX 570,
NVS 320M, FX 1700M, FX 1600M,
FX 770M, FX 570M
1.1 4 32
Quadro FX 380 LP, FX 380M,
NVS 3100M, NVS 2100M
1.2 2 16
Quadro FX 370, NVS 290,
NVS 160M, NVS 150M, NVS 140M,
NVS 135M, FX 360M
1.1 2 16
Quadro FX 370M, NVS 130M 1.1 1 8







CUDA C Programming Guide Version 3.1 103

Appendix B.
C Language Extensions
B.1 Function Type Qualifiers
Function type qualifiers specify whether a function executes on the host or on the
device and whether it is callable from the host or from the device.
B.1.1 __device__
The __device__ qualifier declares a function that is:
 Executed on the device
 Callable from the device only.
In device code compiled for devices of compute capability 1.x, a __device__
function is always inlined by default. The __noinline__ function qualifier
however can be used as a hint for the compiler not to inline the function if possible
(see Section E.1).
B.1.2 __global__
The __global__ qualifier declares a function as being a kernel. Such a function is:
 Executed on the device,
 Callable from the host only.
__global__ functions must have void return type.
Any call to a __global__ function must specify its execution configuration as
described in Section B.16.
A call to a __global__ function is asynchronous, meaning it returns before the
device has completed its execution.
B.1.3 __host__
The __host__ qualifier declares a function that is:
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104 CUDA C Programming Guide Version 3.2

 Executed on the host,
 Callable from the host only.
It is equivalent to declare a function with only the __host__ qualifier or to declare
it without any of the __host__, __device__, or __global__ qualifier; in either
case the function is compiled for the host only.
The __global__ and __host__ qualifiers cannot be used together.
The __device__ and __host__ qualifiers can be used together however, in
which case the function is compiled for both the host and the device. The
__CUDA_ARCH__ macro introduced in Section 3.1.4 can be used to differentiate
code paths between host and device:
__host__ __device__ func()
{
#if __CUDA_ARCH__ == 100
// Device code path for compute capability 1.0
#elif __CUDA_ARCH__ == 200
// Device code path for compute capability 2.0
#elif !defined(__CUDA_ARCH__)
// Host code path
#endif
}
B.1.4 Restrictions
B.1.4.1 Functions Parameters
__global__ function parameters are passed to the device:
 via shared memory and are limited to 256 bytes on devices of compute
capability 1.x,
 via constant memory and are limited to 4 KB on devices of compute
capability 2.x.
B.1.4.2 Variadic Functions
__device__ and __global__ functions cannot have a variable number of
arguments.
B.1.4.3 Static Variables
__device__ and __global__ functions cannot declare static variables inside
their body.
B.1.4.4 Function Pointers
Function pointers to __global__ functions are supported, but function pointers
to __device__ functions are only supported in device code compiled for devices
of compute capability 2.x.
It is not allowed to take the address of a __device__ function in host code.
B.1.4.5 Recursion
__global__ functions do not support recursion.
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CUDA C Programming Guide Version 3.2 105

__device__ functions only support recursion in device code compiled for devices
of compute capability 2.x.
B.2 Variable Type Qualifiers
Variable type qualifiers specify the memory location on the device of a variable.
B.2.1 __device__
The __device__ qualifier declares a variable that resides on the device.
At most one of the other type qualifiers defined in the next three sections may be
used together with __device__ to further specify which memory space the
variable belongs to. If none of them is present, the variable:
 Resides in global memory space,
 Has the lifetime of an application,
 Is accessible from all the threads within the grid and from the host through the
runtime library (cudaGetSymbolAddress() / cudaGetSymbolSize() /
cudaMemcpyToSymbol() / cudaMemcpyFromSymbol() for the runtime
API and cuModuleGetGlobal() for the driver API).
B.2.2 __constant__
The __constant__ qualifier, optionally used together with __device__,
declares a variable that:
 Resides in constant memory space,
 Has the lifetime of an application,
 Is accessible from all the threads within the grid and from the host through the
runtime library (cudaGetSymbolAddress() / cudaGetSymbolSize() /
cudaMemcpyToSymbol() / cudaMemcpyFromSymbol() for the runtime
API and cuModuleGetGlobal() for the driver API).
B.2.3 __shared__
The __shared__ qualifier, optionally used together with __device__, declares a
variable that:
 Resides in the shared memory space of a thread block,
 Has the lifetime of the block,
 Is only accessible from all the threads within the block.
When declaring a variable in shared memory as an external array such as
extern __shared__ float shared[];
the size of the array is determined at launch time (see Section B.16). All variables
declared in this fashion, start at the same address in memory, so that the layout of
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106 CUDA C Programming Guide Version 3.2

the variables in the array must be explicitly managed through offsets. For example, if
one wants the equivalent of
short array0[128];
float array1[64];
int array2[256];
in dynamically allocated shared memory, one could declare and initialize the arrays
the following way:
extern __shared__ float array[];
__device__ void func() // __device__ or __global__ function
{
short* array0 = (short*)array;
float* array1 = (float*)&array0[128];
int* array2 = (int*)&array1[64];
}
Note that pointers need to be aligned to the type they point to, so the following
code, for example, does not work since array1 is not aligned to 4 bytes.
extern __shared__ float array[];
__device__ void func() // __device__ or __global__ function
{
short* array0 = (short*)array;
float* array1 = (float*)&array0[127];
}
Alignment requirements for the built-in vector types are listed in Table B-1.
B.2.4 Restrictions
The __device__, __shared__ and __constant__ qualifiers are not allowed
on struct and union members, on formal parameters and on local variables
within a function that executes on the host.
B.2.4.1 Storage and Scope
__shared__ and __constant__ variables have implied static storage.
__device__, __shared__ and __constant__ variables cannot be defined as
external using the extern keyword. The only exception is for dynamically allocated
__shared__ variables as described in Section B.2.3.
__device__ and __constant__ variables are only allowed at file scope.
B.2.4.2 Assignment
__constant__ variables cannot be assigned to from the device, only from the
host through host runtime functions (Sections 3.2.1 and 3.3.4).
__shared__ variables cannot have an initialization as part of their declaration.
B.2.4.3 Automatic Variable
An automatic variable declared in device code without any of the __device__,
__shared__ and __constant__ qualifiers generally resides in a register.
However in some cases the compiler might choose to place it in local memory,
which can have adverse performance consequences as detailed in Section 5.3.2.2.
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CUDA C Programming Guide Version 3.2 107

B.2.4.4 Pointers
For devices of compute capability 1.x, pointers in code that is executed on the
device are supported as long as the compiler is able to resolve whether they point to
either the shared memory space or the global memory space, otherwise they are
restricted to only point to memory allocated or declared in the global memory space.
For devices of compute capability 2.x, pointers are supported without any
restriction.
Dereferencing a pointer either to global or shared memory in code that is executed
on the host or to host memory in code that is executed on the device results in an
undefined behavior, most often in a segmentation fault and application termination.
The address obtained by taking the address of a __device__, __shared__ or
__constant__ variable can only be used in device code. The address of a
__device__ or __constant__ variable obtained through
cudaGetSymbolAddress() as described in Section 3.3.4 can only be used in
host code.
B.2.5 volatile
Only after the execution of a __threadfence_block(), __threadfence(),
or __syncthreads() (Sections B.5 and B.6) are prior writes to global or shared
memory guaranteed to be visible by other threads. As long as this requirement is
met, the compiler is free to optimize reads and writes to global or shared memory.
For example, in the code sample below, the first reference to myArray[tid]
compiles into a global or shared memory read instruction, but the second reference
does not as the compiler simply reuses the result of the first read.
// myArray is an array of non-zero integers
// located in global or shared memory
__global__ void MyKernel(int* result) {
int tid = threadIdx.x;
int ref1 = myArray[tid] * 1;
myArray[tid + 1] = 2;
int ref2 = myArray[tid] * 1;
result[tid] = ref1 * ref2;
}
Therefore, ref2 cannot possibly be equal to 2 in thread tid as a result of thread
tid-1 overwriting myArray[tid] by 2.
This behavior can be changed using the volatile keyword: If a variable located in
global or shared memory is declared as volatile, the compiler assumes that its value
can be changed at any time by another thread and therefore any reference to this
variable compiles to an actual memory read instruction.
Note that even if myArray is declared as volatile in the code sample above, there is
no guarantee, in general, that ref2 will be equal to 2 in thread tid since thread
tid might read myArray[tid] into ref2 before thread tid-1 overwrites its
value by 2. Synchronization is required as mentioned in Section 5.4.3.
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108 CUDA C Programming Guide Version 3.2

B.3 Built-in Vector Types
B.3.1 char1, uchar1, char2, uchar2, char3, uchar3,
char4, uchar4, short1, ushort1, short2, ushort2,
short3, ushort3, short4, ushort4, int1, uint1, int2,
uint2, int3, uint3, int4, uint4, long1, ulong1,
long2, ulong2, long3, ulong3, long4, ulong4,
longlong1, ulonglong1, longlong2, ulonglong2,
float1, float2, float3, float4, double1, double2
These are vector types derived from the basic integer and floating-point types. They
are structures and the 1
st
, 2
nd
, 3
rd
, and 4
th
components are accessible through the
fields x, y, z, and w, respectively. They all come with a constructor function of the
form make_<type name>; for example,
int2 make_int2(int x, int y);
which creates a vector of type int2 with value (x, y).
In host code, the alignment requirement of a vector type is equal to the alignment
requirement of its base type. This is not always the case in device code as detailed in
Table B-1.
Table B-1. Alignment Requirements in Device Code
Type Alignment
char1, uchar1 1
char2, uchar2 2
char3, uchar3 1
char4, uchar4 4
short1, ushort1 2
short2, ushort2 4
short3, ushort3 2
short4, ushort4 8
int1, uint1 4
int2, uint2 8
int3, uint3 4
int4, uint4 16
long1, ulong1 4 if sizeof(long) is equal to sizeof(int),
8, otherwise
long2, ulong2 8 if sizeof(long) is equal to sizeof(int),
16, otherwise
long3, ulong3 4 if sizeof(long) is equal to sizeof(int),
8, otherwise
long4, ulong4 16
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longlong1, ulonglong1 8
longlong2, ulonglong2 16
float1 4
float2 8
float3 4
float4 16
double1 8
double2 16
B.3.2 dim3
This type is an integer vector type based on uint3 that is used to specify
dimensions. When defining a variable of type dim3, any component left unspecified
is initialized to 1.
B.4 Built-in Variables
Built-in variables specify the grid and block dimensions and the block and thread
indices. They are only valid within functions that are executed on the device.
B.4.1 gridDim
This variable is of type dim3 (see Section B.3.2) and contains the dimensions of the
grid.
B.4.2 blockIdx
This variable is of type uint3 (see Section B.3.1) and contains the block index
within the grid.
B.4.3 blockDim
This variable is of type dim3 (see Section B.3.2) and contains the dimensions of the
block.
B.4.4 threadIdx
This variable is of type uint3 (see Section B.3.1) and contains the thread index
within the block.
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B.4.5 warpSize
This variable is of type int and contains the warp size in threads (see Section 4.1
for the definition of a warp).
B.4.6 Restrictions
 It is not allowed to take the address of any of the built-in variables.
 It is not allowed to assign values to any of the built-in variables.
B.5 Memory Fence Functions
void __threadfence_block();
waits until all global and shared memory accesses made by the calling thread prior to
__threadfence_block() are visible to all threads in the thread block.
void __threadfence();
waits until all global and shared memory accesses made by the calling thread prior to
__threadfence() are visible to:
 All threads in the thread block for shared memory accesses,
 All threads in the device for global memory accesses.
void __threadfence_system();
waits until all global and shared memory accesses made by the calling thread prior to
__threadfence_system() are visible to:
 All threads in the thread block for shared memory accesses,
 All threads in the device for global memory accesses,
 Host threads for page-locked host memory accesses (see Section 3.2.5.3).
__threadfence_system() is only supported by devices of compute
capability 2.x.
In general, when a thread issues a series of writes to memory in a particular order,
other threads may see the effects of these memory writes in a different order.
__threadfence_block(), __threadfence(), and
__threadfence_system() can be used to enforce some ordering.
One use case is when threads consume some data produced by other threads as
illustrated by the following code sample of a kernel that computes the sum of an
array of N numbers in one call. Each block first sums a subset of the array and
stores the result in global memory. When all blocks are done, the last block done
reads each of these partial sums from global memory and sums them to obtain the
final result. In order to determine which block is finished last, each block atomically
increments a counter to signal that it is done with computing and storing its partial
sum (see Section B.11 about atomic functions). The last block is the one that
receives the counter value equal to gridDim.x-1. If no fence is placed between
storing the partial sum and incrementing the counter, the counter might increment
before the partial sum is stored and therefore, might reach gridDim.x-1 and let
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the last block start reading partial sums before they have been actually updated in
memory.
__device__ unsigned int count = 0;
__shared__ bool isLastBlockDone;
__global__ void sum(const float* array, unsigned int N,
float* result)
{
// Each block sums a subset of the input array
float partialSum = calculatePartialSum(array, N);

if (threadIdx.x == 0) {

// Thread 0 of each block stores the partial sum
// to global memory
result[blockIdx.x] = partialSum;

// Thread 0 makes sure its result is visible to
// all other threads
__threadfence();

// Thread 0 of each block signals that it is done
unsigned int value = atomicInc(&count, gridDim.x);

// Thread 0 of each block determines if its block is
// the last block to be done
isLastBlockDone = (value == (gridDim.x - 1));
}

// Synchronize to make sure that each thread reads
// the correct value of isLastBlockDone
__syncthreads();

if (isLastBlockDone) {

// The last block sums the partial sums
// stored in result[0 .. gridDim.x-1]
float totalSum = calculateTotalSum(result);

if (threadIdx.x == 0) {

// Thread 0 of last block stores total sum
// to global memory and resets count so that
// next kernel call works properly
result[0] = totalSum;
count = 0;
}
}
}
B.6 Synchronization Functions
void __syncthreads();
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waits until all threads in the thread block have reached this point and all global and
shared memory accesses made by these threads prior to __syncthreads() are
visible to all threads in the block.
__syncthreads() is used to coordinate communication between the threads of
the same block. When some threads within a block access the same addresses in
shared or global memory, there are potential read-after-write, write-after-read, or
write-after-write hazards for some of these memory accesses. These data hazards
can be avoided by synchronizing threads in-between these accesses.
__syncthreads() is allowed in conditional code but only if the conditional
evaluates identically across the entire thread block, otherwise the code execution is
likely to hang or produce unintended side effects.
Devices of compute capability 2.x support three variations of __syncthreads()
described below.
int __syncthreads_count(int predicate);
is identical to __syncthreads() with the additional feature that it evaluates
predicate for all threads of the block and returns the number of threads for
which predicate evaluates to non-zero.
int __syncthreads_and(int predicate);
is identical to __syncthreads() with the additional feature that it evaluates
predicate for all threads of the block and returns non-zero if and only if
predicate evaluates to non-zero for all of them.
int __syncthreads_or(int predicate);
is identical to __syncthreads() with the additional feature that it evaluates
predicate for all threads of the block and returns non-zero if and only if
predicate evaluates to non-zero for any of them.
B.7 Mathematical Functions
Section C.1 contains a comprehensive list of the C/C++ standard library
mathematical functions that are currently supported in device code, along with their
respective error bounds. When executed in host code, a given function uses the C
runtime implementation if available.
For some of the functions of Section C.1, a less accurate, but faster version exists in
the device runtime component; it has the same name prefixed with __ (such as
__sinf(x)). These intrinsic functions are listed in Section C.2, along with their
respective error bounds.
The compiler has an option (-use_fast_math) that forces each function in Table
B-2 to compile to its intrinsic counterpart. In addition to reduce accuracy of the
affected functions, it may also cause some differences in special case handling. A
more robust approach is to selectively replace mathematical function calls by calls to
intrinsic functions only where it is merited by the performance gains and where
changed properties such as reduced accuracy and different special case handling can
be tolerated.
Table B-2. Functions Affected by –use_fast_math
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Operator/Function Device Function
x/y __fdividef(x,y)
sinf(x) __sinf(x)
cosf(x) __cosf(x)
tanf(x) __tanf(x)
sincosf(x,sptr,cptr) __sincosf(x,sptr,cptr)
logf(x) __logf(x)
log2f(x) __log2f(x)
log10f(x) __log10f(x)
expf(x) __expf(x)
exp10f(x) __exp10f(x)
powf(x,y) __powf(x,y)
B.8 Texture Functions
For texture functions, a combination of the texture reference‟s immutable (i.e.
compile-time) and mutable (i.e. runtime) attributes determine how the texture
coordinates are interpreted, what processing occurs during the texture fetch, and the
return value delivered by the texture fetch. Immutable attributes are described in
Section 3.2.4.1.1. Mutable attributes are described in Section 3.2.4.1.2. Texture
fetching is described in Appendix F.
B.8.1 tex1Dfetch()
template<class Type>
Type tex1Dfetch(
texture<Type, 1, cudaReadModeElementType> texRef,
int x);

float tex1Dfetch(
texture<unsigned char, 1, cudaReadModeNormalizedFloat> texRef,
int x);

float tex1Dfetch(
texture<signed char, 1, cudaReadModeNormalizedFloat> texRef,
int x);

float tex1Dfetch(
texture<unsigned short, 1, cudaReadModeNormalizedFloat> texRef,
int x);

float tex1Dfetch(
texture<signed short, 1, cudaReadModeNormalizedFloat> texRef,
int x);
fetch the region of linear memory bound to texture reference texRef using integer
texture coordinate x. No texture filtering and addressing modes are supported. For
integer types, these functions may optionally promote the integer to single-precision
floating point.
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Besides the functions shown above, 2-, and 4-tuples are supported; for example:
float4 tex1Dfetch(
texture<uchar4, 1, cudaReadModeNormalizedFloat> texRef,
int x);
fetches the region of linear memory bound to texture reference texRef using
texture coordinate x.
B.8.2 tex1D()
template<class Type, enum cudaTextureReadMode readMode>
Type tex1D(texture<Type, 1, readMode> texRef,
float x);
fetches the CUDA array bound to texture reference texRef using texture
coordinate x.
B.8.3 tex2D()
template<class Type, enum cudaTextureReadMode readMode>
Type tex2D(texture<Type, 2, readMode> texRef,
float x, float y);
fetches the CUDA array or the region of linear memory bound to texture reference
texRef using texture coordinates x and y.
B.8.4 tex3D()
template<class Type, enum cudaTextureReadMode readMode>
Type tex3D(texture<Type, 3, readMode> texRef,
float x, float y, float z);
fetches the CUDA array bound to texture reference texRef using texture
coordinates x, y, and z.
B.9 Surface Functions
Surface functions are only supported by devices of compute capability 2.0 and
higher.
Surface reference declaration is described in Section 3.2.4.2.1 and surface binding in
Section 3.2.4.2.2.
In the sections below, boundaryMode specifies the boundary mode, that is how
out-of-range surface coordinates are handled; it is equal to either
cudaBoundaryModeClamp, in which case out-of-range coordinates are clamped
to the valid range, or cudaBoundaryModeZero, in which case out-of-range reads
return zero and out-of-range writes are ignored, or cudaBoundaryModeTrap, in
which case out-of-range accesses cause the kernel execution to fail.
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B.9.1 surf1Dread()
template<class Type>
Type surf1Dread(surface<void, 1> surfRef, int x,
boundaryMode = cudaBoundaryModeTrap);
reads the CUDA array bound to surface reference surfRef using coordinate x.
B.9.2 surf1Dwrite()
template<class Type>
void surf1Dwrite(Type data, surface<void, 1> surfRef, int x,
boundaryMode = cudaBoundaryModeTrap);
writes value data to the CUDA array bound to surface reference surfRef at
coordinate x.
B.9.3 surf2Dread()
template<class Type>
Type surf2Dread(surface<void, 2> surfRef,
int x, int y,
boundaryMode = cudaBoundaryModeTrap);
reads the CUDA array bound to surface reference surfRef using coordinates x
and y.
B.9.4 surf2Dwrite()
template<class Type>
void surf2Dwrite(Type data, surface<void, 2> surfRef,
int x, int y,
boundaryMode = cudaBoundaryModeTrap);
writes value data to the CUDA array bound to surface reference surfRef at
coordinate x and y.
B.10 Time Function
clock_t clock();
when executed in device code, returns the value of a per-multiprocessor counter
that is incremented every clock cycle. Sampling this counter at the beginning and at
the end of a kernel, taking the difference of the two samples, and recording the
result per thread provides a measure for each thread of the number of clock cycles
taken by the device to completely execute the thread, but not of the number of
clock cycles the device actually spent executing thread instructions. The former
number is greater that the latter since threads are time sliced.
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B.11 Atomic Functions
An atomic function performs a read-modify-write atomic operation on one 32-bit or
64-bit word residing in global or shared memory. For example, atomicAdd()
reads a 32-bit word at some address in global or shared memory, adds a number to
it, and writes the result back to the same address. The operation is atomic in the
sense that it is guaranteed to be performed without interference from other threads.
In other words, no other thread can access this address until the operation is
complete.
Atomic functions can only be used in device functions and are only available for
devices of compute capability 1.1 and above.
Atomic functions operating on shared memory and atomic functions operating on
64-bit words are only available for devices of compute capability 1.2 and above.
Atomic functions operating on 64-bit words in shared memory are only available for
devices of compute capability 2.x and higher.
Atomic functions operating on mapped page-locked memory (Section 3.2.5.3) are
not atomic from the point of view of the host or other devices.
Atomic operations only work with signed and unsigned integers with the exception
of atomicAdd() for devices of compute capability 2.x and atomicExch() for all
devices, that also work for single-precision floating-point numbers. Note however
that any atomic operation can be implemented based on atomicCAS() (Compare
And Swap). For example, atomicAdd() for double-precision floating-point
numbers can be implemented as follows:
__device__ double atomicAdd(double* address, double val)
{
double old = *address, assumed;
do {
assumed = old;
old =
__longlong_as_double(
atomicCAS((unsigned long long int*)address,
__double_as_longlong(assumed),
__double_as_longlong(val + assumed)));
} while (assumed != old);
return old;
}
B.11.1 Arithmetic Functions
B.11.1.1 atomicAdd()
int atomicAdd(int* address, int val);
unsigned int atomicAdd(unsigned int* address,
unsigned int val);
unsigned long long int atomicAdd(unsigned long long int* address,
unsigned long long int val);
float atomicAdd(float* address, float val);
reads the 32-bit or 64-bit word old located at the address address in global or
shared memory, computes (old + val), and stores the result back to memory at
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the same address. These three operations are performed in one atomic transaction.
The function returns old.
The floating-point version of atomicAdd() is only supported by devices of
compute capability 2.x.
B.11.1.2 atomicSub()
int atomicSub(int* address, int val);
unsigned int atomicSub(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes (old - val), and stores the result back to memory at the
same address. These three operations are performed in one atomic transaction. The
function returns old.
B.11.1.3 atomicExch()
int atomicExch(int* address, int val);
unsigned int atomicExch(unsigned int* address,
unsigned int val);
unsigned long long int atomicExch(unsigned long long int* address,
unsigned long long int val);
float atomicExch(float* address, float val);
reads the 32-bit or 64-bit word old located at the address address in global or
shared memory and stores val back to memory at the same address. These two
operations are performed in one atomic transaction. The function returns old.
B.11.1.4 atomicMin()
int atomicMin(int* address, int val);
unsigned int atomicMin(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes the minimum of old and val, and stores the result back to
memory at the same address. These three operations are performed in one atomic
transaction. The function returns old.
B.11.1.5 atomicMax()
int atomicMax(int* address, int val);
unsigned int atomicMax(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes the maximum of old and val, and stores the result back to
memory at the same address. These three operations are performed in one atomic
transaction. The function returns old.
B.11.1.6 atomicInc()
unsigned int atomicInc(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes ((old >= val) ? 0 : (old+1)), and stores the result
back to memory at the same address. These three operations are performed in one
atomic transaction. The function returns old.
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B.11.1.7 atomicDec()
unsigned int atomicDec(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes (((old == 0) | (old > val)) ? val : (old-1)),
and stores the result back to memory at the same address. These three operations
are performed in one atomic transaction. The function returns old.
B.11.1.8 atomicCAS()
int atomicCAS(int* address, int compare, int val);
unsigned int atomicCAS(unsigned int* address,
unsigned int compare,
unsigned int val);
unsigned long long int atomicCAS(unsigned long long int* address,
unsigned long long int compare,
unsigned long long int val);
reads the 32-bit or 64-bit word old located at the address address in global or
shared memory, computes (old == compare ? val : old), and stores the
result back to memory at the same address. These three operations are performed in
one atomic transaction. The function returns old (Compare And Swap).
B.11.2 Bitwise Functions
B.11.2.1 atomicAnd()

int atomicAnd(int* address, int val);
unsigned int atomicAnd(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes (old & val), and stores the result back to memory at the
same address. These three operations are performed in one atomic transaction. The
function returns old.
B.11.2.2 atomicOr()

int atomicOr(int* address, int val);
unsigned int atomicOr(unsigned int* address,
unsigned int val);
reads the 32-bit word old located at the address address in global or shared
memory, computes (old | val), and stores the result back to memory at the
same address. These three operations are performed in one atomic transaction. The
function returns old.
B.11.2.3 atomicXor()

int atomicXor(int* address, int val);
unsigned int atomicXor(unsigned int* address,
unsigned int val);
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reads the 32-bit word old located at the address address in global or shared
memory, computes (old ^ val), and stores the result back to memory at the
same address. These three operations are performed in one atomic transaction. The
function returns old.
B.12 Warp Vote Functions
Warp vote functions are only supported by devices of compute capability 1.2 and
higher (see Section 4.1 for the definition of a warp).
int __all(int predicate);
evaluates predicate for all threads of the warp and returns non-zero if and only if
predicate evaluates to non-zero for all of them.
int __any(int predicate);
evaluates predicate for all threads of the warp and returns non-zero if and only if
predicate evaluates to non-zero for any of them.
unsigned int __ballot(int predicate);
evaluates predicate for all threads of the warp and returns an integer whose N
th

bit is set if and only if predicate evaluates to non-zero for the N
th
thread of the
warp. This function is only supported by devices of compute capability 2.x.
B.13 Profiler Counter Function
Each multiprocessor has a set of sixteen hardware counters that an application can
increment with a single instruction by calling the __prof_trigger() function.
void __prof_trigger(int counter);
increments by one per warp the per-multiprocessor hardware counter of index
counter. Counters 8 to 15 are reserved and should not be used by applications.
The value of counters 0, 1, …, 7 for the first multiprocessor can be obtained via the
CUDA profiler by listing prof_trigger_00, prof_trigger_01, …,
prof_trigger_07, etc. in the profiler.conf file (see the profiler manual for
more details). All counters are reset before each kernel call (note that when an
application is run via a CUDA debugger or profiler (cuda-gdb, CUDA Visual
Profiler, Parallel Nsight), all launches are synchronous).
B.14 Formatted Output
Formatted output is only supported by devices of compute capability 2.x.
int printf(const char *format[, arg, ...]);
prints formatted output from a kernel to a host-side output stream.
The in-kernel printf() function behaves in a similar way to the standard C-library
printf() function, and the user is referred to the host system‟s manual pages for a
complete description of printf() behavior. In essence, the string passed in as
format is output to a stream on the host, with substitutions made from the
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argument list wherever a format specifier is encountered. Supported format
specifiers are listed below.
The printf() command is executed as any other device-side function: per-thread,
and in the context of the calling thread. From a multi-threaded kernel, this means
that a straightforward call to printf() will be executed by every thread, using that
thread‟s data as specified. Multiple versions of the output string will then appear at
the host stream, once for each thread which encountered the printf().
It is up to the programmer to limit the output to a single thread if only a single
output string is desired (see Section B.14.4 for an illustrative example).
Unlike the C-standard printf(), which returns the number of characters printed,
CUDA‟s printf() returns the number of arguments parsed. If no arguments
follow the format string, 0 is returned. If the format string is NULL, -1 is returned.
If an internal error occurs, -2 is returned.
B.14.1 Format Specifiers
As for standard printf(), format specifiers take the form:
%[flags][width][.precision][size]type
The following fields are supported (see widely-available documentation for a
complete description of all behaviors):
 Flags: „#‟ „ „ „0‟ „+‟ „-„
 Width: „*‟ „0-9‟
 Precision: „0-9‟
 Size: „h‟ „l‟ „ll‟
 Type: „%cdiouxXpeEfgGaAs‟
Note that CUDA‟s printf() will accept any combination of flag, width, precision,
size and type, whether or not overall they form a valid format specifier. In other
words, “%hd” will be accepted and printf will expect a double-precision variable in
the corresponding location in the argument list.
B.14.2 Limitations
Final formatting of the printf() output takes place on the host system. This
means that the format string must be understood by the host-system‟s compiler and
C library. Every effort has been made to ensure that the format specifiers supported
by CUDA‟s printf function form a universal subset from the most common host
compilers, but exact behavior will be host-O/S-dependent.
As described in Section B.14.1, printf() will accept all combinations of valid flags
and types. This is because it cannot determine what will and will not be valid on the
host system where the final output is formatted. The effect of this is that output
may be undefined if the program emits a format string which contains invalid
combinations.
The output buffer for printf() is set to a fixed size before kernel launch (see
below). This buffer is circular, and is flushed at any host-side synchronisation point
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and at when the context is explicitly destroyed; if more output is produced during
kernel execution than can fit in the buffer, older output is overwritten.
The printf() command can accept at most 32 arguments in addition to the
format string. Additional arguments beyond this will be ignored, and the format
specifier output as-is.
Owing to the differing size of the long type on 64-bit Windows platforms (four
bytes on 64-bit Windows platforms, eight bytes on other 64-bit platforms), a kernel
which is compiled on a non-Windows 64-bit machine but then run on a win64
machine will see corrupted output for all format strings which include “%ld”. It is
recommended that the compilation platform matches the execution platform to
ensure safety.
The output buffer for printf() is not flushed automatically to the output stream,
but instead is flushed only when one of these actions is performed:
 Kernel launch via <<<>>> or cuLaunch(),
 Synchronization via cudaThreadSynchronize(),
cuCtxSynchronize(), cudaStreamSynchronize(), or
cuStreamSynchronize(),
 Module loading/unloading via cuModuleLoad() or cuModuleUnload(),
 Context destruction via cudaThreadExit() or cuCtxDestroy().
Note that the buffer is not flushed automatically when the program exits. The user
must call cudaThreadExit() or cuCtxDestroy() explicitly, as shown in the
examples below.
B.14.3 Associated Host-Side API
The following API functions get and set the size of the buffer used to transfer the
printf() arguments and internal metadata to the host (default is 1 megabyte):
 Driver API:
cuCtxGetLimit(size_t* size, CU_LIMIT_PRINTF_FIFO_SIZE)
cuCtxSetLimit(CU_LIMIT_PRINTF_FIFO_SIZE, size_t size)
 Runtime API:
cudaThreadGetLimit(size_t* size,cudaLimitPrintfFifoSize)
cudaThreadSetLimit(cudaLimitPrintfFifoSize, size_t size)
B.14.4 Examples
The following code sample:
__global__ void helloCUDA(float f)
{
printf(“Hello thread %d, f=%f\n”, threadIdx.x, f) ;
}

void main()
{
helloCUDA<<<1, 5>>>(1.2345f);
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122 CUDA C Programming Guide Version 3.2

cudaThreadExit();
}
will output:
Hello thread 0, f=1.2345
Hello thread 1, f=1.2345
Hello thread 2, f=1.2345
Hello thread 3, f=1.2345
Hello thread 4, f=1.2345
Notice how each thread encounters the printf() command, so there are as many
lines of output as there were threads launched in the grid. As expected, global values
(i.e. float f) are common between all threads, and local values (i.e.
threadIdx.x) are distinct per-thread.
The following code sample:
__global__ void helloCUDA(float f)
{
if (threadIdx.x == 0)
printf(“Hello thread %d, f=%f\n”, threadIdx.x, f) ;
}

void main()
{
helloCUDA<<<1, 5>>>(1.2345f);
cudaThreadExit();
}
will output:
Hello thread 0, f=1.2345
Self-evidently, the if() statement limits which threads will call printf, so that
only a single line of output is seen.
B.15 Dynamic Global Memory Allocation
void* malloc(size_t size);
void free(void* ptr);
allocate and free memory dynamically from a fixed-size heap in global memory.
The CUDA in-kernel malloc() function allocates at least size bytes from the
device heap and returns a pointer to the allocated memory or NULL if insufficient
memory exists to fulfill the request. The returned pointer is guaranteed to be aligned
to a 16-byte boundary.
The CUDA in-kernel free() function deallocates the memory pointed to by ptr,
which must have been returned by a previous call to malloc(). If ptr is NULL,
the call to free() is ignored. Repeated calls to free() with the same ptr has
undefined behavior.
The memory allocated by a given CUDA thread via malloc() remains allocated
for the lifetime of the CUDA context, or until it is explicitly released by a call to
free(). It can be used by any other CUDA threads even from subsequent kernel
launches. Any CUDA thread may free memory allocated by another thread, but care
should be taken to ensure that the same pointer is not freed more than once.
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B.15.1 Heap Memory Allocation
The device memory heap has a fixed size that must be specified before any program
using malloc() or free() is loaded into the context. A default heap of eight
megabytes is allocated if any program uses malloc() without explicitly specifying
the heap size.
The following API functions get and set the heap size:
 Driver API:
cuCtxGetLimit(size_t* size, CU_LIMIT_MALLOC_HEAP_SIZE)
cuCtxSetLimit(CU_LIMIT_MALLOC_HEAP_SIZE, size_t size)
 Runtime API:
cudaThreadGetLimit(size_t* size, cudaLimitMallocHeapSize)
cudaThreadSetLimit(cudaLimitMallocHeapSize, size_t size)
The heap size granted will be at least size bytes. cuCtxGetLimit() and
cudaThreadGetLimit() return the currently requested heap size.
The actual memory allocation for the heap occurs when a module is loaded into the
context, either explicitly via the CUDA driver API (see Section 3.3.2), or implicitly
via the CUDA runtime API (see Section 3.2). If the memory allocation fails, the
module load will generate a CUDA_ERROR_SHARED_OBJECT_INIT_FAILED
error.
Heap size cannot be changed once a module load has occurred and it does not
resize dynamically according to need.
Memory reserved for the device heap is in addition to memory allocated through
host-side CUDA API calls such as cudaMalloc().
B.15.2 Interoperability with Host Memory API
Memory allocated via malloc() cannot be freed using the runtime or driver API
(i.e. by calling any of the free memory functions from Sections 3.2.1 and 3.3.4).
Similarly, memory allocated via the runtime or driver API (i.e. by calling any of the
memory allocation functions from Sections 3.2.1 and 3.3.4) cannot be freed via
free().
Memory allocated via malloc() can be copied using the runtime or driver API (i.e.
by calling any of the copy memory functions from Sections 3.2.1 and 3.3.4).
B.15.3 Examples
B.15.3.1 Per Thread Allocation
The following code sample:
__global__ void mallocTest()
{
char* ptr = (char*)malloc(123);
printf(“Thread %d got pointer: %p\n”, threadIdx.x, ptr);
free(ptr);
Appendix B. C Language Extensions


124 CUDA C Programming Guide Version 3.2

}

void main()
{
// Set a heap size of 128 megabytes. Note that this must
// be done before any kernel is launched.
cudaThreadSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<1, 5>>>();
cudaThreadSynchronize();
}

will output:
Thread 0 got pointer: 00057020
Thread 1 got pointer: 0005708c
Thread 2 got pointer: 000570f8
Thread 3 got pointer: 00057164
Thread 4 got pointer: 000571d0
Notice how each thread encounters the malloc() command and so receives its
own allocation. (Exact pointer values will vary: these are illustrative.)
B.15.3.2 Per Thread Block Allocation
__global__ void mallocTest()
{
__shared__ int* data;

// The first thread in the block does the allocation
// and then shares the pointer with all other threads
// through shared memory, so that access can easily be
// coalesced. 64 bytes per thread are allocated.
if (threadIdx.x == 0)
data = (int*)malloc(blockDim.x * 64);
__syncthreads();

// Check for failure
if (data == NULL)
return;

// Threads index into the memory, ensuring coalescence
int* ptr = data;
for (int i = 0; i < 64; ++i)
ptr[i * blockDim.x + threadIdx.x] = threadIdx.x;

// Ensure all threads complete before freeing
__syncthreads();

// Only one thread may free the memory!
if (threadIdx.x == 0)
free(data);
}

void main()
{
cudaThreadSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);
mallocTest<<<10, 128>>>();
cudaThreadSynchronize();
Appendix B. C Language Extensions


CUDA C Programming Guide Version 3.2 125

}
B.15.3.3 Allocation Persisting Between Kernel Launches
#define NUM_BLOCKS 20

__device__ int* dataptr[NUM_BLOCKS]; // Per-block pointer

__global__ void allocmem()
{
// Only the first thread in the block does the allocation
// since we want only one allocation per block.
if (threadIdx.x == 0)
dataptr[blockIdx.x] = (int*)malloc(blockDim.x * 4);
__syncthreads();

// Check for failure
if (dataptr[blockIdx.x] == NULL)
return;

// Zero the data with all threads in parallel
dataptr[blockIdx.x][threadIdx.x] = 0;
}

// Simple example: store thread ID into each element
__global__ void usemem()
{
int* ptr = dataptr[blockIdx.x];
if (ptr != NULL)
ptr[threadIdx.x] += threadIdx.x;
}

// Print the content of the buffer before freeing it
__global__ void freemem()
{
int* ptr = dataptr[blockIdx.x];
if (ptr != NULL)
printf(“Block %d, Thread %d: final value = %d\n”,
blockIdx.x, threadIdx.x, ptr[threadIdx.x]);

// Only free from one thread!
if (threadIdx.x == 0)
free(ptr);
}

void main()
{
cudaThreadSetLimit(cudaLimitMallocHeapSize, 128*1024*1024);

// Allocate memory
allocmem<<< NUM_BLOCKS, 10 >>>();

// Use memory
usemem<<< NUM_BLOCKS, 10 >>>();
usemem<<< NUM_BLOCKS, 10 >>>();
usemem<<< NUM_BLOCKS, 10 >>>();

// Free memory
Appendix B. C Language Extensions


126 CUDA C Programming Guide Version 3.2

freemem<<< NUM_BLOCKS, 10 >>>();

cudaThreadSynchronize();
}
B.16 Execution Configuration
Any call to a __global__ function must specify the execution configuration for that
call. The execution configuration defines the dimension of the grid and blocks that
will be used to execute the function on the device, as well as the associated stream
(see Section 3.3.9.1 for a description of streams).
When using the driver API, the execution configuration is specified through a series
of driver function calls as detailed in Section 3.3.3.
When using the runtime API (Section 3.2), the execution configuration is specified
by inserting an expression of the form <<< Dg, Db, Ns, S >>> between the
function name and the parenthesized argument list, where:
 Dg is of type dim3 (see Section B.3.2) and specifies the dimension and size of
the grid, such that Dg.x * Dg.y equals the number of blocks being launched;
Dg.z must be equal to 1;
 Db is of type dim3 (see Section B.3.2) and specifies the dimension and size of
each block, such that Db.x * Db.y * Db.z equals the number of threads
per block;
 Ns is of type size_t and specifies the number of bytes in shared memory that
is dynamically allocated per block for this call in addition to the statically
allocated memory; this dynamically allocated memory is used by any of the
variables declared as an external array as mentioned in Section B.2.3; Ns is an
optional argument which defaults to 0;
 S is of type cudaStream_t and specifies the associated stream; S is an
optional argument which defaults to 0.
As an example, a function declared as
__global__ void Func(float* parameter);
must be called like this:
Func<<< Dg, Db, Ns >>>(parameter);
The arguments to the execution configuration are evaluated before the actual
function arguments and like the function arguments, are currently passed via shared
memory to the device.
The function call will fail if Dg or Db are greater than the maximum sizes allowed
for the device as specified in Appendix G, or if Ns is greater than the maximum
amount of shared memory available on the device, minus the amount of shared
memory required for static allocation, functions arguments (for devices of compute
capability 1.x), and execution configuration.
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CUDA C Programming Guide Version 3.2 127

B.17 Launch Bounds
As discussed in detail in Section 5.2.3, the fewer registers a kernel uses, the more
threads and thread blocks are likely to reside on a multiprocessor, which can
improve performance.
Therefore, the compiler uses heuristics to minimize register usage while keeping
register spilling (see Section 5.3.2.2) and instruction count to a minimum. An
application can optionally aid these heuristics by providing additional information to
the compiler in the form of launch bounds that are specified using the
__launch_bounds__() qualifier in the definition of a __global__ function:
__global__ void
__launch_bounds__(maxThreadsPerBlock, minBlocksPerMultiprocessor)
MyKernel(...)
{
...
}
 maxThreadsPerBlock specifies the maximum number of threads per block
with which the application will ever launch MyKernel(); it compiles to the
.maxntid PTX directive;
 minBlocksPerMultiprocessor is optional and specifies the desired
minimum number of resident blocks per multiprocessor; it compiles to the
.minnctapersm PTX directive.
If launch bounds are specified, the compiler first derives from them the upper limit
L on the number of registers the kernel should use to ensure that
minBlocksPerMultiprocessor blocks (or a single block if
minBlocksPerMultiprocessor is not specified) of maxThreadsPerBlock
threads can reside on the multiprocessor (see Section 4.2 for the relationship
between the number of registers used by a kernel and the number of registers
allocated per block). The compiler then optimizes register usage in the following
way:
 If the initial register usage is higher than L, the compiler reduces it further until
it becomes less or equal to L, usually at the expense of more local memory
usage and/or higher number of instructions;
 If the initial register usage is lower than L,
 If maxThreadsPerBlock is specified and
minBlocksPerMultiprocessor is not, the compiler uses
maxThreadsPerBlock to determine the register usage thresholds for the
transitions between n and n+1 resident blocks (i.e. when using one less
register makes room for an additional resident block as in the example of
Section 5.2.3) and then applies similar heuristics as when no launch bounds
are specified;
 If both minBlocksPerMultiprocessor and maxThreadsPerBlock
are specified, the compiler may increase register usage as high as L to
reduce the number of instructions and better hide single thread instruction
latency.
A kernel will fail to launch if it is executed with more threads per block than its
launch bound maxThreadsPerBlock.
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128 CUDA C Programming Guide Version 3.2

Optimal launch bounds for a given kernel will usually differ across major
architecture revisions. The sample code below shows how this is typically handled in
device code using the __CUDA_ARCH__ macro introduced in Section 3.1.4.
#define THREADS_PER_BLOCK 256
#if __CUDA_ARCH__ >= 200
#define MY_KERNEL_MAX_THREADS (2 * THREADS_PER_BLOCK)
#define MY_KERNEL_MIN_BLOCKS 3
#else
#define MY_KERNEL_MAX_THREADS THREADS_PER_BLOCK
#define MY_KERNEL_MIN_BLOCKS 2
#endif

// Device code
__global__ void
__launch_bounds__(MY_KERNEL_MAX_THREADS, MY_KERNEL_MIN_BLOCKS)
MyKernel(...)
{
...
}
In the common case where MyKernel is invoked with the maximum number of
threads per block (specified as the first parameter of __launch_bounds__()), it
is tempting to use MY_KERNEL_MAX_THREADS as the number of threads per block
in the execution configuration:
// Host code
MyKernel<<<blocksPerGrid, MY_KERNEL_MAX_THREADS>>>(...);
This will not work however since __CUDA_ARCH__ is undefined in host code as
mentioned in Section 3.1.4, so MyKernel will launch with 256 threads per block
even when __CUDA_ARCH__ is greater or equal to 200. Instead the number of
threads per block should be determined:
 Either at compile time using a macro that does not depend on
__CUDA_ARCH__, for example
// Host code
MyKernel<<<blocksPerGrid, THREADS_PER_BLOCK>>>(...);
 Or at runtime based on the compute capability
// Host code
cudaGetDeviceProperties(&deviceProp, device);
int threadsPerBlock =
(deviceProp.major >= 2 ?
2 * THREADS_PER_BLOCK : THREADS_PER_BLOCK);
MyKernel<<<blocksPerGrid, threadsPerBlock>>>(...);
Register usage is reported by the --ptxas-options=-v compiler option. The
number of resident blocks can be derived from the occupancy reported by the
CUDA profiler (see Section 5.2.3 for a definition of occupancy).
Register usage can also be controlled for all __global__ functions in a file using
the -maxrregcount compiler option. The value of -maxrregcount is ignored
for functions with launch bounds.








CUDA C Programming Guide Version 3.1 129

Appendix C.
Mathematical Functions
Functions from Section C.1 can be used in both host and device code whereas
functions from Section C.2 can only be used in device code.
Note that floating-point functions are overloaded, so that in general, there are three
prototypes for a given function <func-name>:
(1) double <func-name>(double), e.g. double log(double)
(2) float <func-name>(float), e.g. float log(float)
(3) float <func-name>f(float), e.g. float logf(float)
This means, in particular, that passing a float argument always results in a float
result (variants (2) and (3) above).
C.1 Standard Functions
This section lists all the mathematical standard library functions supported in device
code. It also specifies the error bounds of each function when executed on the
device. These error bounds also apply when the function is executed on the host in
the case where the host does not supply the function. They are generated from
extensive but not exhaustive tests, so they are not guaranteed bounds.
C.1.1 Single-Precision Floating-Point Functions
Addition and multiplication are IEEE-compliant, so have a maximum error of
0.5 ulp. However, on the device, the compiler often combines them into a single
multiply-add instruction (FMAD) and for devices of compute capability 1.x, FMAD
truncates the intermediate result of the multiplication as mentioned in Section G.2.
This combination can be avoided by using the __fadd_rn() and __fmul_rn()
intrinsic functions (see Section C.2).
The recommended way to round a single-precision floating-point operand to an
integer, with the result being a single-precision floating-point number is rintf(),
not roundf(). The reason is that roundf() maps to an 8-instruction sequence on
the device, whereas rintf() maps to a single instruction. truncf(), ceilf(),
and floorf() each map to a single instruction as well.
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130 CUDA C Programming Guide Version 3.2

Table C-1. Mathematical Standard Library Functions with
Maximum ULP Error
The maximum error is stated as the absolute value of the difference
in ulps between a correctly rounded single-precision result and the
result returned by the CUDA library function.
Function Maximum ulp error
x+y 0 (IEEE-754 round-to-nearest-even)
(except for devices of compute capability 1.x when addition is
merged into an FMAD)
x*y 0 (IEEE-754 round-to-nearest-even)
(except for devices of compute capability 1.x when
multiplication is merged into an FMAD)
x/y 0 for compute capability ≥ 2 when compiled with
-prec-div=true
2 (full range), otherwise
1/x 0 for compute capability ≥ 2 when compiled with
-prec-div=true
1 (full range), otherwise
rsqrtf(x)
1/sqrtf(x)
2 (full range)
Applies to 1/sqrtf(x) only when it is converted to
rsqrtf(x) by the compiler.
sqrtf(x) 0 for compute capability ≥ 2 when compiled with
-prec-sqrt=true
3 (full range), otherwise
cbrtf(x) 1 (full range)
rcbrtf(x) 2 (full range)
hypotf(x,y) 3 (full range)
expf(x) 2 (full range)
exp2f(x) 2 (full range)
exp10f(x) 2 (full range)
expm1f(x) 1 (full range)
logf(x) 1 (full range)
log2f(x) 3 (full range)
log10f(x) 3 (full range)
log1pf(x) 2 (full range)
sinf(x) 2 (full range)
cosf(x) 2 (full range)
tanf(x) 4 (full range)
sincosf(x,sptr,cptr) 2 (full range)
sinpif(x) 2 (full range)
asinf(x) 4 (full range)
acosf(x) 3 (full range)
atanf(x) 2 (full range)
atan2f(y,x) 3 (full range)
sinhf(x) 3 (full range)
coshf(x) 2 (full range)
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CUDA C Programming Guide Version 3.2 131

Function Maximum ulp error
tanhf(x) 2 (full range)
asinhf(x) 3 (full range)
acoshf(x) 4 (full range)
atanhf(x) 3 (full range)
powf(x,y) 8 (full range)
erff(x) 3 (full range)
erfcf(x) 6 (full range)
erfinvf(x) 3 (full range)
erfcinvf(x) 7 (full range)
lgammaf(x) 6 (outside interval -10.001 ... -2.264; larger inside)
tgammaf(x) 11 (full range)
fmaf(x,y,z) 0 (full range)
frexpf(x,exp) 0 (full range)
ldexpf(x,exp) 0 (full range)
scalbnf(x,n) 0 (full range)
scalblnf(x,l) 0 (full range)
logbf(x) 0 (full range)
ilogbf(x) 0 (full range)
fmodf(x,y) 0 (full range)
remainderf(x,y) 0 (full range)
remquof(x,y,iptr) 0 (full range)
modff(x,iptr) 0 (full range)
fdimf(x,y) 0 (full range)
truncf(x) 0 (full range)
roundf(x) 0 (full range)
rintf(x) 0 (full range)
nearbyintf(x) 0 (full range)
ceilf(x) 0 (full range)
floorf(x) 0 (full range)
lrintf(x) 0 (full range)
lroundf(x) 0 (full range)
llrintf(x) 0 (full range)
llroundf(x) 0 (full range)
signbit(x) N/A
isinf(x) N/A
isnan(x) N/A
isfinite(x) N/A
copysignf(x,y) N/A
fminf(x,y) N/A
fmaxf(x,y) N/A
fabsf(x) N/A
nanf(cptr) N/A
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132 CUDA C Programming Guide Version 3.2

Function Maximum ulp error
nextafterf(x,y) N/A
C.1.2 Double-Precision Floating-Point Functions
The errors listed below only apply when compiling for devices with native double-
precision support. When compiling for devices without such support, such as
devices of compute capability 1.2 and lower, the double type gets demoted to
float by default and the double-precision math functions are mapped to their
single-precision equivalents.
The recommended way to round a double-precision floating-point operand to an
integer, with the result being a double-precision floating-point number is rint(),
not round(). The reason is that round() maps to an 8-instruction sequence on
the device, whereas rint() maps to a single instruction. trunc(), ceil(), and
floor() each map to a single instruction as well.
Table C-2. Mathematical Standard Library Functions with
Maximum ULP Error
The maximum error is stated as the absolute value of the difference
in ulps between a correctly rounded double-precision result and the
result returned by the CUDA library function.
Function Maximum ulp error
x+y 0 (IEEE-754 round-to-nearest-even)
x*y 0 (IEEE-754 round-to-nearest-even)
x/y 0 (IEEE-754 round-to-nearest-even)
1/x 0 (IEEE-754 round-to-nearest-even)
sqrt(x) 0 (IEEE-754 round-to-nearest-even)
rsqrt(x) 1 (full range)
cbrt(x) 1 (full range)
rcbrt(x) 1 (full range)
hypot(x,y) 2 (full range)
exp(x) 1 (full range)
exp2(x) 1 (full range)
exp10(x) 1 (full range)
expm1(x) 1 (full range)
log(x) 1 (full range)
log2(x) 1 (full range)
log10(x) 1 (full range)
log1p(x) 1 (full range)
sin(x) 2 (full range)
cos(x) 2 (full range)
tan(x) 2 (full range)
sincos(x,sptr,cptr) 2 (full range)
sinpi(x) 2 (full range)
Appendix C. Mathematical Functions


CUDA C Programming Guide Version 3.2 133

Function Maximum ulp error
asin(x) 2 (full range)
acos(x) 2 (full range)
atan(x) 2 (full range)
atan2(y,x) 2 (full range)
sinh(x) 1 (full range)
cosh(x) 1 (full range)
tanh(x) 1 (full range)
asinh(x) 2 (full range)
acosh(x) 2 (full range)
atanh(x) 2 (full range)
pow(x,y) 2 (full range)
erf(x) 2 (full range)
erfc(x) 5 (full range)
erfinv(x) 8 (full range)
erfcinv(x) 8 (full range)
lgamma(x) 4 (outside interval -11.0001 ... -2.2637; larger inside)
tgamma(x) 8 (full range)
fma(x,y,z) 0 (IEEE-754 round-to-nearest-even)
frexp(x,exp) 0 (full range)
ldexp(x,exp) 0 (full range)
scalbn(x,n) 0 (full range)
scalbln(x,l) 0 (full range)
logb(x) 0 (full range)
ilogb(x) 0 (full range)
fmod(x,y) 0 (full range)
remainder(x,y) 0 (full range)
remquo(x,y,iptr) 0 (full range)
modf(x,iptr) 0 (full range)
fdim(x,y) 0 (full range)
trunc(x) 0 (full range)
round(x) 0 (full range)
rint(x) 0 (full range)
nearbyint(x) 0 (full range)
ceil(x) 0 (full range)
floor(x) 0 (full range)
lrint(x) 0 (full range)
lround(x) 0 (full range)
llrint(x) 0 (full range)
llround(x) 0 (full range)
signbit(x) N/A
isinf(x) N/A
isnan(x) N/A
Appendix C. Mathematical Functions


134 CUDA C Programming Guide Version 3.2

Function Maximum ulp error
isfinite(x) N/A
copysign(x,y) N/A
fmin(x,y) N/A
fmax(x,y) N/A
fabs(x) N/A
nan(cptr) N/A
nextafter(x,y) N/A
C.1.3 Integer Functions
Integer min(x,y) and max(x,y) are supported and map to a single instruction on
the device.
C.2 Intrinsic Functions
This section lists the intrinsic functions that are only supported in device code.
Among these functions are the less accurate, but faster versions of some of the
functions of Section C.1; they have the same name prefixed with __ (such as
__sinf(x)).
Functions suffixed with _rn operate using the round-to-nearest-even rounding
mode.
Functions suffixed with _rz operate using the round-towards-zero rounding mode.
Functions suffixed with _ru operate using the round-up (to positive infinity)
rounding mode.
Functions suffixed with _rd operate using the round-down (to negative infinity)
rounding mode.
C.2.1 Single-Precision Floating-Point Functions
__fadd_rn() and __fmul_rn() map to addition and multiplication operations
that the compiler never merges into FMADs. By contrast, additions and
multiplications generated from the '*' and '+' operators will frequently be combined
into FMADs.
The accuracy of floating-point division varies depending on the compute capability
of the device and whether the code is compiled with -prec-div=false or
-prec-div=true. For devices of compute capability 1.x or for devices of
compute capability 2.x when the code is compiled with -prec-div=false, both
the regular division “/” operator and __fdividef(x,y) have the same accuracy,
but for 2
126
< y < 2
128
, __fdividef(x,y) delivers a result of zero, whereas the
“/” operator delivers the correct result to within the accuracy stated in Table C-3.
Also, for 2
126
< y < 2
128
, if x is infinity, __fdividef(x,y) delivers a NaN (as a
result of multiplying infinity by zero), while the “/” operator returns infinity. For
Appendix C. Mathematical Functions


CUDA C Programming Guide Version 3.2 135

devices of compute capability 2.x when the code is compiled with
-prec-div=true, the “/” operator is IEEE compliant as mentioned in
Section C.1.1.
__saturate(x) returns 0 if x is less than 0, 1 if x is more than 1, and x
otherwise.
__float2ll_[rn,rz,ru,rd](x) (respectively
__float2ull_[rn,rz,ru,rd](x)) converts single-precision floating-point
parameter x to 64-bit signed (respectively unsigned) integer with specified IEEE-
754 rounding modes.
Table C-3. Single-Precision Floating-Point Intrinsic Functions
Supported by the CUDA Runtime Library with
Respective Error Bounds
Function Error bounds
__fadd_[rn,rz,ru,rd](x,y) IEEE-compliant.
__fmul_[rn,rz,ru,rd](x,y) IEEE-compliant.
__fmaf_[rn,rz,ru,rd](x,y,z) IEEE-compliant.
__frcp_[rn,rz,ru,rd](x) IEEE-compliant.
__fsqrt_[rn,rz,ru,rd](x) IEEE-compliant.
__fdiv_[rn,rz,ru,rd](x,y) IEEE-compliant.
__fdividef(x,y) For y in [2
-126
, 2
126
], the maximum ulp error is
2.
__expf(x) The maximum ulp error is
2 + floor(abs(1.16 * x)).
__exp10f(x) The maximum ulp error is
2 + floor(abs(2.95 * x)).
__logf(x) For x in [0.5, 2], the maximum absolute error
is 2
-21.41
, otherwise, the maximum ulp error is
3.
__log2f(x) For x in [0.5, 2], the maximum absolute error
is 2
-22
, otherwise, the maximum ulp error is 2.
__log10f(x) For x in [0.5, 2], the maximum absolute error
is 2
-24
, otherwise, the maximum ulp error is 3.
__sinf(x) For x in [-t, t], the maximum absolute error
is 2
-21.41
, and larger otherwise.
__cosf(x) For x in [-t, t], the maximum absolute error
is 2
-21.19
, and larger otherwise.
__sincosf(x,sptr,cptr) Same as sinf(x) and cosf(x).
__tanf(x) Derived from its implementation as
__sinf(x) * (1 / __cosf(x)).
__powf(x, y) Derived from its implementation as
exp2f(y * __log2f(x)).
__saturate(x) N/A
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136 CUDA C Programming Guide Version 3.2

C.2.2 Double-Precision Floating-Point Functions
__dadd_rn() and __dmul_rn() map to addition and multiplication operations
that the compiler never merges into FMADs. By contrast, additions and
multiplications generated from the '*' and '+' operators will frequently be combined
into FMADs.
Table C-4. Double-Precision Floating-Point Intrinsic
Functions Supported by the CUDA Runtime
Library with Respective Error Bounds
Function Error bounds
__dadd_[rn,rz,ru,rd](x,y) IEEE-compliant.
__dmul_[rn,rz,ru,rd](x,y) IEEE-compliant.
__fma_[rn,rz,ru,rd](x,y,z) IEEE-compliant.
__ddiv_[rn,rz,ru,rd](x,y)(x,y) IEEE-compliant.
Requires compute capability ≥ 2.
__drcp_[rn,rz,ru,rd](x) IEEE-compliant.
Requires compute capability ≥ 2
__dsqrt_[rn,rz,ru,rd](x) IEEE-compliant.
Requires compute capability ≥ 2
C.2.3 Integer Functions
__[u]mul24(x,y) computes the product of the 24 least significant bits of the
integer parameters x and y and delivers the 32 least significant bits of the result. The
8 most significant bits of x or y are ignored.
__[u]mulhi(x,y) computes the product of the integer parameters x and y and
delivers the 32 most significant bits of the 64-bit result.
__[u]mul64hi(x,y) computes the product of the 64-bit integer parameters x
and y and delivers the 64 most significant bits of the 128-bit result.
__[u]sad(x,y,z) (Sum of Absolute Difference) returns the sum of integer
parameter z and the absolute value of the difference between integer parameters x
and y.
__clz(x) returns the number, between 0 and 32 inclusive, of consecutive zero bits
starting at the most significant bit (i.e. bit 31) of integer parameter x.
__clzll(x) returns the number, between 0 and 64 inclusive, of consecutive zero
bits starting at the most significant bit (i.e. bit 63) of 64-bit integer parameter x.
__ffs(x) returns the position of the first (least significant) bit set in integer
parameter x. The least significant bit is position 1. If x is 0, __ffs() returns 0.
Note that this is identical to the Linux function ffs.
__ffsll(x) returns the position of the first (least significant) bit set in 64-bit
integer parameter x. The least significant bit is position 1. If x is 0, __ffsll()
returns 0. Note that this is identical to the Linux function ffsll.
Appendix C. Mathematical Functions


CUDA C Programming Guide Version 3.2 137

__popc(x) returns the number of bits that are set to 1 in the binary representation
of 32-bit integer parameter x.
__popcll(x) returns the number of bits that are set to 1 in the binary
representation of 64-bit integer parameter x.
__brev(x) reverses the bits of 32-bit unsigned integer parameter x, i.e. bit N of
the result corresponds to bit 31-N of x.
__brevll(x) reverses the bits of 64-bit unsigned long long parameter x, i.e. bit N
of the result corresponds to bit 63-N of x.
__byte_perm(x,y,s) returns, as a 32-bit integer r, four bytes from eight input
bytes provided in the two input integers x and y. The input bytes are indexed as
follows:
input[0] = x<0:7> input[1] = x<8:15>
input[2] = x<16:23> input[3] = x<24:31>
input[4] = y<0:7> input[5] = y<8:15>
input[6] = y<16:23> input[7] = y<24:31>
The selector indices are stored in 4-bit nibbles (with the upper 16-bit of the selector
not being used):
selector[0] = s<0:3> selector[1] = s<4:7>
selector[2] = s<8:11> selector[3] = s<12:15>
The returned value r is computed to be:
result[n] := input[selector[n]]
where result[n] is the n
th
byte of r.
C.2.4 Type Casting Functions
There are two categories of type casting functions: the type conversion functions
(Table C-5) and the type reinterpretation functions (Table C-6).
A type reinterpretation function does not change the binary representation of its
input value. For example, __int_as_float(0xC0000000) is equal to -2.0f,
__float_as_int(1.0f) is equal to 0x3f800000.
A type conversion function may change the binary representation of its input value.
For example, __int2float_rn(0xC0000000) is equal to -1073741824.0f,
__float2int_rn(1.0f) is equal to 1.
Table C-5. Type Conversion Functions
__float2int_[rn,rz,ru,rd](x)
__float2uint_[rn,rz,ru,rd](x)
__int2float_[rn,rz,ru,rd](x)
__uint2float_[rn,rz,ru,rd](x)
__float2ll_[rn,rz,ru,rd](x)
__float2ull_[rn,rz,ru,rd](x)
Appendix C. Mathematical Functions


138 CUDA C Programming Guide Version 3.2

__ll2float_[rn,rz,ru,rd](x)
__ull2float_[rn,rz,ru,rd](x)
__float2half_rn(x)
__half2float(x)
__double2float_[rn,rz,ru,rd](x)
__double2int_[rn,rz,ru,rd](x)
__double2uint_[rn,rz,ru,rd](x)
__double2ll_[rn,rz,ru,rd](x)
__double2ull_[rn,rz,ru,rd](x)
__int2double_rn(x)
__uint2double_rn(x)
__ll2double_[rn,rz,ru,rd](x)
__ull2double_[rn,rz,ru,rd](x)
Table C-6. Type Reinterpretation Functions
__int_as_float(x)
__float_as_int(x)
__double_as_longlong(x)
__longlong_as_double(x)
__double2hiint(x)
__double2loint(x)
__hiloint2double(hi, lo)








CUDA C Programming Guide Version 3.1 139

Appendix D.
C++ Language Constructs
CUDA supports the following C++ language constructs for device code:
 Polymorphism
 Default Parameters
 Operator Overloading
 Namespaces
 Function Templates
 Classes for devices of compute capability 2.x
These C++ constructs are implemented as specified in “The C++ Programming
Langue” reference. It is valid to use any of these constructs in .cu CUDA files for
host, device, and kernel (__global__) functions. Any restrictions detailed in previous
parts of this programming guide, like the lack of support for recursion, still apply.
The following subsections provide examples of the various constructs.
D.1 Polymorphism
Generally, polymorphism is the ability to define that functions or operators behave
differently in different contexts. This is also referred to as function (and operator,
see below) overloading.
In practical terms, this means that it is permissible to define two different functions
within the same scope (namespace) as long as they have a distinguishable function
signature. That means that the two functions either consume a different number of
parameters or parameters of different types. When either of the multiple functions
gets invoked the compiler resolves to the function‟s implementation that matches
the function signature.
Because of implicit typecasting, a compiler may encounter multiple potential
matches for a function invocation and in that case the matching rules as described in
the C++ Language Standard apply. In practice this means that the compiler will pick
the closest match in case of multiple potential matches.
Example: The following is valid CUDA code:
__device__ void f(float x)
{
Appendix D. C++ Language Constructs


140 CUDA C Programming Guide Version 3.2

// do something with x
}

__device__ void f(int i)
{
// do something with i
}

__device__ void f(double x, double y)
{
// do something with x and y
}
D.2 Default Parameters
With support for polymorphism as described in the previous subsection and the
function signature matching rules in place it becomes possible to provide support
for default values for function parameters.
Example:
__device__ void f(float x = 0.0f)
{
// do something with x
}
Kernel or other device functions can now invoke this version of f in one of two
ways:
f();
// or
float x = /* some value */;
f(x);

Default parameters can only be given for the last n parameters of a function.
D.3 Operator Overloading
Operator overloading allows programmers to define operators for new data-types.
Examples of overloadable operators in C++ are: +, -, *, /, +=, &, [], etc.
Example: The following is valid CUDA code, implementing the + operation
between two uchar4 vectors:
__device__ uchar4 operator+ (const uchar4 & a, const uchar4 & b)
{
uchar4 r;
r.x = a.x + b.x;
...
return r;
}
This new operator can now be used like this:
uchar4 a, b, c;
a = b = /* some initial value */;
Appendix D. C++ Language Constructs


CUDA C Programming Guide Version 3.2 141

c = a + b;
D.4 Namespaces
Namespaces in C++ allow for the creation of a hierarchy of scopes of visibility. All
the symbols inside a namespace can be used within this namespaces without
additional syntax.
The use of namespaces can be used to solve the problem of name-clashes (two
different symbols using identical names), which commonly occurs when using
multiple function libraries from different sources.
Example: The following code defines two functions “f()” in two separate
namespaces (“nvidia” and “other”):
namespace nvidia {
__device__ void f(float x)
{ /* do something with x */ ;}
}

namespace other {
__device__ void f(float x)
{ /* do something with x */ ;}
}

The functions can now be used anywhere via fully qualified names:
nvidia::f(0.5f);
All the symbols in a namespace can be imported into another namespace (scope)
like this:
using namespace nvidia;
f(0.5f);
D.5 Function Templates
Function templates are a form of meta-programming that allows writing a generic
function in a data-type independent fashion. CUDA supports function templates to
the full extent of the C++ standard, including the following concepts:
 Implicit template parameter deduction.
 Explicit instantiation.
 Template specialization.
Example:
template <T>
__device__ bool f(T x)
{ return /* some clever code that turns x into a bool here */ }
This function will convert x of any data-type to a bool as long as the code in the
function‟s body can be compiled for the actually type (T) of the variable x.
f() can be invoked in two ways:
int x = 1;
Appendix D. C++ Language Constructs


142 CUDA C Programming Guide Version 3.2

bool result = f(x);
This first type of invocation relies on the compiler‟s ability to implicitly deduce the
correct function type for T. In this case the compiler would deduce T to be int and
instantiate f<int>(x).
The second type of invoking the template function is via explicit instantiation like
this:
bool result = f<double>(0.5);

Function templates may be specialized:
template <T>
__device__ bool f(T x)
{ return false; }

template <>
__device__ bool
f<int>(T x)
{ return true; }

In this case the implementation for T representing the int type are specialized to
return true, all other types will be caught by the more general template and return
false.
The complete set of matching rules (for implicitly deducing template parameters)
and matching polymorphous functions apply as specified in the C++ standard.
D.6 Classes
Code compiled for devices with compute capability 2.x and higher may make use of
C++ classes, as long as none of the member functions are virtual (this restriction
will be removed in some future release).
There are two common use cases for classes without virtual member functions:
 Small-data aggregations. E.g. data types like pixels (r, g, b, a), 2D and 3D points,
vectors, etc.
 Functor classes. The use of functors is necessitated by the fact that device-
function pointers are not supported and thus it is not possible to pass functions
as template parameters. A workaround for this restriction is the use of functor
classes (see code sample below).
D.6.1 Example 1 Pixel Data Type
The following is an example of a data type for RGBA pixels with 8 bit per channel
depth:
class PixelRGBA
{
public:
__device__
PixelRGBA(): r_(0), g_(0), b_(0), a_(0)
{ ; }
Appendix D. C++ Language Constructs


CUDA C Programming Guide Version 3.2 143


__device__
PixelRGBA(unsigned char r, unsigned char g, unsigned char b,
unsigned char a = 255): r_(r), g_(g), b_(b), a_(a)
{ ; }

// other methods and operators left out for sake of brevity

private:
unsigned char r_, g_, b_, a_;

friend PixelRGBA operator+(const PixelRGBA &,
const PixelRGBA &);
};

__device__
PixelRGBA operator+(const PixelRGBA & p1, const PixelRGBA & p2)
{
return PixelRGBA(p1.r_ + p2.r_,
p1.g_ + p2.g_,
p1.b_ + p2.b_,
p1.a_ + p2.a_);
}

Other device code can now make use of this new data type as one would expect:
PixelRGBA p1, p2;

// [...] initialization of p1 and p2 here

PixelRGBA p3 = p1 + p2;
D.6.2 Example 2 Functor Class
The following example shows how functors may be used as function template
parameters to implement a set of vector arithmetic operations.
Here are two functors for float addition and subtraction:
class Add
{
public:
__device__
float
operator() (float a, float b)
const
{
return a + b;
}
};

class Sub
{
public:
__device__
float
Appendix D. C++ Language Constructs


144 CUDA C Programming Guide Version 3.2

operator() (float a, float b)
const
{
return a - b;
}
};
The following templatized kernel makes use of the functors like the ones above in
order to implement operations on vectors of floats:
// Device code
template<class O>
__global__
void
VectorOperation(const float * A, const float * B,
float * C, unsigned int N, O op)
{
unsigned int iElement = blockDim.x * blockIdx.x + threadIdx.x;
if (iElement < N)
{
C[iElement] = op(A[iElement], B[iElement]);
}
}
The VectorOperation kernel may now be launched like this in order to get a
vector addition:
// Host code
VectorOperation<<<blocks, threads>>>(v1, v2, v3, N, Add());







CUDA C Programming Guide Version 3.1 145

Appendix E.
NVCC Specifics
E.1 __noinline__ and __forceinline__
When compiling code for devices of compute capability 1.x, a __device__
function is always inlined by default. When compiling code for devices of compute
capability 2.x, a __device__ function is only inlined when deemed appropriate by
the compiler.
The __noinline__ function qualifier can be used as a hint for the compiler not to
inline the function if possible. The function body must still be in the same file where
it is called. For devices of compute capability 1.x, the compiler will not honor the
__noinline__ qualifier for functions with pointer parameters and for functions
with large parameter lists. For devices of compute capability 2.x, the compiler will
always honor the __noinline__ qualifier.
The __forceinline__ function qualifier can be used to force the compiler to
inline the function.
E.2 #pragma unroll
By default, the compiler unrolls small loops with a known trip count. The #pragma
unroll directive however can be used to control unrolling of any given loop. It
must be placed immediately before the loop and only applies to that loop. It is
optionally followed by a number that specifies how many times the loop must be
unrolled.
For example, in this code sample:
#pragma unroll 5
for (int i = 0; i < n; ++i)
the loop will be unrolled 5 times. The compiler will also insert code to ensure
correctness (in the example above, to ensure that there will only be n iterations if n
is less than 5, for example). It is up to the programmer to make sure that the
specified unroll number gives the best performance.
#pragma unroll 1 will prevent the compiler from ever unrolling a loop.
Appendix E. NVCC Specifics


146 CUDA C Programming Guide Version 3.2

If no number is specified after #pragma unroll, the loop is completely unrolled
if its trip count is constant, otherwise it is not unrolled at all.
E.3 __restrict__
nvcc supports restricted pointers via the __restrict__ keyword.
Restricted pointers were introduced in C99 to alleviate the aliasing problem that
exists in C-type languages, and which inhibits all kind of optimization from code re-
ordering to common sub-expression elimination.
Here is an example subject to the aliasing issue, where use of restricted pointer can
help the compiler to reduce the number of instructions:
void foo(const float* a,
const float* b,
float* c)
{
c[0] = a[0] * b[0];
c[1] = a[0] * b[0];
c[2] = a[0] * b[0] * a[1];
c[3] = a[0] * a[1];
c[4] = a[0] * b[0];
c[5] = b[0];
...
}
In C-type languages, the pointers a, b, and c may be aliased, so any write through c
could modify elements of a or b. This means that to guarantee functional
correctness, the compiler cannot load a[0] and b[0] into registers, multiply them,
and store the result to both c[0] and c[1], because the results would differ from
the abstract execution model if, say, a[0] is really the same location as c[0]. So
the compiler cannot take advantage of the common sub-expression. Likewise,
the compiler cannot just reorder the computation of c[4] into the proximity of the
computation of c[0] and c[1] because the preceding write to c[3] could change
the inputs to the computation of c[4].
By making a, b, and c restricted pointers, the programmer asserts to the compiler
that the pointers are in fact not aliased, which in this case means writes through c
would never overwrite elements of a or b. This changes the function prototype as
follows:
void foo(const float* __restrict__ a,
const float* __restrict__ b,
float* __restrict__ c);
Note that all pointer arguments need to be made restricted for the compiler
optimizer to derive any benefit. With the __restrict keywords added, the
compiler can now reorder and do common sub-expression elimination at will, while
retaining functionality identical with the abstract execution model:
void foo(const float* __restrict__ a,
const float* __restrict__ b,
float* __restrict__ c)
{
float t0 = a[0];
Appendix E. NVCC Specifics


CUDA C Programming Guide Version 3.2 147

float t1 = b[0];
float t2 = t0 * t2;
float t3 = a[1];
c[0] = t2;
c[1] = t2;
c[4] = t2;
c[2] = t2 * t3;
c[3] = t0 * t3;
c[5] = t1;
...
}
The effects here are a reduced number of memory accesses and reduced number of
computations. This is balanced by an increase in register pressure due to "cached"
loads and common sub-expressions.
Since register pressure is a critical issue in many CUDA codes, use of restricted
pointers can have negative performance impact on CUDA code, due to reduced
occupancy.








CUDA C Programming Guide Version 3.1 149

Appendix F.
Texture Fetching
This appendix gives the formula used to compute the value returned by the texture
functions of Section B.8 depending on the various attributes of the texture reference
(see Section 3.2.4).
The texture bound to the texture reference is represented as an array T of N texels
for a one-dimensional texture, M N× texels for a two-dimensional texture, or
L M N × × texels for a three-dimensional texture. It is fetched using texture
coordinates x , y , and z .
A texture coordinate must fall within T ‟s valid addressing range before it can be
used to address T . The addressing mode specifies how an out-of-range texture
coordinate x is remapped to the valid range. If x is non-normalized, only the clamp
addressing mode is supported and x is replaced by 0 if 0 < x and 1 ÷ N if x N s . If
x is normalized:
 In clamp addressing mode, x is replaced by 0 if 0 < x and
N
1
1÷ if x s 1 ,
 In wrap addressing mode, x is replaced by ) (x frac , where
) ( ) ( x floor x x frac ÷ = and ) (x floor is the largest integer not greater than x .
In the remaining of the appendix, x , , and z are the non-normalized texture
coordinates remapped to ‟s valid addressing range. , , and z are derived from
the normalized texture coordinates xˆ , yˆ , and zˆ as such: x N x ˆ = , y M y ˆ = , and
z L z ˆ = .
y
T x y
Appendix F. Texture Fetching


150 CUDA C Programming Guide Version 3.2

F.1 Nearest-Point Sampling
In this filtering mode, the value returned by the texture fetch is
 ] [ ) ( i T x tex = for a one-dimensional texture,
 ] , [ ) , ( j i T y x tex = for a two-dimensional texture,
 ] , , [ ) , , ( k j i T z y x tex = for a three-dimensional texture,
where ) (x floor i = , ) (y floor j = , and ) (z floor k = .
Figure D-1 illustrates nearest-point sampling for a one-dimensional texture with
4 = N .
For integer textures, the value returned by the texture fetch can be optionally
remapped to [0.0, 1.0] (see Section 3.2.4.1.1).


Figure F-1. Nearest-Point Sampling of a One-Dimensional
Texture of Four Texels
F.2 Linear Filtering
In this filtering mode, which is only available for floating-point textures, the value
returned by the texture fetch is
 ] 1 [ ] [ ) 1 ( ) ( + + ÷ = i T i T x tex o o for a one-dimensional texture,
0 4 1 2 3
T[0]
T[1]
T[2]
T[3]
x
0 1 0.25 0.5 0.75
Non-Normalized
Normalized
tex(x)
Appendix F. Texture Fetching


CUDA C Programming Guide Version 3.2 151

 ] 1 , 1 [ ] 1 , [ ) 1 ( ] , 1 [ ) 1 ( ] , [ ) 1 )( 1 ( ) , ( + + + + ÷ + + ÷ + ÷ ÷ = j i T j i T j i T j i T y x tex o| | o | o | o
for a two-dimensional texture,
 = ) , , ( z y x tex

] 1 , 1 , 1 [ ] 1 , 1 , [ ) 1 (
] 1 , , 1 [ ) 1 ( ] 1 , , [ ) 1 )( 1 (
] , 1 , 1 [ ) 1 ( ] , 1 , [ ) 1 ( ) 1 (
] , , 1 [ ) 1 )( 1 ( ] , , [ ) 1 )( 1 )( 1 (
+ + + + + + ÷
+ + + ÷ + + ÷ ÷
+ + + ÷ + + ÷ ÷
+ + ÷ ÷ + ÷ ÷ ÷
k j i T k j i T
k j i T k j i T
k j i T k j i T
k j i T k j i T
o|¸ |¸ o
¸ | o ¸ | o
¸ o| ¸ | o
¸ | o ¸ | o

for a three-dimensional texture,
where:
 ) (
B
x floor i = , ) (
B
x frac = o , 5 . 0 ÷ = x x
B
,
 ) (
B
y floor j = , ) (
B
y frac = | , 5 . 0 ÷ = y y
B
,
 ) (
B
z floor k = , ) (
B
z frac = ¸ , 5 . 0 ÷ = z z
B
.
o , | , and ¸ are stored in 9-bit fixed point format with 8 bits of fractional value
(so 1.0 is exactly represented).
Figure F-2 illustrates nearest-point sampling for a one-dimensional texture with
4 = N .

Figure F-2. Linear Filtering of a One-Dimensional Texture of
Four Texels in Clamp Addressing Mode
0 4 1 2 3
T[0]
T[1]
T[2]
T[3]
tex(x)
x
0 1 0.25 0.5 0.75
Non-Normalized
Normalized
Appendix F. Texture Fetching


152 CUDA C Programming Guide Version 3.2

F.3 Table Lookup
A table lookup ) (x TL where x spans the interval ] , 0 [ R can be implemented as
) 5 . 0
1
( ) ( +
÷
= x
R
N
tex x TL in order to ensure that ] 0 [ ) 0 ( T TL = and ] 1 [ ) ( ÷ = N T R TL .
Figure F-3 illustrates the use of texture filtering to implement a table lookup with
4 = R or 1 = R from a one-dimensional texture with .


Figure F-3. One-Dimensional Table Lookup Using Linear
Filtering

4 = N
0 4 4/3 8/3
T[0]
T[1]
T[2]
T[3]
TL(x)
x
0 1 1/3 2/3






CUDA C Programming Guide Version 3.1 153

Appendix G.
Compute Capabilities
The general specifications and features of a compute device depend on its compute
capability (see Section 2.5).
Section G.1 gives the features and technical specifications associated to each
compute capability.
Section G.2 reviews the compliance with the IEEE floating-point standard.
Section G.3 and 0 give more details on the architecture of devices of compute
capability 1.x and 2.x, respectively.

Appendix G. Compute Capabilities


154 CUDA C Programming Guide Version 3.2

G.1 Features and Technical Specifications
Compute Capability
Feature Support
(Unlisted features are supported
for all compute capabilities)
1.0 1.1 1.2 1.3 2.x
Integer atomic functions operating on
32-bit words in global memory
(Section B.11)
No yes
Integer atomic functions operating on
64-bit words in global memory
(Section B.11)
No Yes Integer atomic functions operating on
32-bit words in shared memory
(Section B.11)
Warp vote functions (Section B.12)
Double-precision floating-point
numbers
No Yes
Floating-point atomic addition
operating on 32-bit words in global
and shared memory (Section B.11)
No Yes
__ballot() (Section B.12)
__threadfence_system() (Section B.5)
__syncthreads_count(),
__syncthreads_and(),
__syncthreads_or() (Section B.6)
Surface functions (Section B.9)


Compute Capability
Technical Specifications 1.0 1.1 1.2 1.3 2.x
Maximum x- or y-dimension of a grid
of thread blocks
65535
Maximum number of threads per
block
512 1024
Maximum x- or y-dimension of a
block
512 1024
Maximum z-dimension of a block 64
Warp size 32
Maximum number of resident blocks
per multiprocessor
8
Maximum number of resident warps
per multiprocessor
24 32 48
Maximum number of resident threads
per multiprocessor
768 1024 1536
Number of 32-bit registers per
multiprocessor
8 K 16 K 32 K
Maximum amount of shared memory 16 KB 48 KB
Appendix G. Compute Capabilities


CUDA C Programming Guide Version 3.2 155

Compute Capability
Technical Specifications 1.0 1.1 1.2 1.3 2.x
per multiprocessor
Number of shared memory banks 16 32
Amount of local memory per thread 16 KB 512 KB
Constant memory size 64 KB
Cache working set per multiprocessor
for constant memory
8 KB
Cache working set per multiprocessor
for texture memory
Device dependent, between 6 KB and 8 KB
Maximum width for a 1D texture
reference bound to a CUDA array
8192 32768
Maximum width for a 1D texture
reference bound to linear memory
2
27

Maximum width and height for a 2D
texture reference bound to linear
memory or to a CUDA array
65536 x 32768
65536 x
65535
Maximum width, height, and depth
for a 3D texture reference bound to
linear memory or a CUDA array
2048 x 2048 x 2048
Maximum number of textures that
can be bound to a kernel
128
Maximum width for a 1D surface
reference bound to a CUDA array
N/A
8192
Maximum width and height for a 2D
surface reference bound to a CUDA
array
8192 x
8192
Maximum number of surfaces that
can be bound to a kernel
8
Maximum number of instructions per
kernel
2 million

G.2 Floating-Point Standard
All compute devices follow the IEEE 754-2008 standard for binary floating-point
arithmetic with the following deviations:
 There is no dynamically configurable rounding mode; however, most of the
operations support multiple IEEE rounding modes, exposed via device
intrinsics;
 There is no mechanism for detecting that a floating-point exception has
occurred and all operations behave as if the IEEE-754 exceptions are always
masked, and deliver the masked response as defined by IEEE-754 if there is an
exceptional event; for the same reason, while SNaN encodings are supported,
they are not signaling and are handled as quiet;
 The result of a single-precision floating-point operation involving one or more
input NaNs is the quiet NaN of bit pattern 0x7fffffff;
Appendix G. Compute Capabilities


156 CUDA C Programming Guide Version 3.2

 Double-precision floating-point absolute value and negation are not compliant
with IEEE-754 with respect to NaNs; these are passed through unchanged;
 For single-precision floating-point numbers on devices of compute
capability 1.x:
 Denormalized numbers are not supported; floating-point arithmetic and
comparison instructions convert denormalized operands to zero prior to
the floating-point operation;
 Underflowed results are flushed to zero;
 Some instructions are not IEEE-compliant:
 Addition and multiplication are often combined into a single multiply-
add instruction (FMAD), which truncates (i.e. without rounding) the
intermediate mantissa of the multiplication;
 Division is implemented via the reciprocal in a non-standard-compliant
way;
 Square root is implemented via the reciprocal square root in a non-
standard-compliant way;
 For addition and multiplication, only round-to-nearest-even and
round-towards-zero are supported via static rounding modes; directed
rounding towards +/- infinity is not supported;
To mitigate the impact of these restrictions, IEEE-compliant software (and
therefore slower) implementations are provided through the following
intrinsics (c.f. Section C.2.1):
 __fmaf_r{n,z,u,d}(float, float, float): single-precision
fused multiply-add with IEEE rounding modes,
 __frcp_r[n,z,u,d](float): single-precision reciprocal with
IEEE rounding modes,
 __fdiv_r[n,z,u,d](float, float): single-precision division
with IEEE rounding modes,
 __fsqrt_r[n,z,u,d](float): single-precision square root with
IEEE rounding modes,
 __fadd_r[u,d](float, float): single-precision addition with
IEEE directed rounding,
 __fmul_r[u,d](float, float): single-precision multiplication
with IEEE directed rounding;
 For double-precision floating-point numbers on devices of compute
capability 1.x:
 Round-to-nearest-even is the only supported IEEE rounding mode for
reciprocal, division, and square root.
When compiling for devices without native double-precision floating-point support,
i.e. devices of compute capability 1.2 and lower, each double variable is converted
to single-precision floating-point format (but retains its size of 64 bits) and double-
precision floating-point arithmetic gets demoted to single-precision floating-point
arithmetic.
For devices of compute capability 2.x, code must be compiled with -ftz=false,
-prec-div=true, and -prec-sqrt=true to ensure IEEE compliance (this is
the default setting; see the nvcc user manual for description of these compilation
flags); code compiled with -ftz=true, -prec-div=false, and
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CUDA C Programming Guide Version 3.2 157

-prec-sqrt=false comes closest to the code generated for devices of compute
capability 1.x.
Addition and multiplication are often combined into a single multiply-add
instruction:
 FMAD for single precision on devices of compute capability 1.x,
 FFMA for single precision on devices of compute capability 2.x.
As mentioned above, FMAD truncates the mantissa prior to use it in the addition.
FFMA, on the other hand, is an IEEE-754(2008) compliant fused multiply-add
instruction, so the full-width product is being used in the addition and a single
rounding occurs during generation of the final result. While FFMA in general has
superior numerical properties compared to FMAD, the switch from FMAD to
FFMA can cause slight changes in numeric results and can in rare circumstances
lead to slighty larger error in final results.
In accordance to the IEEE-754R standard, if one of the input parameters to
fminf(), fmin(), fmaxf(), or fmax() is NaN, but not the other, the result is
the non-NaN parameter.
The conversion of a floating-point value to an integer value in the case where the
floating-point value falls outside the range of the integer format is left undefined by
IEEE-754. For compute devices, the behavior is to clamp to the end of the
supported range. This is unlike the x86 architecture behavior.
G.3 Compute Capability 1.x
G.3.1 Architecture
For devices of compute capability 1.x, a multiprocessor consists of:
 8 CUDA cores for integer and single-precision floating-point arithmetic
operations,
 1 double-precision floating-point unit for double-precision floating-point
arithmetic operations,
 2 special function units for single-precision floating-point transcendental
functions (these units can also handle single-precision floating-point
multiplications),
 1 warp scheduler.
To execute an instruction for all threads of a warp, the warp scheduler must
therefore issue the instruction over:
 4 clock cycles for an integer or single-precision floating-point arithmetic
instruction,
 32 clock cycles for a double-precision floating-point arithmetic instruction,
 16 clock cycles for a single-precision floating-point transcendental instruction.
A multiprocessor also has a read-only constant cache that is shared by all functional
units and speeds up reads from the constant memory space, which resides in device
memory.
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158 CUDA C Programming Guide Version 3.2

Multiprocessors are grouped into Texture Processor Clusters (TPCs). The number of
multiprocessors per TPC is:
 2 for devices of compute capabilities 1.0 and 1.1,
 3 for devices of compute capabilities 1.2 and 1.3.
Each TPC has a read-only texture cache that is shared by all multiprocessors and
speeds up reads from the texture memory space, which resides in device memory.
Each multiprocessor accesses the texture cache via a texture unit that implements
the various addressing modes and data filtering mentioned in Section 3.2.4.
The local and global memory spaces reside in device memory and are not cached.
G.3.2 Global Memory
A global memory request for a warp is split into two memory requests, one for each
half-warp, that are issued independently. Sections G.3.2.1 and G.3.2.2 describe how
the memory accesses of threads within a half-warp are coalesced into one or more
memory transactions depending on the compute capability of the device. Figure G-1
shows some examples of global memory accesses and corresponding memory
transactions based on compute capability.
The resulting memory transactions are serviced at the throughput of device
memory.
G.3.2.1 Devices of Compute Capability 1.0 and 1.1
To coalesce, the memory request for a half-warp must satisfy the following
conditions:
 The size of the words accessed by the threads must be 4, 8, or 16 bytes;
 If this size is:
 4, all 16 words must lie in the same 64-byte segment,
 8, all 16 words must lie in the same 128-byte segment,
 16, the first 8 words must lie in the same 128-byte segment and the last 8
words in the following 128-byte segment;
 Threads must access the words in sequence: The k
th
thread in the half-warp
must access the k
th
word.
If the half-warp meets these requirements, a 64-byte memory transaction, a 128-byte
memory transaction, or two 128-byte memory transactions are issued if the size of
the words accessed by the threads is 4, 8, or 16, respectively. Coalescing is achieved
even if the warp is divergent, i.e. there are some inactive threads that do not actually
access memory.
If the half-warp does not meet these requirements, 16 separate 32-byte memory
transactions are issued.
G.3.2.2 Devices of Compute Capability 1.2 and 1.3
Threads can access any words in any order, including the same words, and a single
memory transaction for each segment addressed by the half-warp is issued. This is
in contrast with devices of compute capabilities 1.0 and 1.1 where threads need to
access words in sequence and coalescing only happens if the half-warp addresses a
single segment.
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CUDA C Programming Guide Version 3.2 159

More precisely, the following protocol is used to determine the memory transactions
necessary to service all threads in a half-warp:
 Find the memory segment that contains the address requested by the lowest
numbered active thread. The segment size depends on the size of the words
accessed by the threads:
 32 bytes for 1-byte words,
 64 bytes for 2-byte words,
 128 bytes for 4-, 8- and 16-byte words.
 Find all other active threads whose requested address lies in the same segment.
 Reduce the transaction size, if possible:
 If the transaction size is 128 bytes and only the lower or upper half is used,
reduce the transaction size to 64 bytes;
 If the transaction size is 64 bytes (originally or after reduction from 128
bytes) and only the lower or upper half is used, reduce the transaction size
to 32 bytes.
 Carry out the transaction and mark the serviced threads as inactive.
 Repeat until all threads in the half-warp are serviced.
G.3.3 Shared Memory
Shared memory has 16 banks that are organized such that successive 32-bit words
are assigned to successive banks, i.e. interleaved. Each bank has a bandwidth of 32
bits per two clock cycles.
A shared memory request for a warp is split into two memory requests, one for each
half-warp, that are issued independently. As a consequence, there can be no bank
conflict between a thread belonging to the first half of a warp and a thread
belonging to the second half of the same warp.
If a non-atomic instruction executed by a warp writes to the same location in shared
memory for more than one of the threads of the warp, only one thread per half-
warp performs a write and which thread performs the final write is undefined.
G.3.3.1 32-Bit Strided Access
A common access pattern is for each thread to access a 32-bit word from an array
indexed by the thread ID tid and with some stride s:
__shared__ float shared[32];
float data = shared[BaseIndex + s * tid];
In this case, threads tid and tid+n access the same bank whenever s*n is a
multiple of the number of banks (i.e. 16) or, equivalently, whenever n is a multiple
of 16/d where d is the greatest common divisor of 16 and s. As a consequence,
there will be no bank conflict only if half the warp size (i.e. 16) is less than or equal
to 16/d., that is only if d is equal to 1, i.e. s is odd.
Figure G-2 shows some examples of strided access for devices of compute
capability 2.x. The same examples apply for devices of compute capability 1.x, but
with 16 banks instead of 32.
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160 CUDA C Programming Guide Version 3.2

G.3.3.2 32-Bit Broadcast Access
Shared memory features a broadcast mechanism whereby a 32-bit word can be read
and broadcast to several threads simultaneously when servicing one memory read
request. This reduces the number of bank conflicts when several threads read from
an address within the same 32-bit word. More precisely, a memory read request
made of several addresses is serviced in several steps over time by servicing one
conflict-free subset of these addresses per step until all addresses have been
serviced; at each step, the subset is built from the remaining addresses that have yet
to be serviced using the following procedure:
 Select one of the words pointed to by the remaining addresses as the broadcast
word;
 Include in the subset:
 All addresses that are within the broadcast word,
 One address for each bank (other than the broadcasting bank) pointed to
by the remaining addresses.
Which word is selected as the broadcast word and which address is picked up for
each bank at each cycle are unspecified.
A common conflict-free case is when all threads of a half-warp read from an address
within the same 32-bit word.
Figure G-3 shows some examples of memory read accesses that involve the
broadcast mechanism. The same examples apply for devices of compute capability
1.x, but with 16 banks instead of 32.
G.3.3.3 8-Bit and 16-Bit Access
8-bit and 16-bit accesses typically generate bank conflicts. For example, there are
bank conflicts if an array of char is accessed the following way:
__shared__ char shared[32];
char data = shared[BaseIndex + tid];
because shared[0], shared[1], shared[2], and shared[3], for example,
belong to the same bank. There are no bank conflicts however, if the same array is
accessed the following way:
char data = shared[BaseIndex + 4 * tid];
G.3.3.4 Larger Than 32-Bit Access
Accesses that are larger than 32-bit per thread are split into 32-bit accesses that
typically generate bank conflicts.
For example, there are 2-way bank conflicts for arrays of doubles accessed as
follows:
__shared__ double shared[32];
double data = shared[BaseIndex + tid];
as the memory request is compiled into two separate 32-bit requests with a stride of
two. One way to avoid bank conflicts in this case is two split the double operands
like in the following sample code:
__shared__ int shared_lo[32];
__shared__ int shared_hi[32];

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CUDA C Programming Guide Version 3.2 161

double dataIn;
shared_lo[BaseIndex + tid] = __double2loint(dataIn);
shared_hi[BaseIndex + tid] = __double2hiint(dataIn);

double dataOut =
__hiloint2double(shared_hi[BaseIndex + tid],
shared_lo[BaseIndex + tid]);
This might not always improve performance however and does perform worse on
devices of compute capabilities 2.x.
The same applies to structure assignments. The following code, for example:
__shared__ struct type shared[32];
struct type data = shared[BaseIndex + tid];
results in:
 Three separate reads without bank conflicts if type is defined as
struct type {
float x, y, z;
};
since each member is accessed with an odd stride of three 32-bit words;
 Two separate reads with bank conflicts if type is defined as
struct type {
float x, y;
};
since each member is accessed with an even stride of two 32-bit words.
G.4 Compute Capability 2.x
G.4.1 Architecture
For devices of compute capability 2.x, a multiprocessor consists of:
 For devices of compute capability 2.0:
 32 CUDA cores for integer and floating-point arithmetic operations,
 4 special function units for single-precision floating-point transcendental
functions,
 For devices of compute capability 2.1:
 48 CUDA cores for integer and floating-point arithmetic operations,
 8 special function units for single-precision floating-point transcendental
functions,
 2 warp schedulers.
At every instruction issue time, each scheduler issues:
 One instruction for devices of compute capability 2.0,
 Two instructions for devices of compute capability 2.1,
for some warp that is ready to execute, if any. The first scheduler is in charge of the
warps with an odd ID and the second scheduler is in charge of the warps with an
Appendix G. Compute Capabilities


162 CUDA C Programming Guide Version 3.2

even ID. Note that when a scheduler issues a double-precision floating-point
instruction, the other scheduler cannot issue any instruction.
A warp scheduler can issue an instruction to only half of the CUDA cores. To
execute an instruction for all threads of a warp, a warp scheduler must therefore
issue the instruction over two clock cycles for an integer or floating-point arithmetic
instruction.
A multiprocessor also has a read-only uniform cache that is shared by all functional
units and speeds up reads from the constant memory space, which resides in device
memory.
There is an L1 cache for each multiprocessor and an L2 cache shared by all
multiprocessors, both of which are used to cache accesses to local or global
memory, including temporary register spills. The cache behavior (e.g. whether reads
are cached in both L1 and L2 or in L2 only) can be partially configured on a per-
access basis using modifiers to the load or store instruction.
The same on-chip memory is used for both L1 and shared memory: It can be
configured as 48 KB of shared memory and 16 KB of L1 cache or as 16 KB of
shared memory and 48 KB of L1 cache, using
cudaFuncSetCacheConfig()/cuFuncSetCacheConfig():
// Device code
__global__ void MyKernel()
{
...
}

// Host code

// Runtime API
// cudaFuncCachePreferShared: shared memory is 48 KB
// cudaFuncCachePreferL1: shared memory is 16 KB
// cudaFuncCachePreferNone: no preference
cudaFuncSetCacheConfig(MyKernel, cudaFuncCachePreferShared)

// Driver API
// CU_FUNC_CACHE_PREFER_SHARED: shared memory is 48 KB
// CU_FUNC_CACHE_PREFER_L1: shared memory is 16 KB
// CU_FUNC_CACHE_PREFER_NONE: no preference
CUfunction myKernel;
cuFuncSetCacheConfig(myKernel, CU_FUNC_CACHE_PREFER_SHARED)
The default cache configuration is "prefer none," meaning "no preference." If a
kernel is configured to have no preference, then it will default to the preference of
the current thread/context, which is set using
cudaThreadSetCacheConfig()/cuCtxSetCacheConfig() (see the
reference manual for details). If the current thread/context also has no preference
(which is again the default setting), then whichever cache configuration was most
recently used for any kernel will be the one that is used, unless a different cache
configuration is required to launch the kernel (e.g., due to shared memory
requirements). The initial configuration is 48KB of shared memory and 16KB of L1
cache.
Multiprocessors are grouped into Graphics Processor Clusters (GPCs). A GPC includes
four multiprocessors.
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CUDA C Programming Guide Version 3.2 163

Each multiprocessor has a read-only texture cache to speed up reads from the
texture memory space, which resides in device memory. It accesses the texture cache
via a texture unit that implements the various addressing modes and data filtering
mentioned in Section 3.2.4.
G.4.2 Global Memory
Global memory accesses are cached. Using the –dlcm compilation flag, they can be
configured at compile time to be cached in both L1 and L2 (-Xptxas -dlcm=ca)
(this is the default setting) or in L2 only (-Xptxas -dlcm=cg).
A cache line is 128 bytes and maps to a 128-byte aligned segment in device memory.
Memory accesses that are cached in both L1 and L2 are serviced with 128-byte
memory transactions whereas memory accesses that are cached in L2 only are
serviced with 32-byte memory transactions. Caching in L2 only can therefore reduce
over-fetch, for example, in the case of scattered memory accesses.
If the size of the words accessed by each thread is more than 4 bytes, a memory
request by a warp is first split into separate 128-byte memory requests that are
issued independently:
 Two memory requests, one for each half-warp, if the size is 8 bytes,
 Four memory requests, one for each quarter-warp, if the size is 16 bytes.
Each memory request is then broken down into cache line requests that are issued
independently. A cache line request is serviced at the throughput of L1 or L2 cache
in case of a cache hit, or at the throughput of device memory, otherwise.
Note that threads can access any words in any order, including the same words.
If a non-atomic instruction executed by a warp writes to the same location in global
memory for more than one of the threads of the warp, only one thread performs a
write and which thread does it is undefined.

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164 CUDA C Programming Guide Version 3.2


Figure G-1. Examples of Global Memory Accesses by a Warp,
4-Byte Word per Thread, and Associated Memory
Transactions Based on Compute Capability
128 160 192 256 224 96 288 Addresses:
0 31

Threads:
Compute capability:
Memory transactions:
1.0 and 1.1
8 x 32B at 128
8 x 32B at 160
8 x 32B at 192
8 x 32B at 224
1.2 and 1.3
1 x 64B at 128
1 x 64B at 192


2.0
1 x 128B at 128
Aligned and non-sequential
Uncached Cached
128 160 192 256 224 96 288 Addresses:
0 31

Threads:
Compute capability:
Memory transactions:
1.0 and 1.1
1 x 64B at 128
1 x 64B at 192
1.2 and 1.3
1 x 64B at 128
1 x 64B at 192


2.0
1 x 128B at 128
Aligned and sequential
Uncached Cached
128 160 192 256 224 96 288 Addresses:
0 31

Threads:
Compute capability:
Memory transactions:
1.0 and 1.1
7 x 32B at 128
8 x 32B at 160
8 x 32B at 192
8 x 32B at 224
1 x 32B at 256

1.2 and 1.3
1 x 128B at 128
1 x 64B at 192
1 x 32B at 256


2.0
1 x 128B at 128
1 x 128B at 256
Misaligned and sequential
Uncached Cached
Appendix G. Compute Capabilities


CUDA C Programming Guide Version 3.2 165

G.4.3 Shared Memory
Shared memory has 32 banks that are organized such that successive 32-bit words
are assigned to successive banks, i.e. interleaved. Each bank has a bandwidth of 32
bits per two clock cycles. Therefore, unlike for devices of lower compute capability,
there may be bank conflicts between a thread belonging to the first half of a warp
and a thread belonging to the second half of the same warp.
A bank conflict only occurs if two or more threads access any bytes within different
32-bit words belonging to the same bank. If two or more threads access any bytes
within the same 32-bit word, there is no bank conflict between these threads: For
read accesses, the word is broadcast to the requesting threads (unlike for devices of
compute capability 1.x, multiple words can be broadcast in a single transaction); for
write accesses, each byte is written by only one of the threads (which thread
performs the write is undefined).
This means, in particular, that unlike for devices of compute capability 1.x, there are
no bank conflicts if an array of char is accessed as follows, for example:
__shared__ char shared[32];
char data = shared[BaseIndex + tid];
G.4.3.1 32-Bit Strided Access
A common access pattern is for each thread to access a 32-bit word from an array
indexed by the thread ID tid and with some stride s:
__shared__ float shared[32];
float data = shared[BaseIndex + s * tid];
In this case, threads tid and tid+n access the same bank whenever s*n is a
multiple of the number of banks (i.e. 32) or, equivalently, whenever n is a multiple
of 32/d where d is the greatest common divisor of 32 and s. As a consequence,
there will be no bank conflict only if the warp size (i.e. 32) is less than or equal to
32/d., that is only if d is equal to 1, i.e. s is odd.
Figure G-2 shows some examples of strided access.
G.4.3.2 Larger Than 32-Bit Access
64-bit and 128-bit accesses are specifically handled to minimize bank conflicts as
described below.
Other accesses larger than 32-bit are split into 32-bit, 64-bit, or 128-bit accesses.
The following code, for example:
struct type {
float x, y, z;
};

__shared__ struct type shared[32];
struct type data = shared[BaseIndex + tid];
results in three separate 32-bit reads without bank conflicts since each member is
accessed with a stride of three 32-bit words.
64-Bit Accesses
For 64-bit accesses, a bank conflict only occurs if two or more threads in either of
the half-warps access different addresses belonging to the same bank.
Appendix G. Compute Capabilities


166 CUDA C Programming Guide Version 3.2

Unlike for devices of compute capability 1.x, there are no bank conflicts for arrays
of doubles accessed as follows, for example:
__shared__ double shared[32];
double data = shared[BaseIndex + tid];
128-Bit Accesses
The majority of 128-bit accesses will cause 2-way bank conflicts, even if no two
threads in a quarter-warp access different addresses belonging to the same bank.
Therefore, to determine the ways of bank conflicts, one must add 1 to the
maximum number of threads in a quarter-warp that access different addresses
belonging to the same bank.
G.4.4 Constant Memory
In addition to the constant memory space supported by devices of all compute
capabilities (where __constant__ variables reside), devices of compute
capability 2.x support the LDU (LoaD Uniform) instruction that the compiler use
to load any variable that is:
 pointing to global memory,
 read-only in the kernel (programmer can enforce this using the const
keyword),
 not dependent on thread ID.


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CUDA C Programming Guide Version 3.2 167


Left: Linear addressing with a stride of one 32-bit word (no bank conflict).
Middle: Linear addressing with a stride of two 32-bit words (2-way bank conflicts).
Right: Linear addressing with a stride of three 32-bit words (no bank conflict).
Figure G-2 Examples of Strided Shared Memory Accesses for
Devices of Compute Capability 2.x
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168 CUDA C Programming Guide Version 3.2


Left: Conflict-free access via random permutation.
Middle: Conflict-free access since threads 3, 4, 6, 7, and 9 access the same word within bank 5.
Right: Conflict-free broadcast access (all threads access the same word).
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CUDA C Programming Guide Version 3.2 169

Figure G-3 Examples of Irregular and Colliding Shared
Memory Accesses for Devices of Compute
Capability 2.x

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Queue, VOL 6, No. 2 (March/April 2008), © ACM, 2008. http://mags.acm.org/queue/20080304/?u1=texterity"

Changes from Version 3.1.1

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Simplified all the code samples that use cuParamSetv() to set a kernel parameter of type CUdeviceptr since CUdeviceptr is now of same size and alignment as void*, so there is no longer any need to go through an interneditate void* variable. Added Section 3.2.4.1.4 on 16-bit floating-point textures. Added Section 3.2.4.4 on read/write coherency for texture and surface memory. Added more details about surface memory access to Section 3.2.4.2. Added more details to Section 3.2.6.5. Mentioned new stream synchronization function cudaStreamSynchronize() in Section 3.2.6.5.2. Mentioned in Sections 3.2.7.2, 3.3.10.2, and 4.3 the new API calls to deal with devices using NVIDIA SLI in AFR mode. Added Sections 3.2.9 and 3.3.12 about the call stack. Changed the type of the pitch variable in the second code sample of Section 3.3.4 from unsigned int to size_t following the function signature change of cuMemAllocPitch(). Changed the type of the bytes variable in the last code sample of Section 3.3.4 from unsigned int to size_t following the function signature change of cuModuleGetGlobal(). Removed cuParamSetTexRef() from Section 3.3.7 as it is no longer necessary. Updated Section 5.2.3, Table 5-1, and Section G.4.1 for devices of compute capability 2.1. Added GeForce GTX 480M, GeForce GTX 470M, GeForce GTX 460M, GeForce GTX 445M, GeForce GTX 435M, GeForce GTX 425M, GeForce GTX 420M, GeForce GTX 415M, GeForce GTX 460, GeForce GTS 450, GeForce GTX 465, GeForce GTX 580, Quadro 2000, Quadro 600, Quadro 4000, Quadro 5000, Quadro 5000M, and Quadro 6000 to Table A-1. Fixed sample code in Section B.2.3: array[] was declared as an array of char causing a compiler error (“Unaligned memory accesses not supported”) when casting array to a pointer of higher alignment requirement; declaring array[] as an array of float fixes it. Mentioned in Section B.11 that any atomic operation can be implemented based on atomic Compare And Swap. Added Section B.15 on the new malloc() and free() device functions. Moved the type casting functions to a separate section C.2.4. Fixed the maximum height of a 2D texture reference for devices of compute capability 2.x (65535 instead of 65536) in Section G.1.

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CUDA C Programming Guide Version 3.2

Fixed the maximum dimensions for surface references in Section G.1.  Mentioned the new cudaThreadSetCacheConfig()/cuCtxSetCacheConfig() API calls in Section G.4.1.  Mentioned in Section G.4.2 that global memory accesses that are cached in L2 only are serviced with 32-byte memory transactions.

CUDA C Programming Guide Version 3.2

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.......................................1 1.................................................................................................... 3 A Scalable Programming Model ......... 36 Chapter 2.........2 3............. 28 Texture and Surface Memory ...................... 16 Application Compatibility .........................4..............3 2.........2..4 CUDA C .......................... Introduction .......................1 3......................................................3 3.............................1.................................................5 3......................2 3.................................... 29 Texture Memory ...........................................1 From Graphics Processing to General-Purpose Parallel Computing...................4 2.........................................1 3..........4 2..................... 17 C/C++ Compatibility .......2 3..............................................................4 3........ 10 Heterogeneous Programming .................................. 8 Memory Hierarchy ............ 34 CUDA Arrays ....... Programming Model ...... 18 3....................4.....................................................1 2.........................................................................................................................................................2.................. 36 Read/Write Coherency ...........3 3........................ 15 3.................................6 3........................................................... Programming Interface ....................................................................................Table of Contents Chapter 1................................................1.....................................2 ................ 16 PTX Compatibility ...............................1........................................................................................ 19 Shared Memory ........... 16 Binary Compatibility ......... 18 64-Bit Compatibility ..................... 11 Compute Capability .............. 14 Compilation with NVCC ............ 21 Multiple Devices .................4 iv CUDA C Programming Guide Version 3..2 2........1 3.........................2 1............... 6 Kernels ............................1.....2.................2....... 7 Thread Hierarchy .... 1 CUDA™: a General-Purpose Parallel Computing Architecture ......2..........................4..........................................................2............ 18 Device Memory ..................1..............................3 1.........5 3............. 15 Compilation Workflow................................2 3.................................................4..........2...1.... 4 Document’s Structure .............................. 7 Chapter 3..............................................................................2..................... 29 Surface Memory ................ 1 1.....3 3................................................................

.........7 3.......2.. 66 Stream .........7.... 61 Multiple Devices .........................................................................2 3.. 41 Synchronous Calls ...............................6................................6 3....2 3... 38 Concurrent Data Transfers ................4 3.............. 62 Texture Memory .............................3.......1 3.... 52 Context ..........2.........................3..............3 3.. 39 Stream ......5... 39 Event .....................2....................2............7.....6 3............ 56 Device Memory ...........................................2 3.................................. 37 Mapped Memory.................................... 42 Error Handling ....................................2................................................2......................3.................3........10 Graphics Interoperability............................ 64 Driver API ..............2.........3 3............................................................6............. 37 Write-Combining Memory ..............5 3...... 54 Module ...3.........2 3................... 43 Direct3D Interoperability .....5 Page-Locked Host Memory...................3........................................................ 62 Texture and Surface Memory .............. 67 CUDA C Programming Guide Version 3............................ 37 Concurrent Execution between Host and Device ............. 55 Kernel Execution ................... 67 Synchronous Calls ..2.....3.....5 3...6 3........................................................3.....................6...3........3..................2......................2..9 3... 51 Call Stack ..2.........9......7...1 3.9......................... 38 Concurrent Kernel Execution ..... 42 OpenGL Interoperability .......................................... 45 3................................ 36 Portable Memory .............................................7.......................................................2..........6......................9 Page-Locked Host Memory.................................7 3........................................3 3............................................ 62 Surface Memory ...2 3.............................5..........3......3.2 v ...........................................................3 3..6......................6..1 3...............................................3...........................................2....2.................................................................... 38 Overlap of Data Transfer and Kernel Execution ..........................................8 3...3..................................1 3........................................................................................ 38 Graphics Interoperability......2 3................................................................................1 3.........................................................................................9....7 Asynchronous Concurrent Execution ......2...........2.................................... 67 3..........................................4 3................... 52 3.................3 3.................5......... 65 Asynchronous Concurrent Execution .............1 3............................................3...............3........ 58 Shared Memory ....... 66 Event Management ...8 3.........................................6..................2...........

...... 85 5........................................................................4 3...................................................... 81 Chapter 5.......................3 5........................................ 81 Hardware Multithreading .................2 4.................... 90 Local Memory.2................. 92 Constant Memory ............................2................................2...................4.12 3..................................................3..................... 96 Synchronization Instruction ......................................................10...................6 3........1 3.......3...3..............3................3....3 5..............4 5.... Performance Guidelines .............................2 5..........................10..... CUDA-Enabled GPUs ........................... 82 Multiple Devices .2.....1 5.....2 ....................................3..................4........................................................... 70 Error Handling ......... 89 Global Memory . 85 Application Level .............................................. 77 Versioning and Compatibility.....................................................................................2.............................3............................4 5........... 93 Arithmetic Instructions .........................3....... Hardware Implementation .............................................4...... 99 Appendix B.......................... 88 5..... 91 Shared Memory ...........................................................................................3.................2............................... 83 Overall Performance Optimization Strategies ..2.................. 79 SIMT Architecture .......... 79 Mode Switches .........................................................................................2 Maximize Memory Throughput .1 5...................1 4........................................................................................3 5....1 5.............................................................................................3..............................2 3.........2 OpenGL Interoperability ...........3................................................. 78 Compute Modes ............................. 89 Device Memory Accesses ............. 103 B.......................................................................... 86 Multiprocessor Level ....................2......................................7 4.........................1 Function Type Qualifiers ............ 77 Call Stack ............................... 92 Texture and Surface Memory ...................................3............................................3 Maximize Instruction Throughput ......1 5.... 86 Data Transfer between Host and Device ......5 3.............................................................1 5................5 5.....11 3......................................................... 85 Maximize Utilization .......... 94 Control Flow Instructions ......... 93 Chapter 4......2 5........ 85 Device Level .................... 97 Appendix A............. C Language Extensions .............................. 68 Direct3D Interoperability ......................................................................................................3 5...... 103 vi CUDA C Programming Guide Version 3................................2 5....... 77 Interoperability between Runtime and Driver APIs ...........................

.....4 B.............. 104 Variadic Functions ... ulong4....4 __device__ ............. 109 gridDim ......5 B..................2........................................... short4..4 B. 105 __constant__ ........................2............................ float4................................................................3 B................................................ double2 108 B.6 B...............5 dim3 . short3.... 109 blockDim ...2. uint3...............................2.........................1 B...........2 B.. 107 B... float1..........4... 105 Restrictions ..1 B...........................4... 109 warpSize ..................4.............................2 B............. 109 blockIdx ........... 107 Built-in Vector Types .. uchar2................ char2....................2.............1.1.................................................................... 106 Storage and Scope . int2..............4...... char4.....4......4 B.........2........... 104 Functions Parameters ............4.................4 B........... short2..............................2 B...........................1 char1.......4............................... uint4........1......................................... uchar3.................. long2.....1 B.............. int1..........................................................B................3.................................................... ushort3..... 104 Function Pointers........................................................ int4...... 110 Built-in Variables ..................1.................... ulong1...........4............................................2 B..... char3........1.....................1...................1...........4.........................................3 B.......................................................................................2.......................................3...5 B................. 109 threadIdx ........... ulonglong1.............4.......1................................................................ 106 Pointers ........... double1...................... ushort2......................................... ushort4.2 vii ..2 B............. 103 __global__ .......... longlong2.................5 B....... 104 Recursion ............................ 105 __device__ ...... uchar1................... int3................................................... ulong3.2 B.............1 B....... ushort1................. 108 B............3 B..3 B....... float3................... long4... longlong1................................ uint1................2 B........ uchar4.............2................ 103 __host__ ................... 104 B................................................................ 103 Restrictions ....... short1.. 110 CUDA C Programming Guide Version 3.............. 109 Memory Fence Functions ..............1......... 110 Restrictions ......................... ulong2....3 B.............................................. 105 __shared__ ...............4..................... 106 Automatic Variable .............................................1 B..........................3 volatile .............4...............................4................ ulonglong2.....4 Variable Type Qualifiers .... 106 Assignment ................................................ long3............................................................ uint2...........4....... float2............... long1......................2........4............... 104 Static Variables ........

......... 112 Texture Functions ...................................... 114 tex3D() ...................8....11........................................4 B................................1... 120 Limitations ..................... 117 atomicMin() ............................................................................ 120 Associated Host-Side API .........11....................12 B...... 118 B........................................................11.........................3 B...3 B...... 121 B..........................................11....................................................8.......14... 116 atomicAdd() .......... 118 atomicOr() .................9......................6 B.........11.............................2 B............................................................. 117 atomicDec() ...........................1 B........................11..4 B.............. 119 Format Specifiers .....11......................................11......... 111 Mathematical Functions ............................................................................................................1 B........................11........... 113 tex1Dfetch() ............11................... 117 atomicExch() .............................................................2 B........................1....................................................9.......... 117 atomicMax()..1...13 B........................ 119 Formatted Output .............. 115 Atomic Functions ......................................................... 115 surf2Dwrite() ................................... 115 B..............................2 Bitwise Functions ........... 118 B..................................................................7 B..........1.....8 Synchronization Functions ................................. 116 Arithmetic Functions .....................9.............. 115 surf2Dread() .....3 viii CUDA C Programming Guide Version 3............. 115 surf1Dwrite() ................. 119 Profiler Counter Function ...... 117 atomicInc() ..............................................7 B..................2..1 B......4 B.....1 B................................... 118 atomicXor()............8...............................2 ..................2...........................10 B............14 Warp Vote Functions....14........................................................3 B.......................................................................................................11............ 116 atomicSub() .............................................. 118 atomicAnd() ...... 114 tex2D() ............................................................2 B............................1........8....................B....................1 B................................................8 B...........................9 B..........11.......1..........11 Surface Functions ......................2.................................................................................................. 114 Time Function ........................................... 113 tex1D() ............... 114 surf1Dread() ..............1 B........................14................1...............2 B....................9............................................................................................11...............6 B..............................................................................................1...................5 B..................2 B............3 B.............................................................................. 118 atomicCAS() .......................

......... 123 Interoperability with Host Memory API ................ 146 CUDA C Programming Guide Version 3........... 142 Example 2 Functor Class .........5 D..3 B.........4 B..............1 E............ 129 C............2............................. 137 Appendix C. 143 D........................................................................15 B.. 123 Examples .............................................................. 145 __noinline__ and __forceinline__ ...............................1 D........................ C++ Language Constructs .....................................1 D..15.............................................................4 D.. 136 Type Casting Functions...................15....................................................2 B..................... 134 Double-Precision Floating-Point Functions ..................................1 B.. 145 #pragma unroll ....... 140 Operator Overloading.. 129 Double-Precision Floating-Point Functions ........................1 C............................ 142 Example 1 Pixel Data Type....1...................................................15.....2 C...................... 126 Launch Bounds .......... 123 Per Thread Block Allocation .............................................15....................... 134 Single-Precision Floating-Point Functions ............3 Examples .......17 C.....15...................... 139 Polymorphism ...................................... 140 Namespaces...............1 B..........................................................................................................3 D.................................................................................. 129 Single-Precision Floating-Point Functions ......... 134 Appendix D....6.....................2.2 D....2 E................. 141 Classes .....................6 Intrinsic Functions ...........................2 C................B..............................................................15...................4 D......3 Appendix E. 139 Default Parameters ............................................. 141 Function Templates ...................14...............................2 C....................................................................2..............................................1........................................................................................16 B......................................................................6....1........ 127 Standard Functions ......3 C..... 124 Allocation Persisting Between Kernel Launches ....................................................................................... 122 B......................................3...........2 ix ........................................1 Execution Configuration ...2 B............... 145 __restrict__ ..................... 125 Dynamic Global Memory Allocation ...............................................................................3...............2 E........................................................................1 C........ 136 Integer Functions .............................................. 132 Integer Functions ................. NVCC Specifics ...............................................3.............3 C............ 123 Per Thread Allocation ..................................... 121 Heap Memory Allocation ...................2........................................................................................ Mathematical Functions .........................

....2 G........................4....................... 165 Larger Than 32-Bit Access .............3..3. 157 Global Memory ............................4..........3.....1 G................................1 G...4.....3..........2.................. 161 Architecture ...............................................................................................................................0 and 1............... 160 Larger Than 32-Bit Access ......3 Shared Memory ........3............................................... 165 32-Bit Strided Access ....2 G................................................................3........................ 165 G...............................................x ..2 and 1.......... 158 Devices of Compute Capability 1.............Appendix F................. 150 Table Lookup ............................................................................3 .......1 F............................................................................1 G........................3 G...........2 ..............................................2 F..............3................................3 G.. 155 Compute Capability 1...................................................................................................... 166 x CUDA C Programming Guide Version 3...................... 161 Global Memory .1 G......................3............3....................................... 160 Appendix G............... 153 G.......................... 159 Compute Capability 2............4... 160 8-Bit and 16-Bit Access ...3...........4...3 G............x ...... 149 F.........................2 G.................... Texture Fetching ................. 152 Features and Technical Specifications ......2.................................................................... 158 32-Bit Strided Access .............. Compute Capabilities .............1 G............3 Nearest-Point Sampling ....... 163 Shared Memory ............2 G........3.........2 G...................................... 159 32-Bit Broadcast Access ...4 G................. 150 Linear Filtering ......3..........3..........2 G......... 154 Floating-Point Standard ......................4............................1 .................................. 157 Architecture .1 G....3.........................................4 Constant Memory .......................................................... 158 Devices of Compute Capability 1.......4 G..................................................3.................................

.................................................................x .......... 150 Figure F-2................. Figure 3-4................ 24 Matrix Multiplication with Shared Memory ....................................... Figure F-1.... 5 Grid of Thread Blocks ...........................2 xi ....................... 167 Figure G-3 Examples of Irregular and Colliding Shared Memory Accesses for Devices of Compute Capability 2.........................x ........... 13 Matrix Multiplication without Shared Memory ...... 55 The Driver API is Backward...................................................... Figure 2-3................ 152 Figure G-1...... 3 Figure 1-3.......... 28 Library Context Management ...................... 4-Byte Word per Thread...................... Figure 3-1.. One-Dimensional Table Lookup Using Linear Filtering .............................. 11 Heterogeneous Programming .. but Not Forward Compatible ......................................................................... and Associated Memory Transactions Based on Compute Capability ................... Figure 3-2..... 151 Figure F-3...................... Figure 2-2.............................................................................. 164 Figure G-2 Examples of Strided Shared Memory Accesses for Devices of Compute Capability 2............................ Automatic Scalability .......... The GPU Devotes More Transistors to Data Processing ..................................................................... 4 Figure 1-4. 9 Memory Hierarchy ............................................................ CUDA is Designed to Support Various Languages or Application Programming Interfaces ..... Linear Filtering of a One-Dimensional Texture of Four Texels in Clamp Addressing Mode........................ Figure 2-1.List of Figures Figure 1-1................................... Figure 3-3............ 79 Nearest-Point Sampling of a One-Dimensional Texture of Four Texels ... Examples of Global Memory Accesses by a Warp........ Floating-Point Operations per Second and Memory Bandwidth for the CPU and GPU 2 Figure 1-2............................. 169 CUDA C Programming Guide Version 3...............

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1 From Graphics Processing to General-Purpose Parallel Computing Driven by the insatiable market demand for realtime. the programmable Graphic Processor Unit or GPU has evolved into a highly parallel. Introduction 1. high-definition 3D graphics. CUDA C Programming Guide Version 3. manycore processor with tremendous computational horsepower and very high memory bandwidth. multithreaded. as illustrated by Figure 1-1.1 1 .Chapter 1.

Floating-Point Operations per Second and Memory Bandwidth for the CPU and GPU 2 CUDA C Programming Guide Version 3. Introduction Figure 1-1.Chapter 1.2 .

the GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. stereo vision. video encoding and decoding. In fact. In 3D rendering. large sets of pixels and vertices are mapped to parallel threads. NVIDIA introduced CUDA™. Because the same program is executed for each data element. 1. image scaling. many algorithms outside the field of image rendering and processing are accelerated by data-parallel processing. Control ALU ALU ALU ALU Cache DRAM DRAM CPU GPU Figure 1-2. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Similarly. a general purpose parallel computing architecture – with a new parallel programming model and instruction set architecture – that leverages the parallel compute engine in NVIDIA GPUs to CUDA C Programming Guide Version 3. The GPU Devotes More Transistors to Data Processing More specifically.2 3 . there is a lower requirement for sophisticated flow control. image and media processing applications such as post-processing of rendered images. Introduction The reason behind the discrepancy in floating-point capability between the CPU and the GPU is that the GPU is specialized for compute-intensive. from general signal processing or physics simulation to computational finance or computational biology.2 CUDA™: a General-Purpose Parallel Computing Architecture In November 2006. Data-parallel processing maps data elements to parallel processing threads.Chapter 1. the memory access latency can be hidden with calculations instead of big data caches. as schematically illustrated by Figure 1-2. and because it is executed on many data elements and has high arithmetic intensity. highly parallel computation – exactly what graphics rendering is about – and therefore designed such that more transistors are devoted to data processing rather than data caching and flow control. and pattern recognition can map image blocks and pixels to parallel processing threads.

They guide the programmer to partition the problem into coarse sub-problems that can be solved independently in parallel by blocks of threads. nested within coarse-grained data parallelism and task parallelism. The challenge is to develop application software that transparently scales its parallelism to leverage the increasing number of processor cores.2 . CUDA is Designed to Support Various Languages or Application Programming Interfaces 1. much as 3D graphics applications transparently scale their parallelism to manycore GPUs with widely varying numbers of cores. their parallelism continues to scale with Moore‟s law. This decomposition preserves language expressivity by allowing threads to 4 CUDA C Programming Guide Version 3. and DirectCompute. At its core are three key abstractions – a hierarchy of thread groups. such as CUDA FORTRAN. and barrier synchronization – that are simply exposed to the programmer as a minimal set of language extensions. Furthermore. Introduction solve many complex computational problems in a more efficient way than on a CPU. and each sub-problem into finer pieces that can be solved cooperatively in parallel by all threads within the block. As illustrated by Figure 1-3. shared memories. OpenCL. Figure 1-3. These abstractions provide fine-grained data parallelism and thread parallelism. CUDA comes with a software environment that allows developers to use C as a high-level programming language. other languages or application programming interfaces are supported.3 A Scalable Programming Model The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems.Chapter 1. The CUDA parallel programming model is designed to overcome this challenge while maintaining a low learning curve for programmers familiar with standard programming languages such as C.

This scalable programming model allows the CUDA architecture to span a wide market range by simply scaling the number of processors and memory partitions: from the high-performance enthusiast GeForce GPUs and professional Quadro and Tesla computing products to a variety of inexpensive. so that a compiled CUDA program can execute on any number of processor cores as illustrated by Figure 1-4. and at the same time enables automatic scalability. Figure 1-4. each block of threads can be scheduled on any of the available processor cores. Multithreaded CUDA Program Block 0 Block 4 Block 1 Block 5 Block 5 Block 2 Block 6 Block 6 Block 3 Block 7 GPU with 2 Cores Core 0 Core 1 GPU with 4 Cores Core 0 Core 1 Core 2 Core 3 Block 0 Block 1 Block 0 Block 1 Block 2 Block 3 Block 2 Block 3 Block 4 Block 5 Block 6 Block 7 Block 4 Block 5 Block 6 Block 7 A multithreaded program is partitioned into blocks of threads that execute independently from each other. concurrently or sequentially.2 5 .Chapter 1. so that a GPU with more cores will automatically execute the program in less time than a GPU with fewer cores. and only the runtime system needs to know the physical processor count. Introduction cooperate when solving each sub-problem. mainstream GeForce GPUs (see Appendix A for a list of all CUDA-enabled GPUs). Indeed. Automatic Scalability CUDA C Programming Guide Version 3. in any order.

Chapter 3 describes the programming interface. Chapter 4 describes the hardware implementation. Introduction 1. Chapter 2 outlines the CUDA programming model. Appendix F gives more details on texture fetching.2 . 6 CUDA C Programming Guide Version 3. Appendix G gives the technical specifications of various devices. Appendix E lists the specific keywords and directives supported by nvcc.Chapter 1. as well as more architectural details. Appendix C lists the mathematical functions supported in CUDA. Chapter 5 gives some guidance on how to achieve maximum performance. Appendix A lists all CUDA-enabled devices.4 Document’s Structure This document is organized into the following chapters:             Chapter 1 is a general introduction to CUDA. Appendix D lists the C++ constructs supported in device code. Appendix B is a detailed description of all extensions to the C language.

} int main() { . called kernels. As an illustration. the following sample code adds two vectors A and B of size N and stores the result into vector C: // Kernel definition __global__ void VecAdd(float* A. } Here. each of the N threads that execute VecAdd() performs one pair-wise addition. B.16). C[i] = A[i] + B[i]. CUDA C Programming Guide Version 3. float* B.Chapter 2. C). // Kernel invocation with N threads VecAdd<<<1. 2. Full code for the vector addition example used in this chapter and the next can be found in the vectorAdd SDK code sample. An extensive description of CUDA C is given in Section 3. A kernel is defined using the __global__ declaration specifier and the number of CUDA threads that execute that kernel for a given kernel call is specified using a new <<<…>>> execution configuration syntax (see Appendix B. as opposed to only once like regular C functions.2..1 7 . are executed N times in parallel by N different CUDA threads. that.1 Kernels CUDA C extends C by allowing the programmer to define C functions. when called. N>>>(A.x. float* C) { int i = threadIdx. Each thread that executes the kernel is given a unique thread ID that is accessible within the kernel through the built-in threadIdx variable. Programming Model This chapter introduces the main concepts behind the CUDA programming model by outlining how they are exposed in C..

or three-dimensional thread index. forming a one-dimensional..y. the following code adds two matrices A and B of size NxN and stores the result into matrix C: // Kernel definition __global__ void MatAdd(float A[N][N]. As an example. 8 CUDA C Programming Guide Version 3. float B[N][N].Chapter 2. so that the total number of threads is equal to the number of threads per block times the number of blocks. The number of thread blocks in a grid is usually dictated by the size of the data being processed or the number of processors in the system.. since all threads of a block are expected to reside on the same processor core and must share the limited memory resources of that core. a thread block may contain up to 1024 threads. // Kernel invocation with one block of N * N * 1 threads int numBlocks = 1. y) is (x + y Dx). This provides a natural way to invoke computation across the elements in a domain such as a vector. } There is a limit to the number of threads per block.2 . a kernel can be executed by multiple equally-shaped thread blocks. B. Programming Model 2. The index of a thread and its thread ID relate to each other in a straightforward way: For a one-dimensional block. y. the thread ID of a thread of index (x. float C[N][N]) { int i = threadIdx. However.2 Thread Hierarchy For convenience. Dy). which it can greatly exceed. or volume. so that threads can be identified using a one-dimensional. threadsPerBlock>>>(A. MatAdd<<<numBlocks. threadIdx is a 3-component vector. On current GPUs.x. N). or three-dimensional thread block. matrix. for a two-dimensional block of size (Dx. Blocks are organized into a one-dimensional or two-dimensional grid of thread blocks as illustrated by Figure 2-1. Dz). for a threedimensional block of size (Dx. } int main() { . two-dimensional. two-dimensional. z) is (x + y Dx + z Dx Dy). they are the same. C). the thread ID of a thread of index (x. Dy. dim3 threadsPerBlock(N. C[i][j] = A[i][j] + B[i][j]. int j = threadIdx.

float B[N][N]. the code becomes as follows. 1) Thread (1. 1) Thread (2.2 9 .x * blockDim.x. 1) Thread (0. Grid of Thread Blocks The number of threads per block and the number of blocks per grid specified in the <<<…>>> syntax can be of type int or dim3. CUDA C Programming Guide Version 3.Chapter 2: Programming Model Grid Block (0. 1) Block (1. Extending the previous MatAdd() example to handle multiple blocks. if (i < N && j < N) C[i][j] = A[i][j] + B[i][j]. 2) Thread (1. 0) Block (1. 1) Thread (0. 0) Thread (2. 2) Figure 2-1. 0) Thread (0. // Kernel definition __global__ void MatAdd(float A[N][N]. int j = blockIdx. Two-dimensional blocks or grids can be specified as in the example above. The dimension of the thread block is accessible within the kernel through the built-in blockDim variable.y + threadIdx. 1) Block (2. 1) Thread (3. Each block within the grid can be identified by a one-dimensional or twodimensional index accessible within the kernel through the built-in blockIdx variable. 2) Thread (2. 0) Block (0. 0) Block (2.x + threadIdx. 0) Thread (3. float C[N][N]) { int i = blockIdx. 2) Thread (3. 1) Block (1. 0) Thread (1.y * blockDim.y.

The grid is created with enough blocks to have one thread per matrix element as before. Each thread block has shared memory visible to all threads of the block and with the same lifetime as the block.2. N / threadsPerBlock.. MatAdd<<<numBlocks.y). although that need not be the case. The global. 16).1. 5. and texture memory spaces are persistent across kernel launches by the same application.3. __syncthreads() acts as a barrier at which all threads in the block must wait before any is allowed to proceed. 2. All threads have access to the same global memory. one can specify synchronization points in the kernel by calling the __syncthreads() intrinsic function. Each thread has private local memory. is a common choice.3. For efficient cooperation. as well as data filtering. More precisely. This independence requirement allows thread blocks to be scheduled in any order across any number of cores as illustrated by Figure 1-4. B.2. dim3 numBlocks(N / threadsPerBlock. in parallel or in series. Thread blocks are required to execute independently: It must be possible to execute them in any order.4. this example assumes that the number of threads per grid in each dimension is evenly divisible by the number of threads per block in that dimension. Texture memory also offers different addressing modes.2 gives an example of using shared memory. Programming Model } int main() { . enabling programmers to write code that scales with the number of cores. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. and texture memory spaces are optimized for different memory usages (see Sections 5. // Kernel invocation dim3 threadsPerBlock(16. Section 3. constant. threadsPerBlock>>>(A. constant..x.2. C). the shared memory is expected to be a low-latency memory near each processor core (much like an L1 cache) and __syncthreads() is expected to be lightweight.Chapter 2. and 5.4).2 .2. } A thread block size of 16x16 (256 threads).3 Memory Hierarchy CUDA threads may access data from multiple memory spaces during their execution as illustrated by Figure 2-2. for some specific data formats (see Section 3. The global. 10 CUDA C Programming Guide Version 3.3. For simplicity. although arbitrary in this case.5). Threads within a block can cooperate by sharing data through some shared memory and by synchronizing their execution to coordinate memory accesses.2.

0) Block (1. Memory Hierarchy 2. 1) Block (0. when the kernels execute on a GPU and the rest of the C program executes on a CPU. 1) Block (1.4 Heterogeneous Programming As illustrated by Figure 2-3. 2) Block (1. 0) Block (0. 1) Grid 1 Block (0. for example. 1) Block (2. This is the case. 0) Block (2. 1) Block (1. CUDA C Programming Guide Version 3.2 11 . 0) Block (1.Chapter 2: Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Figure 2-2. the CUDA programming model assumes that the CUDA threads execute on a physically separate device that operates as a coprocessor to the host running the C program. 0) Global memory Block (0.

a program manages the global. Programming Model The CUDA programming model also assumes that both the host and the device maintain their own separate memory spaces in DRAM. and texture memory spaces visible to kernels through calls to the CUDA runtime (described in Chapter 3).2 .Chapter 2. 12 CUDA C Programming Guide Version 3. Therefore. referred to as host memory and device memory. This includes device memory allocation and deallocation as well as data transfer between host and device memory. constant. respectively.

2 13 . 0) Block (0. 1) Block (1. 0) Block (0. 1) Block (2.Chapter 2: Programming Model C Program Sequential Execution Serial code Host Parallel kernel Kernel0<<<>>>() Device Grid 0 Block (0. 0) Block (1. Heterogeneous Programming CUDA C Programming Guide Version 3. 1) Block (1. 0) Block (2. 1) Serial code Host Parallel kernel Kernel1<<<>>>() Device Grid 1 Block (0. 2) Block (1. 0) Block (1. Figure 2-3. 1) Block (0. 2) Serial code executes on the host while parallel code executes on the device.

x (Their major revision number is 1).Chapter 2.2 . Appendix G gives the technical specifications of each compute capability. Prior devices are all of compute capability 1. The minor revision number corresponds to an incremental improvement to the core architecture. Devices with the same major revision number are of the same core architecture. Programming Model 2. possibly including new features. The major revision number of devices based on the Fermi architecture is 2. Appendix A lists of all CUDA-enabled devices along with their compute capability.5 Compute Capability The compute capability of a device is defined by a major revision number and a minor revision number. 14 CUDA C Programming Guide Version 3.

The CUDA driver API is a lower-level C API that provides functions to load kernels as modules of CUDA binary or assembly code.2 continues the description of CUDA C started in Chapter 2. but offers a better level of control and is language-independent since it handles binary or assembly code. interoperability with graphics APIs. to inspect their parameters. device enumeration. asynchronous execution. It also introduces concepts that are common to both CUDA C and the driver API: linear memory. Section 3. 3. transfer data between host memory and device memory.1. CUDA C comes with a runtime API and both the runtime API and the driver API provide functions to allocate and deallocate device memory. and to launch them. Binary and assembly codes are usually obtained by compiling kernels written in C.3 assumes knowledge of these concepts and describes how they are exposed by the driver API. The runtime API is built on top of the CUDA driver API. called PTX.Chapter 3. These extensions allow programmers to define a kernel as a C function and use some new syntax to specify the grid and block dimension each time the function is called. texture memory. It is however usually more CUDA C Programming Guide Version 3. is harder to program and debug. Programming Interface Two interfaces are currently supported to write CUDA programs: CUDA C and the CUDA driver API. the CUDA driver API requires more code. Section 3. and module management are all implicit and resulting code is more concise. but it can use both as described in Section 3. shared memory. An application typically uses either one or the other. Any source file that contains some of these extensions must be compiled with nvcc as outlined in Section 3. which is described in the PTX reference manual. manage systems with multiple devices. CUDA arrays. context. CUDA C exposes the CUDA programming model as a minimal set of extensions to the C language.4.1 15 . Initialization.1 Compilation with NVCC Kernels can be written using the CUDA instruction set architecture. In contrast. page-locked host memory. etc.

compiling with –code=sm_13 produces binary code for devices of compute capability 1.1 (and described in more details in Section B.1. In other words.3. Programming Interface effective to use a high-level programming language such as C. Applications can then: Either load and execute the PTX code or cubin object on the device using the CUDA driver API (see Section 3.3 PTX Compatibility Some PTX instructions are only supported on devices of higher compute capabilities.1 Compilation Workflow Source files compiled with nvcc can include a mix of host code (i. It is also the only way for applications to run on devices that did not exist at the time the application was compiled. code that executes on the device). Binary compatibility is guaranteed from one minor revision to the next one.1. 3. as detailed in Section 3.4. This section gives an overview of nvcc workflow and command options.  Or link to the generated host code.y is only guaranteed to execute on devices of compute capability X.2 Binary Compatibility Binary code is architecture-specific. For example.  3. nvcc‟s basic workflow consists in separating device code from host code and compiling the device code into an assembly form (PTX code) and/or binary form (cubin object). nvcc is a compiler driver that simplifies the process of compiling C or PTX code: It provides simple and familiar command line options and executes them by invoking the collection of tools that implement the different compilation stages.16) into the necessary CUDA C runtime function calls to load and launch each compiled kernel. 3. a cubin object generated for compute capability X.z where z≥y. The generated host code is output either as C code that is left to be compiled using another tool or as object code directly by letting nvcc invoke the host compiler during the last compilation stage.3) and ignore the generated host code (if any).e.e. Just-in-time compilation increases application load time. the generated host code includes the PTX code and/or cubin object as a global initialized data array and a translation of the <<<…>>> syntax introduced in Section 2.1. kernels must be compiled into binary code by nvcc to execute on the device. This is called just-in-time compilation. but not from one minor revision to the previous one or across major revisions. A complete description can be found in the nvcc user manual. code that executes on the host) and device code (i. but allow applications to benefit from latest compiler improvements. atomic instructions on global memory are only supported 16 CUDA C Programming Guide Version 3.Chapter 3.2 . In both cases. Any PTX code loaded by an application at runtime is compiled further to binary code by the device driver.1. A cubin object is generated using the compiler option –code that specifies the targeted architecture: For example.

in the above example. and gencode compiler options. –code. “arch=sm_13” is a shorthand for “arch=compute_13 code=compute_13. PTX code produced for some specific compute capability can always be compiled to binary code of greater or equal compute capability. Programming Interface on devices of compute capability 1. The nvcc user manual lists various shorthands for the –arch. __CUDA_ARCH__ is equal to 110.1. which are only supported in devices of compute capability 1. For example. 1. which.2 and 3.sm_13\’”). for example. nvcc x.0 and higher. will be: 1.1 (second -gencode option).code=sm_10 –gencode arch=compute_11.1 PTX code for devices with compute capabilities 2. code that contains double-precision arithmetic.3.2 17 .0 binary code for devices with compute capability 1.1 binary code for devices with compute capability 1.code=\’compute_13.1.cu –gencode arch=compute_10.1 and above.sm_13” (which is the same as “gencode arch=compute_13.0.1.3 and above. The –arch compiler option specifies the compute capability that is assumed when compiling C to PTX code.2. must be compiled with “-arch=sm_13” (or higher compute capability). When compiling with “arch=compute_11” for example. 1. for example.sm_11\’ embeds binary code compatible with compute capability 1. In particular. to be able to execute code on future architectures with higher compute capability – for which no binary code can be generated yet –. So.code=\’compute_11. an application must load PTX code that will be compiled just-intime for these devices.4 Application Compatibility To execute code on devices of specific compute capability. CUDA C Programming Guide Version 3. For example.1 and higher.  1. Host code is generated to automatically select at runtime the most appropriate code to load and execute.cu can have an optimized code path that uses atomic operations.1. The __CUDA_ARCH__ macro can be used to differentiate various code paths based on compute capability. Which PTX and binary code gets embedded in a CUDA C application is controlled by the –arch and –code compiler options or the –gencode compiler option as detailed in the nvcc user manual. It is only defined for device code. double-precision instructions are only supported on devices of compute capability 1.Chapter 3. x.3. an application must load binary or PTX code that is compatible with this compute capability as described in Sections 3. 3.  Applications using the driver API must compile code to separate files and explicitly load and execute the most appropriate file at runtime.  binary code obtained by compiling 1. otherwise double-precision arithmetic will get demoted to single-precision arithmetic.0 (first –gencode option) and PTX and binary code compatible with compute capability 1.

5 C/C++ Compatibility The front end of the compiler processes CUDA source files according to C++ syntax rules.2 . any resource (memory. Device code compiled in 64-bit mode is only supported with host code compiled in 64-bit mode.1) is created under 18 CUDA C Programming Guide Version 3. A complete description of all extensions can be found in Appendix B and a complete description of the runtime in the CUDA reference manual. The 32-bit version of nvcc can compile device code in 64-bit mode also using the m64 compiler option. As a consequence of the use of C++ syntax rules. the 32-bit version of nvcc compiles device code in 32-bit mode and device code compiled in 32-bit mode is only supported with host code compiled in 32-bit mode. Full C++ is supported for the host code.1. This is because a CUDA context (see Section 3. The 64-bit version of nvcc can compile device code in 32-bit mode also using the m32 compiler option. There is no explicit initialization function for the runtime. 3. void pointers (e. One needs to keep this in mind when timing runtime function calls and when interpreting the error code from the first call into the runtime.1. pointers are 64-bit). The core language extensions have been introduced in Chapter 2. kernel launches. Programming Interface 3. This section continues with an introduction to the runtime.e. etc.g..2 CUDA C CUDA C provides a simple path for users familiar with the C programming language to easily write programs for execution by the device. Once the runtime has been initialized in a host thread. event. The runtime is implemented in the cudart dynamic library and all its entry points are prefixed with cuda.Chapter 3.) allocated via some runtime function call in the host thread is only valid within the context of the host thread. However. Therefore only runtime functions calls made by the host thread (memory copies. nvcc also support specific keywords and directives detailed in Appendix E. 3. it initializes the first time a runtime function is called (more specifically any function other than functions from the device and version management sections of the reference manual). only a subset of C++ is fully supported for the device code as described in detail in Appendix D. It consists of a minimal set of extensions to the C language and a runtime library. …) can operate on these resources. stream. returned by malloc()) cannot be assigned to non-void pointers without a typecast.3.6 64-Bit Compatibility The 64-bit version of nvcc compiles device code in 64-bit mode (i. Similarly.

each with their own separate memory.1.. size). as well as transfer data between host memory and device memory.1 Device Memory As mentioned in Section 2. cudaMalloc(&d_A. so the runtime provides functions to allocate. On system with multiple devices. cudaMalloc(&d_B. the CUDA programming model assumes a system composed of a host and a device.4. // Allocate input vectors h_A and h_B in host memory float* h_A = (float*)malloc(size). float* B. Programming Interface the hood as part of initialization and made current to the host thread.2.. in a binary tree. Linear memory is typically allocated using cudaMalloc() and freed using cudaFree() and data transfer between host memory and device memory are typically done using cudaMemcpy(). int N) { int i = blockDim... 3.x + threadIdx.Chapter 3. In the vector addition code sample of Section 2. and it cannot be made current to any other host thread.2 19 . if (i < N) C[i] = A[i] + B[i]. and copy device memory. so separately allocated entities can reference one another via pointers. Device memory can be allocated either as linear memory or as CUDA arrays. } // Host code int main() { int N = . // Allocate vectors in device memory float* d_A.3.x * blockIdx. Linear memory exists on the device in a 32-bit address space for devices of compute capability 1. float* d_B.x.x and 40-bit address space of devices of compute capability 2. for example. float* h_B = (float*)malloc(size). deallocate.4. They are described in Section 3. CUDA C Programming Guide Version 3. Kernels can only operate out of device memory. the vectors need to be copied from host memory to device memory: // Device code __global__ void VecAdd(float* A. size_t size = N * sizeof(float).. CUDA arrays are opaque memory layouts optimized for texture fetching. float* d_C.2. size). float* C.x. kernels are executed on device 0 by default as detailed in Section 3.2. // Initialize input vectors .

cudaMemcpyHostToDevice). cudaMemcpyHostToDevice). // Free device memory cudaFree(d_A). int blocksPerGrid = (N + threadsPerBlock – 1) / threadsPerBlock. height). threadsPerBlock>>>(d_A. // Device code __global__ void MyKernel(float* devPtr. width * sizeof(float). &pitch. N). ++c) { float element = row[c]. VecAdd<<<blocksPerGrid.3. size. size. // Copy result from device memory to host memory // h_C contains the result in host memory cudaMemcpy(h_C. 512>>>(devPtr. cudaMemcpy(d_B. d_B. therefore ensuring best performance when accessing the row addresses or performing copies between 2D arrays and other regions of device memory (using the cudaMemcpy2D() and cudaMemcpy3D() functions).Chapter 3. d_C. pitch. r < height.1. These functions are recommended for allocations of 2D or 3D arrays as it makes sure that the allocation is appropriately padded to meet the alignment requirements described in Section 5. cudaMallocPitch(&devPtr. width. float* devPtr. The returned pitch (or stride) must be used to access array elements. cudaMemcpyDeviceToHost).. size). ++r) { float* row = (float*)((char*)devPtr + r * pitch). for (int c = 0. cudaFree(d_B). } } } The following code sample allocates a width×height×depth 3D array of floating-point values and shows how to loop over the array elements in device code: 20 CUDA C Programming Guide Version 3. // Invoke kernel int threadsPerBlock = 256. int width..2 . size. cudaFree(d_C). int height) { for (int r = 0. The following code sample allocates a width×height 2D array of floating-point values and shows how to loop over the array elements in device code: // Host code int width = 64. } Linear memory can also be allocated through cudaMallocPitch() and cudaMalloc3D(). h_A. height). c < width. Programming Interface cudaMalloc(&d_C. // Free host memory . MyKernel<<<100. // Copy vectors from host memory to device memory cudaMemcpy(d_A.2. size_t pitch. size_t pitch. d_C. h_B. height = 64.

int height. The size of the allocated memory is obtained through cudaGetSymbolSize(). cudaMemcpyFromSymbol(data. cudaExtent extent = make_cudaExtent(width * sizeof(float).pitch. z < depth. extent). for (int y = 0. float data[256]. __device__ float* devPointer. int width. size_t pitch = devPitchedPtr. 256 * sizeof(float)). sizeof(data)).2. linear memory allocated with cudaMallocPitch() or cudaMalloc3D().2 21 . } } } } The reference manual lists all the various functions used to copy memory between linear memory allocated with cudaMalloc(). size_t slicePitch = pitch * height. height. cudaMemcpyToSymbol(constData. depth = 64. ++z) { char* slice = devPtr + z * slicePitch. cudaMemcpyToSymbol(devPointer. cudaPitchedPtr devPitchedPtr. CUDA arrays. ++y) { float* row = (float*)(slice + y * pitch). The following code sample illustrates various ways of accessing global variables via the runtime API: __constant__ float constData[256]. depth). depth).ptr. 3. cudaMalloc3D(&devPitchedPtr. __device__ float devData. CUDA C Programming Guide Version 3. cudaMemcpyToSymbol(devData. Programming Interface // Host code int width = 64. sizeof(float)). for (int z = 0.14f. 512>>>(devPitchedPtr. cudaMalloc(&ptr. MyKernel<<<100.Chapter 3. y < height. constData. x < width. sizeof(ptr)). data. height = 64. &ptr. sizeof(data)). int depth) { char* devPtr = devPitchedPtr.2 Shared Memory As detailed in Section B.2 shared memory is allocated using the __shared__ qualifier. float* ptr. height. &value. ++x) { float element = row[x]. cudaGetSymbolAddress() is used to retrieve the address pointing to the memory allocated for a variable declared in global memory space. for (int x = 0. // Device code __global__ void MyKernel(cudaPitchedPtr devPitchedPtr. and memory allocated for variables declared in global or constant memory space. float value = 3. width.

A.elements.width. int height. // Matrix multiplication . B. Each thread reads one row of A and one column of B and computes the corresponding element of C as illustrated in Figure 3-1. col) = *(M. cudaMemcpyHostToDevice).elements.height = C. cudaMemcpy(d_A.3. The following code sample is a straightforward implementation of matrix multiplication that does not take advantage of shared memory. float* elements. const Matrix. d_C). size_t size = A. size). dimBlock>>>(d_A.width * A.width = C. d_C. d_A. cudaMemcpy(d_B.x. A.width = B. // Invoke kernel dim3 dimBlock(BLOCK_SIZE. Matrix d_B.height = B. d_B.elements. cudaMalloc(&d_C.height = A.elements. // Allocate C in device memory Matrix d_C.width * C. A is therefore read B.width * B.height / dimBlock.elements. d_C.Chapter 3.height times. } Matrix.elements. size = B. cudaMalloc(&d_B.width / dimBlock. size.height.width.elements + row * M. Matrix). d_A.width times from global memory and B is read A.height * sizeof(float). cudaMalloc(&d_A.height.height * sizeof(float). // Thread block size #define BLOCK_SIZE 16 // Forward declaration of the matrix multiplication kernel __global__ void MatMulKernel(const Matrix. Matrix C) { // Load A and B to device memory Matrix d_A.elements. size = C. size). Programming Interface Shared memory is expected to be much faster than global memory as mentioned in Section 2.width. size. d_B.elements. size). const Matrix B. size.width + col) typedef struct { int width. cudaMemcpyDeviceToHost).width = A.height * sizeof(float). Cd. MatMulKernel<<<dimGrid. Any opportunity to replace global memory accesses by shared memory accesses should therefore be exploited as illustrated by the following matrix multiplication example. 22 CUDA C Programming Guide Version 3. d_B.2 .height.2 and detailed in Section 5. cudaMemcpyHostToDevice). // Read C from device memory cudaMemcpy(C. dim3 dimGrid(B.Host code // Matrix dimensions are assumed to be multiples of BLOCK_SIZE void MatMul(const Matrix A. BLOCK_SIZE).y).2.3.elements. // Matrices are stored in row-major order: // M(row.

width + col].2 23 . Matrix C) { // Each thread computes one element of C // by accumulating results into Cvalue float Cvalue = 0. Matrix B.elements).width + col] = Cvalue. e < A.x * blockDim.y.width. int col = blockIdx. C.x + threadIdx. Programming Interface // Free device memory cudaFree(d_A.y + threadIdx. cudaFree(d_B.elements[e * B. } CUDA C Programming Guide Version 3. } // Matrix multiplication kernel called by MatMul() __global__ void MatMulKernel(Matrix A.elements[row * C.y * blockDim. for (int e = 0.elements).elements). int row = blockIdx.elements[row * A. ++e) Cvalue += A.width + e] * B.Chapter 3.x. cudaFree(d_C.

In this implementation.width) that has the same column indices as Csub. Each of these products is performed by first loading the two corresponding square matrices from global memory to shared memory with one thread loading one element of each matrix. As illustrated in Figure 3-2. Each thread accumulates the result of each of these products into a register and once done writes the result to global memory.width A. In order to fit into the device‟s resources.Chapter 3. Matrix Multiplication without Shared Memory The following code sample is an implementation of matrix multiplication that does take advantage of shared memory. and then by having each thread compute one element of the product. Programming Interface 0 col B 0 A C row A.height B.width. each thread block is responsible for computing one square sub-matrix Csub of C and each thread within the block is responsible for computing one element of Csub.width Figure 3-1. Csub is equal to the product of two rectangular matrices: the sub-matrix of A of dimension (A. these two rectangular matrices are divided into as many square matrices of dimension block_size as necessary and Csub is computed as the sum of the products of these square matrices. block_size) that has the same line indices as Csub. A. 24 CUDA C Programming Guide Version 3.height-1 B.width-1 .2 A.height B. and the submatrix of B of dimension (block_size.

int stride. // Matrices are stored in row-major order: // M(row.width = BLOCK_SIZE.elements[row * A.stride + col) typedef struct { int width. const Matrix. int col) { Matrix Asub.elements = &A. float* elements.elements[row * A.Chapter 3. Asub. const Matrix B.stride = A. // Matrix multiplication . Asub. The Matrix type from the previous code sample is augmented with a stride field. } // Set a matrix element __device__ void SetElement(Matrix A. float value) { A. } // Thread block size #define BLOCK_SIZE 16 // Forward declaration of the matrix multiplication kernel __global__ void MatMulKernel(const Matrix.1. int col) { return A. // Get a matrix element __device__ float GetElement(const Matrix A.stride. so that sub-matrices can be efficiently represented with the same type.stride * BLOCK_SIZE * row + BLOCK_SIZE * col]. int row. Asub. } // Get the BLOCK_SIZExBLOCK_SIZE sub-matrix Asub of A that is // located col sub-matrices to the right and row sub-matrices down // from the upper-left corner of A __device__ Matrix GetSubMatrix(Matrix A.2 25 .stride + col].height = BLOCK_SIZE. CUDA C Programming Guide Version 3. return Asub.width / block_size) times from global memory and B is read (A. int col. } Matrix.1) are used to get and set elements and build any submatrix from a matrix.stride + col] = value. Asub. col) = *(M. int height. int row.elements + row * M. Programming Interface By blocking the computation this way. Matrix C) { // Load A and B to device memory Matrix d_A.Host code // Matrix dimensions are assumed to be multiples of BLOCK_SIZE void MatMul(const Matrix A. Matrix).height / block_size) times. we take advantage of fast shared memory and save a lot of global memory bandwidth since A is only read (B. __device__ functions (see Section B. int row.elements[A.

// Loop over all the sub-matrices of A and B that are // required to compute Csub // Multiply each pair of sub-matrices together // and accumulate the results for (int m = 0.x. B. int blockCol = blockIdx. ++m) { 26 CUDA C Programming Guide Version 3.width / BLOCK_SIZE). MatMulKernel<<<dimGrid.height. // Allocate C in device memory Matrix d_C. size.width / dimBlock. // Each thread computes one element of Csub // by accumulating results into Cvalue float Cvalue = 0.width. cudaMalloc(&d_A. dim3 dimGrid(B.elements). size). m < (A.elements).x.width. size = B. d_A. Matrix d_B. cudaFree(d_C. blockCol).height = B. cudaMemcpy(d_B.elements. size. Matrix B. d_B.y.height * sizeof(float). size = C. d_C.height = C.y). A. d_C. cudaFree(d_B.height. size_t size = A.2 .elements. A. // Free device memory cudaFree(d_A.stride = C.Chapter 3. d_C). dimBlock>>>(d_A.elements.width.height * sizeof(float). BLOCK_SIZE).width = d_A.elements.elements). // Read C from device memory cudaMemcpy(C.elements. d_C.height = A. cudaMalloc(&d_B. cudaMalloc(&d_C.height.width = d_C. size.width * B.stride = A.elements.elements.height / dimBlock. int col = threadIdx. Programming Interface d_A.x. d_B.y.width * C. cudaMemcpyHostToDevice). // Thread row and column within Csub int row = threadIdx. blockRow.height * sizeof(float).width = d_B. cudaMemcpyHostToDevice). size). cudaMemcpy(d_A. d_B.elements. cudaMemcpyDeviceToHost).width * A. Matrix C) { // Block row and column int blockRow = blockIdx.stride = B.elements. // Each thread block computes one sub-matrix Csub of C Matrix Csub = GetSubMatrix(C. } // Matrix multiplication kernel called by MatMul() __global__ void MatMulKernel(Matrix A. size). // Invoke kernel dim3 dimBlock(BLOCK_SIZE.

} // Write Csub to device memory // Each thread writes one element SetElement(Csub. // Get sub-matrix Bsub of B Matrix Bsub = GetSubMatrix(B. col. blockCol). // Synchronize to make sure the sub-matrices are loaded // before starting the computation __syncthreads().2 27 . row. // Multiply Asub and Bsub together for (int e = 0. blockRow. col). Cvalue). row. // Shared memory used to store Asub and Bsub respectively __shared__ float As[BLOCK_SIZE][BLOCK_SIZE]. Bs[row][col] = GetElement(Bsub. // Load Asub and Bsub from device memory to shared memory // Each thread loads one element of each sub-matrix As[row][col] = GetElement(Asub. Programming Interface // Get sub-matrix Asub of A Matrix Asub = GetSubMatrix(A. col). m).Chapter 3. row. } CUDA C Programming Guide Version 3. ++e) Cvalue += As[row][e] * Bs[e][col]. m. e < BLOCK_SIZE. // Synchronize to make sure that the preceding // computation is done before loading two new // sub-matrices of A and B in the next iteration __syncthreads(). __shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE].

It also determines the number of CUDA-enabled devices. and one of them can be selected for kernel executions.width A. multiple host threads are required to execute device code on multiple devices. Several host threads can execute device code on the same device. Also. cudaGetDeviceCount(&deviceCount). any CUDA resources created through the runtime in one host thread cannot be used by the runtime from another host thread. for (device = 0.height B. device < deviceCount. Matrix Multiplication with Shared Memory 3. cudaGetDeviceProperties(&deviceProp. int deviceCount. As a consequence.3 Multiple Devices A host system can have multiple devices.2.Chapter 3. Programming Interface blockCol B BLOCK_SIZE 0 0 A C col Csub BLOCK_SIZE-1 BLOCK_SIZE blockRow BLOCK_SIZE row BLOCK_SIZE-1 BLOCK_SIZE BLOCK_SIZE BLOCK_SIZE B. ++device) { cudaDeviceProp deviceProp.height .width Figure 3-2. their properties can be queried. but by design. device). int device. if (dev == 0) { 28 CUDA C Programming Guide Version 3. The following code sample enumerates all devices in the system and retrieves their properties.2 A. a host thread can execute device code on only one device at any given time. These devices can be enumerated.

Chapter 3. Programming Interface

if (deviceProp.major == 9999 && deviceProp.minor == 9999) printf("There is no device supporting CUDA.\n"); else if (deviceCount == 1) printf("There is 1 device supporting CUDA\n"); else printf("There are %d devices supporting CUDA\n", deviceCount); } }

By default, the device associated to the host thread is implicitly selected as device 0 as soon as a non-device management runtime function is called (see Section 3.6 for exceptions). Any other device can be selected by calling cudaSetDevice() first. After a device has been selected, either implicitly or explicitly, any subsequent explicit call to cudaSetDevice() will fail up until cudaThreadExit() is called. cudaThreadExit() cleans up all runtime-related resources associated with the calling host thread. Any subsequent API call reinitializes the runtime.

3.2.4

Texture and Surface Memory
CUDA supports a subset of the texturing hardware that the GPU uses for graphics to access texture and surface memory. Reading data from texture or surface memory instead of global memory can have several performance benefits as described in Section 5.3.2.5.

3.2.4.1

Texture Memory
Texture memory is read from kernels using device functions called texture fetches, described in Section B.8. The first parameter of a texture fetch specifies an object called a texture reference. A texture reference defines which part of texture memory is fetched. As detailed in Section 3.2.4.1.3, it must be bound through runtime functions to some region of memory, called a texture, before it can be used by a kernel. Several distinct texture references might be bound to the same texture or to textures that overlap in memory. A texture reference has several attributes. One of them is its dimensionality that specifies whether the texture is addressed as a one-dimensional array using one texture coordinate, a two-dimensional array using two texture coordinates, or a threedimensional array using three texture coordinates. Elements of the array are called texels, short for “texture elements.” Other attributes define the input and output data types of the texture fetch, as well as how the input coordinates are interpreted and what processing should be done. A texture can be any region of linear memory or a CUDA array (described in Section 3.2.4.3). Section G.1 lists the maximum texture width, height, and depth depending on the compute capability of the device.

CUDA C Programming Guide Version 3.2

29

Chapter 3. Programming Interface

3.2.4.1.1

Texture Reference Declaration
Some of the attributes of a texture reference are immutable and must be known at compile time; they are specified when declaring the texture reference. A texture reference is declared at file scope as a variable of type texture:
texture<Type, Dim, ReadMode> texRef;

where:

Type specifies the type of data that is returned when fetching the texture; Type

is restricted to the basic integer and single-precision floating-point types and any of the 1-, 2-, and 4-component vector types defined in Section B.3.1;  Dim specifies the dimensionality of the texture reference and is equal to 1, 2, or 3; Dim is an optional argument which defaults to 1;  ReadMode is equal to cudaReadModeNormalizedFloat or cudaReadModeElementType; if it is cudaReadModeNormalizedFloat and Type is a 16-bit or 8-bit integer type, the value is actually returned as floating-point type and the full range of the integer type is mapped to [0.0, 1.0] for unsigned integer type and [-1.0, 1.0] for signed integer type; for example, an unsigned 8-bit texture element with the value 0xff reads as 1; if it is cudaReadModeElementType, no conversion is performed; ReadMode is an optional argument which defaults to cudaReadModeElementType. A texture reference can only be declared as a static global variable and cannot be passed as an argument to a function.

3.2.4.1.2

Runtime Texture Reference Attributes
The other attributes of a texture reference are mutable and can be changed at runtime through the host runtime. They specify whether texture coordinates are normalized or not, the addressing mode, and texture filtering, as detailed below. By default, textures are referenced using floating-point coordinates in the range [0, N) where N is the size of the texture in the dimension corresponding to the coordinate. For example, a texture that is 6432 in size will be referenced with coordinates in the range [0, 63] and [0, 31] for the x and y dimensions, respectively. Normalized texture coordinates cause the coordinates to be specified in the range [0.0, 1.0) instead of [0, N), so the same 6432 texture would be addressed by normalized coordinates in the range [0, 1) in both the x and y dimensions. Normalized texture coordinates are a natural fit to some applications‟ requirements, if it is preferable for the texture coordinates to be independent of the texture size. The addressing mode defines what happens when texture coordinates are out of range. When using unnormalized texture coordinates, texture coordinates outside the range [0, N) are clamped: Values below 0 are set to 0 and values greater or equal to N are set to N-1. Clamping is also the default addressing mode when using normalized texture coordinates: Values below 0.0 or above 1.0 are clamped to the range [0.0, 1.0). For normalized coordinates, the “wrap” addressing mode also may be specified. Wrap addressing is usually used when the texture contains a periodic signal. It uses only the fractional part of the texture coordinate; for example, 1.25 is treated the same as 0.25 and -1.25 is treated the same as 0.75. Linear texture filtering may be done only for textures that are configured to return floating-point data. It performs low-precision interpolation between neighboring texels. When enabled, the texels surrounding a texture fetch location are read and

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the return value of the texture fetch is interpolated based on where the texture coordinates fell between the texels. Simple linear interpolation is performed for onedimensional textures and bilinear interpolation is performed for two-dimensional textures. Appendix F gives more details on texture fetching.

3.2.4.1.3

Texture Binding
As explained in the reference manual, the runtime API has a low-level C-style interface and a high-level C++-style interface. The texture type is defined in the high-level API as a structure publicly derived from the textureReference type defined in the low-level API as such:
struct textureReference { int enum cudaTextureFilterMode enum cudaTextureAddressMode struct cudaChannelFormatDesc }  normalized; filterMode; addressMode[3]; channelDesc;

normalized specifies whether texture coordinates are normalized or not; if it

is non-zero, all elements in the texture are addressed with texture coordinates in the range [0,1] rather than in the range [0,width-1], [0,height-1], or [0,depth-1] where width, height, and depth are the texture sizes;  filterMode specifies the filtering mode, that is how the value returned when fetching the texture is computed based on the input texture coordinates; filterMode is equal to cudaFilterModePoint or cudaFilterModeLinear; if it is cudaFilterModePoint, the returned value is the texel whose texture coordinates are the closest to the input texture coordinates; if it is cudaFilterModeLinear, the returned value is the linear interpolation of the two (for a one-dimensional texture), four (for a two-dimensional texture), or eight (for a three-dimensional texture) texels whose texture coordinates are the closest to the input texture coordinates; cudaFilterModeLinear is only valid for returned values of floating-point type;  addressMode specifies the addressing mode, that is how out-of-range texture coordinates are handled; addressMode is an array of size three whose first, second, and third elements specify the addressing mode for the first, second, and third texture coordinates, respectively; the addressing mode is equal to either cudaAddressModeClamp, in which case out-of-range texture coordinates are clamped to the valid range, or cudaAddressModeWrap, in which case out-of-range texture coordinates are wrapped to the valid range; cudaAddressModeWrap is only supported for normalized texture coordinates;  channelDesc describes the format of the value that is returned when fetching the texture; channelDesc is of the following type:
struct cudaChannelFormatDesc { int x, y, z, w; enum cudaChannelFormatKind f; };

where x, y, z, and w are equal to the number of bits of each component of the returned value and f is:

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textureReference* texRefPtr. cudaReadModeElementType> texRef. Before a kernel can use a texture reference to read from texture memory. 2. cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc<float>(). height. cudaBindTexture2D(0. The following code sample applies some simple transformation kernel to a // 2D float texture texture<float. texRefPtr. 2. cudaReadModeElementType> texRef. textureReference* texRefPtr. devPtr. the results of texture fetches are undefined. cudaUnbindTexture() is used to unbind a texture reference. &channelDesc. the texture reference must be bound to a texture using cudaBindTexture() or cudaBindTextureToArray(). cudaReadModeElementType> texRef. cudaReadModeElementType> texRef. otherwise. cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc<float>(). cudaBindTextureToArray(texRef. &channelDesc). 2. cuArray). devPtr. “texRef”). float theta) { 32 CUDA C Programming Guide Version 3. “texRef”). cudaBindTexture2D(0. cuArray). width. The following code samples bind a texture reference to linear memory pointed to by devPtr:  Using the low-level API: texture<float. cudaChannelFormatDesc channelDesc. addressMode.  Using the high-level API: texture<float. cuArray. texRef. pitch).  cudaChannelFormatKindFloat if they are of floating point type. // Simple transformation kernel __global__ void transformKernel(float* output.Chapter 3. and filterMode may be directly modified in host code. height. Programming Interface  cudaChannelFormatKindSigned if these components are of signed integer type. int width. cudaGetChannelDesc(&channelDesc. width. int height. normalized. cudaGetTextureReference(&texRefPtr. pitch). cudaGetTextureReference(&texRefPtr.  cudaChannelFormatKindUnsigned if they are of unsigned integer type.  Using the high-level API: texture<float. 2. The following code samples bind a texture reference to a CUDA array cuArray:  Using the low-level API: texture<float. &channelDesc. cudaBindTextureToArray(texRef.2 . The format specified when binding a texture to a texture reference must match the parameters specified when declaring the texture reference. 2. cudaReadModeElementType> texRef.

} CUDA C Programming Guide Version 3. v -= 0. float u = x / (float)width. texRef. (height + dimBlock. width. 0. 0. // Free device memory cudaFreeArray(cuArray).x. cudaMemcpyHostToDevice).5f. float tu = u * cosf(theta) – v * sinf(theta) + 0. height). float v = y / (float)height. channelDesc). // Bind the array to the texture reference cudaBindTextureToArray(texRef. cudaFree(output).addressMode[1] = cudaAddressModeWrap. 0. dim3 dimGrid((width + dimBlock. width * height * sizeof(float)). cuArray. // Read from texture and write to global memory output[y * width + x] = tex2D(texRef. } // Host code int main() { // Allocate CUDA array in device memory cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc(32. tu.2 33 . // Allocate result of transformation in device memory float* output. cudaMalloc(&output.filterMode = cudaFilterModeLinear. tv). width.y * blockDim. // Set texture parameters texRef.addressMode[0] = cudaAddressModeWrap. texRef. unsigned int y = blockIdx. // Transform coordinates u -= 0. cudaChannelFormatKindFloat). 16).y + threadIdx.x * blockDim.x. cudaMallocArray(&cuArray.y). height. float tv = v * cosf(theta) + u * sinf(theta) + 0. // Copy to device memory some data located at address h_data // in host memory cudaMemcpyToArray(cuArray. Programming Interface // Calculate normalized texture coordinates unsigned int x = blockIdx. h_data.Chapter 3. // Invoke kernel dim3 dimBlock(16.5f.y.5f. 0.x – 1) / dimBlock. size.x + threadIdx. transformKernel<<<dimGrid.y – 1) / dimBlock. dimBlock>>>(output.5f. angle).normalized = true. 0. texRef. cudaArray* cuArray. &channelDesc.

cuArray). can be read and written via a surface reference using the functions described in Section B. created with the cudaArraySurfaceLoadStore flag. cudaGetSurfaceReference(&surfRefPtr. otherwise. 3. cudaBindSurfaceToArray(surfRef. for example.2 Surface Binding Before a kernel can use a surface reference to access a CUDA array.4. 3. the surface reference must be bound to the CUDA array using cudaBindSurfaceToArray().2 . A channel description for the 16-bit floating-point format can be created by calling one of the cudaCreateChannelDescHalf*() functions. 16-bit floating-point components are promoted to 32 bit float during texture fetching before any filtering is performed. and depth depending on the compute capability of the device. These functions are only supported in device code. cudaGetChannelDesc(&channelDesc. Programming Interface 3.4. cudaChannelFormatDesc channelDesc.4.2.1.Chapter 3.2. but provides intrinsic functions to convert to and from the 32-bit floating-point format via the unsigned short type: __float2half(float) and __half2float(unsigned short).9. the results of reading and writing the CUDA array are undefined. 2> surfRef.2.2. height. cudaBindSurfaceToArray(surfRef. 3.2.1 lists the maximum surface width. Dim> surfRef.  Using the high-level API: surface<void.2 Surface Memory A CUDA array (described in Section 3. surfaceReference* surfRefPtr.3). A surface reference can only be declared as a static global variable and cannot be passed as an argument to a function. &channelDesc). “surfRef”).2. cuArray. The following code samples bind a surface reference to a CUDA array cuArray:  Using the low-level API: surface<void.1 Surface Reference Declaration A surface reference is declared at file scope as a variable of type surface: surface<void.4 16-Bit Floating-Point Textures The 16-bit floating-point or half format supported by CUDA arrays is the same as the IEEE 754-2008 binary2 format. where Dim specifies the dimensionality of the surface reference and is equal to 1 or 2. cuArray). 34 CUDA C Programming Guide Version 3. Dim is an optional argument which defaults to 1. CUDA C does not support a matching data type. Equivalent functions for the host code can be found in the OpenEXR library. 2> surfRef. Section G.4. A CUDA array must be read and written using surface functions of matching dimensionality and type and via a surface reference of matching dimensionality.2.4.

but surf2Dread(surfRef. } } // Host code int main() { // Allocate CUDA arrays in device memory cudaChannelFormatDesc channelDesc = cudaCreateChannelDesc(8. &channelDesc. the element at texture coordinate x of a one-dimensional floating-point CUDA array bound to a texture reference texRef and a surface reference surfRef is read using tex1d(texRef. x * 4. &channelDesc. cudaArray* cuOutputArray. y).2 35 . 4*x) via surfRef. The following code sample applies some simple transformation kernel to a // 2D surfaces surface<void. but surf1Dread(surfRef. width. cudaArraySurfaceLoadStore).x. cudaMallocArray(&cuInputArray. int height) { // Calculate surface coordinates unsigned int x = blockIdx. 0. For example. cudaChannelFormatKindUnsigned). 4*x. if (x < width && y < height) { uchar4 data. unsigned int y = blockIdx. y) via surfRef (the byte offset of the y-coordinate is internally calculated from the underlying line pitch of the CUDA array).y. // Write to output surface surf2Dwrite(data. cuInputArray).y * blockDim. y). // Read from input surface surf2Dread(&data. 8. x. 2> outputSurfRef. cudaArray* cuInputArray. y) via texRef. width. cudaMallocArray(&cuOutputArray.x + threadIdx. // Copy to device memory some data located at address h_data // in host memory cudaMemcpyToArray(cuInputArray. surface memory uses byte addressing. cuOutputArray). size. Similarly.y + threadIdx. cudaArraySurfaceLoadStore). the element at texture coordinate x and y of a two-dimensional floating-point CUDA array bound to a texture reference texRef and a surface reference surfRef is accessed using tex2d(texRef. // Bind the arrays to the surface references cudaBindSurfaceToArray(inputSurfRef. 8. height. x) via texRef. inputSurfRef. height. // Simple copy kernel __global__ void copyKernel(int width. Programming Interface Unlike texture memory.x * blockDim. cudaMemcpyHostToDevice). This means that the x-coordinate used to access a texture element via texture functions needs to be multiplied by the byte size of the element to access the same element via a surface function. 2> inputSurfRef. x * 4. 8. outputSurfRef.Chapter 3. h_data. cudaBindSurfaceToArray(outputSurfRef. surface<void. CUDA C Programming Guide Version 3. 0.

Programming Interface // Invoke kernel dim3 dimBlock(16. dimBlock>>>(width.y – 1) / dimBlock.5.x. eliminating the need to copy it to or from device memory as detailed in Section 3.4. or 32-bit floats.  On some devices.or 32-bit integers. } 3. // Free device memory cudaFreeArray(cuInputArray).3. 16). dim3 dimGrid((width + dimBlock. They are one-dimensional.y).2.2.2.2. by reducing the amount of physical memory available to the operating  36 CUDA C Programming Guide Version 3.x – 1) / dimBlock.5) and within the same kernel call.3 CUDA Arrays CUDA arrays are opaque memory layouts optimized for texture fetching. a thread can safely read some texture or surface memory location only if this memory location has been updated by a previous kernel call or memory copy. 3.4 Read/Write Coherency The texture and surface memory is cached (see Section 5. bandwidth between host memory and device memory is higher if host memory is allocated as page-locked and even higher if in addition it is allocated as write-combining as described in Section 3. Using page-locked host memory has several benefits: Copies between page-locked host memory and device memory can be performed concurrently with kernel execution for some devices as mentioned in Section 3.5. 3. 16.6. or three-dimensional and composed of elements. so any texture fetch or surface read to an address that has been written to via a global write or a surface write in the same kernel call returns undefined data. the cache is not kept coherent with respect to global memory writes and surface memory writes. copyKernel<<<dimGrid. In addition. cudaFreeArray(cuOutputArray).2. page-locked host memory can be mapped into the address space of the device.3.  On systems with a front-side bus. height). so allocations in pagelocked memory will start failing long before allocations in pageable memory. CUDA arrays are only readable by kernels through texture fetching and may only be bound to texture references with the same number of packed components. In other words. two-dimensional.2. 2 or 4 components that may be signed or unsigned 8-.2.2. each of which has 1.5 Page-Locked Host Memory The runtime also provides functions to allocate and free page-locked (also known as pinned) host memory – as opposed to regular pageable host memory allocated by malloc(): cudaHostAlloc() and cudaFreeHost(). but not if it has been previously updated by the same thread or another thread from the same kernel call.Chapter 3.2 . (height + dimBlock.4. Page-locked host memory is a scarce resource however. 16-bit floats.

3. Reading from write-combining memory from the host is prohibitively slow. Write-combining memory frees up L1 and L2 cache resources. or write-afterwrite hazards.1 Portable Memory A block of page-locked memory can be used by any host threads.5. it needs to be allocated by passing flag cudaHostAllocPortable to cudaHostAlloc(). making more cache available to the rest of the application.2. To make these advantages available to all threads.0.5. In addition. 3. in which case each host thread that needs to map the block to its device address space must call cudaHostGetDevicePointer() to retrieve a device pointer. but by default.2.1).2.2.  A block of page-locked host memory can be allocated as both mapped and portable (see Section 3. which can improve transfer performance by up to 40%.5.2. 3.2 Write-Combining Memory By default page-locked host memory is allocated as cacheable.6) to avoid any potential read-after-write. Since mapped page-locked memory is shared between host and device however. as device pointers will generally differ from one host thread to the other. CUDA C Programming Guide Version 3. The host memory pointer is returned by cudaHostAlloc() and the device memory pointer can be retrieved using cudaHostGetDevicePointer()and then used to access the block from within a kernel. the application must synchronize memory accesses using streams or events (see Section 3.  There is no need to use streams (see Section 3. a block of page-locked host memory can also be mapped into the address space of the device by passing flag cudaHostAllocMapped to cudaHostAlloc(). The simple zero-copy SDK sample comes with a detailed document on the pagelocked memory APIs. Such a block has therefore two addresses: one in host memory and one in device memory.4) to overlap data transfers with kernel execution. the kernel-originated data transfers automatically overlap with kernel execution.2 37 . data transfers are implicitly performed as needed by the kernel.5. Accessing host memory directly from within a kernel has several advantages: There is no need to allocate a block in device memory and copy data between this block and the block in host memory. Programming Interface system for paging. so write-combining memory should in general be used for memory that the host only writes to. allocating too much page-locked memory reduces overall system performance.6. It can optionally be allocated as write-combining instead by passing flag cudaHostAllocWriteCombined to cudaHostAlloc(). write-combining memory is not snooped during transfers across the PCI Express bus.3 Mapped Memory On devices of compute capability greater than 1. write-after-read.2. the benefits of using page-locked memory described above are only available for the thread that allocates it.Chapter 3.

cudaHostGetDevicePointer() will return an error. When an application is run via a CUDA debugger or profiler (cuda-gdb. some function calls are asynchronous: Control is returned to the host thread before the device has completed the requested task. Applications may query this capability by calling cudaGetDeviceProperties() and checking the deviceOverlap property.x can execute multiple kernels concurrently. all launches are synchronous.2. page-locked memory mapping must be enabled by calling cudaSetDeviceFlags() with the cudaDeviceMapHost flag before any other CUDA calls is performed by the thread.  Memory copies performed by functions that are suffixed with Async. Device  device memory copies. 3.11) operating on mapped page-locked memory are not atomic from the point of view of the host or other devices.1 Asynchronous Concurrent Execution Concurrent Execution between Host and Device In order to facilitate concurrent execution between host and device. These are:    Kernel launches.2 38 . 3. Programmers can globally disable asynchronous kernel launches for all CUDA applications running on a system by setting the CUDA_LAUNCH_BLOCKING environment variable to 1. The maximum number of kernel launches that a device can execute concurrently is sixteen.6.6. Note that atomic functions (Section B. Applications may query this capability by calling cudaGetDeviceProperties() and checking the concurrentKernels property.2 Overlap of Data Transfer and Kernel Execution Some devices of compute capability 1. This feature is provided for debugging purposes only and should never be used as a way to make production software run reliably.6. CUDA Visual Profiler.Chapter 3.2. Parallel Nsight). cudaHostGetDevicePointer() also returns an error if the device does not support mapped page-locked host memory.1 and higher can perform copies between page-locked host memory and device memory concurrently with kernel execution. Programming Interface To be able to retrieve the device pointer to any mapped page-locked memory within a given host thread. CUDA C Programming Guide Version 3. Host  device memory copies of a memory block of 64 KB or less.2. 3.3 Concurrent Kernel Execution Some devices of compute capability 2.2.2. This capability is currently supported only for memory copies that do not involve CUDA arrays or 2D arrays allocated through cudaMallocPitch() (see Section 3.6 3.1). Otherwise. Applications may query whether a device supports mapped page-locked host memory or not by calling cudaGetDeviceProperties() and checking the canMapHostMemory property.  Memory set function calls.

0. and one memory copy from device to host: for (int i = 0. CUDA C Programming Guide Version 3. cudaStream_t stream[2].6.4 describes how the streams overlap in this example depending on the capability of the device. on the other hand.5. hostPtr + i * size.1 Creation and Destruction A stream is defined by creating a stream object and specifying it as the stream parameter to a sequence of kernel launches and host  device memory copies.5. cudaMemcpyHostToDevice. stream[i]>>> (outputDevPtr + i * size. Each of these streams is defined by the following code sample as a sequence of one memory copy from host to device.6. size).2. size. size. i < 2.2. inter-kernel communication is undefined). Note that hostPtr must point to page-locked host memory for any overlap to occur. MyKernel<<<100. A stream is a sequence of commands that execute in order.g. i < 2. cudaStreamDestroy() waits for all preceding commands in the given stream to complete before destroying the stream and returning control to the host thread. outputDevPtr + i * size. stream[i]).Chapter 3. stream[i]). and copies the result outputDevPtr back to the same portion of hostPtr.x can perform a copy from page-locked host memory to device memory concurrently with a copy from device memory to pagelocked host memory. may execute their commands out of order with respect to one another or concurrently. for (int i = 0.2. 2 * size).5 Stream Applications manage concurrency through streams. ++i) cudaStreamCreate(&stream[i]). cudaMemcpyAsync(hostPtr + i * size. one kernel launch. 512. Kernels that use many textures or a large amount of local memory are less likely to execute concurrently with other kernels. 3. Programming Interface A kernel from one CUDA context cannot execute concurrently with a kernel from another CUDA context. float* hostPtr. this behavior is not guaranteed and should therefore not be relied upon for correctness (e.2. inputDevPtr + i * size. 3. cudaMallocHost(&hostPtr. ++i) cudaStreamDestroy(stream[i]). } Each stream copies its portion of input array hostPtr to array inputDevPtr in device memory. Different streams.2 39 . ++i) { cudaMemcpyAsync(inputDevPtr + i * size.6.4 Concurrent Data Transfers Some devices of compute capability 2. The following code sample creates two streams and allocates an array hostPtr of float in page-locked memory. for (int i = 0. Section 3. i < 2. Streams are released by calling cudaStreamDestroy(). cudaMemcpyDeviceToHost. 3. processes inputDevPtr on the device by calling MyKernel().6.

6. any operation that requires a dependency check to see if a streamed kernel launch is complete: Can start executing only when all thread blocks of all prior kernel launches from any stream in the CUDA context have started executing. Synchronization of any kind should be delayed as long as possible.  a device memory allocation. For devices that support concurrent kernel execution.  a switch between the L1/shared memory configurations described in Section G. allowing other streams to continue executing on the device.3 Implicit Synchronization Two commands from different streams cannot run concurrently if either one of the following operations is issued in-between them by the host thread: a page-locked host memory allocation. all these synchronization functions are usually best used for timing purposes or to isolate a launch or memory copy that is failing.6.6 for a description of events) and makes all the commands added to the given stream after the call to cudaStreamWaitEvent() delay their execution until the given event has completed.5. It can be used to synchronize the host with a specific stream. any CUDA command to stream 0 (including kernel launches and host  device memory copies that do not specify any stream parameter).  Blocks all later kernel launches from any stream in the CUDA context until the kernel launch being checked is complete. Programming Interface 3.2 .    a device  device memory copy. The stream can be 0.2. in which case all the commands added to any stream after the call to cudaStreamWaitEvent() wait on the event.2 Explicit Synchronization There are various ways to explicitly synchronize streams with each other. cudaStreamWaitEvent() cudaStreamQuery() provides applications with a way to know if all preceding commands in a stream have completed. cudaThreadSynchronize() completed.1. Therefore. 3.Chapter 3. 40 CUDA C Programming Guide Version 3.  a device memory set.2. Operations that require a dependency check include any other commands within the same stream as the launch being checked and any call to cudaStreamQuery() on that stream.2. applications should follow these guidelines to improve their potential for concurrent kernel execution:    All independent operations should be issued before dependent operations. takes a stream and an event as parameters (see Section 3. cudaStreamSynchronize() waits until all preceding commands in all streams have takes a stream as a parameter and waits until all preceding commands in the given stream have completed.6.5. To avoid unnecessary slowdowns.4.

6. as well as perform accurate timing. hostPtr + i * size.5. 3. i < 2. ++i) cudaMemcpyAsync(inputDevPtr + i * size. and/or concurrent data transfers (Section 3. CUDA C Programming Guide Version 3. concurrent kernel execution (Section 3. the two streams of the code sample of Section 3. size. Programming Interface 3. i < 2.6.1 do overlap: The memory copy from host to device issued to stream 1 overlaps with the memory copy from device to host issued to stream 0 and even with the kernel launch issued to stream 0 (assuming the device supports overlap of data transfer and kernel execution). then the memory copy from host to device issued to stream 1 overlaps with the kernel launch issued to stream 0. On devices that do support concurrent data transfers.6.2. An event has completed when all tasks – or optionally.6.6. 0. stream[i]>>> (outputDevPtr + i * size. However. the memory copy from device to host issued to stream 0 only overlaps with the last thread blocks of the kernel launch issued to stream 1 as per Section 3.2.5.2.3. for (int i = 0. the kernel executions cannot possibly overlap because the kernel launch is issued to stream 1 after the memory copy from device to host is issued to stream 0. For example. by letting the application asynchronously record events at any point in the program and query when these events are completed.4). the two streams of the code sample of Section 3. inputDevPtr + i * size. on devices that do not support concurrent data transfers.6.3). The following code sample creates two events: cudaEvent_t start.2 41 .5. In that case however.6. stream[i]). all commands in a given stream – preceding the event have completed.2. If the code is rewritten the following way (and assuming the device supports overlap of data transfer and kernel execution) for (int i = 0. outputDevPtr + i * size. i < 2.Chapter 3.5. ++i) MyKernel<<<100. which can represent a small portion of the total execution time of the kernel.5.2. size.1 do not overlap at all because the memory copy from host to device is issued to stream 1 after the memory copy from device to host is issued to stream 0. the kernel executions overlap (assuming the device supports concurrent kernel execution) since the kernel launch is issued to stream 1 before the memory copy from device to host is issued to stream 0.2.6 Event The runtime also provides a way to closely monitor the device‟s progress. Events in stream zero are completed after all preceding task and commands in all streams are completed. ++i) cudaMemcpyAsync(hostPtr + i * size.6. If the code is rewritten as above. cudaEventCreate(&stop). cudaMemcpyHostToDevice. stop. for (int i = 0.2. stream[i]).3.4 Overlapping Behavior The amount of execution overlap between two streams depends on the order in which the commands are issued to each stream and whether or not the device supports overlap of data transfer and kernel execution (Section 3.6. size). 512.2. cudaMemcpyDeviceToHost.2.2). cudaEventCreate(&start). so it is blocked until the kernel launch issued to stream 0 is complete as per Section 3.

size.2.2. or spin can be specified by calling cudaSetDeviceFlags()with some specific flags (see reference manual for details) before any other CUDA calls is performed by the host thread. start.7. either to enable CUDA to read data written by OpenGL or Direct3D.6. 0). inputHost + i * size. Registering a resource is potentially high-overhead and therefore typically called only once per resource.2. 42 CUDA C Programming Guide Version 3. 512. cudaMemcpyHostToDevice.Chapter 3. cudaMemcpyDeviceToHost.2 . cudaEventDestroy(stop). A mapped resource can be read from or written to by kernels using the device memory address returned by cudaGraphicsResourceGetMappedPointer() for buffers and cudaGraphicsSubResourceGetMappedArray() for CUDA arrays. read-only) that the CUDA driver can use to optimize resource management. i < 2. Programming Interface These events can be used to time the code sample of the previous section the following way: cudaEventRecord(start. cudaMemcpyAsync(outputHost + i * size. 0. Once a resource is registered to CUDA. stop). inputDev + i * size. float elapsedTime. They are destroyed this way: cudaEventDestroy(start). 3.7.7 Graphics Interoperability Some resources from OpenGL and Direct3D may be mapped into the address space of CUDA. stream[i]). stream[i]>>> (outputDev + i * size. block. cudaGraphicsResourceSetMapFlags() can be called to specify usage hints (write-only. it can be mapped and unmapped as many times as necessary using cudaGraphicsMapResources() and cudaGraphicsUnmapResources().1 and 3. cudaEventElapsedTime(&elapsedTime.2. Whether the host thread will then yield. A resource must be registered to CUDA before it can be mapped using the functions mentioned in Sections 3. control is not returned to the host thread before the device has completed the requested task. } cudaEventRecord(stop. MyKernel<<<100. size). A CUDA graphics resource is unregistered using cudaGraphicsUnregisterResource().7 Synchronous Calls When a synchronous function is called. cudaEventSynchronize(stop). size. or to enable CUDA to write data for consumption by OpenGL or Direct3D. These functions return a pointer to a CUDA graphics resource of type struct cudaGraphicsResource. stream[i]). 0). outputDev + i * size. for (int i = 0. ++i) { cudaMemcpyAsync(inputDev + i * size. 3.2.

A texture or renderbuffer object is registered using cudaGraphicsGLRegisterImage().g. GL_DYNAMIC_DRAW). The following code sample uses a kernel to dynamically modify a 2D width x height grid of vertices stored in a vertex buffer object: GLuint positionsVBO. cudaGraphicsGLRegisterBuffer(&positionsVBO_CUDA. Please note that since GL_RGBA8UI is an OpenGL 3. In CUDA.0 texture format. Note that cudaSetDevice()and cudaGLSetGLDevice() are mutually exclusive. GL_RGBA8). 0). glBufferData(GL_ARRAY_BUFFER. &vbo).7. glBindBuffer(GL_ARRAY_BUFFER. or 4 components and an internal type of float (e..7. The OpenGL resources that may be mapped into the address space of CUDA are OpenGL buffer. 2.2 43 .2. it can only be written by shaders.2 give specifics for each graphics API and some code samples. size. unsigned int size = width * height * 4 * sizeof(float). // Initialize OpenGL and GLUT . Sections 3. texture. GL_RGBA8UI).g. positionsVBO.Chapter 3. it appears as a CUDA array and can therefore be bound to a texture reference and be read and written by kernels or via cudaMemcpy2D() calls.. It does not currently support normalized integer formats (e. A buffer object is registered using cudaGraphicsGLRegisterBuffer().2. not the fixed function pipeline. struct cudaGraphicsResource* positionsVBO_CUDA.g. Programming Interface Accessing a resource through OpenGL or Direct3D while it is mapped to CUDA produces undefined results. GL_RGBA_FLOAT32) and unnormalized integer (e. cudaGraphicsMapFlagsWriteDiscard). In CUDA.1 OpenGL Interoperability Interoperability with OpenGL requires that the CUDA device be specified by cudaGLSetGLDevice() before any other runtime calls. positionsVBO). it appears as a device pointer and can therefore be read and written by kernels or via cudaMemcpy() calls.2. } CUDA C Programming Guide Version 3. glBindBuffer(GL_ARRAY_BUFFER. 0. and renderbuffer objects. cudaGraphicsGLRegisterImage() supports all texture formats with 1. // Launch rendering loop glutMainLoop(). 3. glutDisplayFunc(display).1 and 3.7. // Create buffer object and register it with CUDA glGenBuffers(1. int main() { // Explicitly set device cudaGLSetGLDevice(0).

} void deleteVBO() { cudaGraphicsUnregisterResource(positionsVBO_CUDA). // Write positions positions[y * width + x] = make_float4(u. GL_FLOAT. 0). // Unmap buffer object cudaGraphicsUnmapResources(1.2 . 1).x. float time.1. // Swap buffers glutSwapBuffers(). // calculate simple sine wave pattern float freq = 4. 0). &num_bytes. w. // Render from buffer object glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT). 0. width. v = v * 2. 1). size_t num_bytes. cudaGraphicsResourceGetMappedPointer((void**)&positions. glEnableClientState(GL_VERTEX_ARRAY).0f. glDisableClientState(GL_VERTEX_ARRAY). cudaGraphicsMapResources(1.x + threadIdx. Programming Interface void display() { // Map buffer object for writing from CUDA float4* positions.0f . v. &positionsVBO_CUDA. &positionsVBO_CUDA.0f. time. 0.y + threadIdx. height / dimBlock. 1.y * blockDim. createVertices<<<dimGrid. glutPostRedisplay(). unsigned int width. &positionsVBO). } __global__ void createVertices(float4* positions. 16.y. 0). glBindBuffer(GL_ARRAY_BUFFER. positionsVBO). float w = sinf(u * freq + time) * cosf(v * freq + time) * 0. positionsVBO_CUDA)). dimBlock>>>(positions.x. unsigned int height) { unsigned int x = blockIdx. unsigned int y = blockIdx.0f.0f). dim3 dimGrid(width / dimBlock. u = u * 2. height). glDrawArrays(GL_POINTS.0f .1. glVertexPointer(4. // Calculate uv coordinates float u = x / (float)width. glDeleteBuffers(1.Chapter 3.5f.y.x * blockDim. // Execute kernel dim3 dimBlock(16. width * height). 44 CUDA C Programming Guide Version 3. float v = y / (float)height.

each using a different CUDA context. before any other runtime calls. and cudaD3D11GetDevice() can be used to retrieve the CUDA device associated to some adapter. textures.2 Direct3D Interoperability Direct3D interoperability is supported for Direct3D 9.2 45 . which allows it to call cuCtxPushCurrent() and cuCtxPopCurrent()to change the CUDA context active at a given time.2. A set of calls is also available to allow the creation of CUDA devices with interoperability with Direct3D devices that use NVIDIA SLI in AFR (Alternate Frame Rendering) mode: cudaD3D[9|10|11]GetDevices(). cudaD3D9GetDevice(). and cudaGraphicsD3D11RegisterResource(). 3. cudaD3D10SetDirect3DDevice() and cudaD3D11SetDirect3DDevice(). The application has the choice to either create multiple CPU threads. The Direct3D resources that may be mapped into the address space of CUDA are Direct3D buffers. cudaGraphicsD3D10RegisterResource(). the application relies on the interoperability between CUDA driver and runtime APIs (Section 3. Programming Interface } On Windows and for Quadro GPUs. See Section 4. cudaWGLGetDevice() can be used to retrieve the CUDA device associated to the handle returned by wglEnumGpusNV(). Quadro GPUs offer higher performance OpenGL interoperability than GeForce and Tesla GPUs in a multi-GPU configuration where OpenGL rendering is performed on the Quadro GPU and CUDA computations are performed on other GPUs in the system. The following code sample uses a kernel to dynamically modify a 2D width x height grid of vertices stored in a vertex buffer object. and Direct3D 11. the Direct3D device must be created with the D3DCREATE_HARDWARE_VERTEXPROCESSING flag. CUDA C Programming Guide Version 3. Direct3D 10. A CUDA context may interoperate with only one Direct3D device at a time and the CUDA context and Direct3D device must be created on the same GPU.3 for general recommendations related to interoperability between Direct3D devices using SLI and CUDA contexts. If using a single CPU thread. Moreover. cudaD3D10GetDevice(). A call to cuD3D[9|10|11]GetDevices()can be used to obtain a list of CUDA device handles that can be passed as the (optional) last parameter to cudaD3D[9|10|11]SetDirect3DDevice(). and surfaces. These resources are registered using cudaGraphicsD3D9RegisterResource(). or a single CPU thread using multiple CUDA context. Direct3D 9 Version: IDirect3D9* D3D. Each of these CUDA contexts would be created using one of the CUDA device handles returned by cudaD3D[9|10|11]GetDevices()).Chapter 3.7.4). Interoperability with Direct3D requires that the Direct3D device be specified by cudaD3D9SetDirect3DDevice().

cudaGraphicsMapResources(1. 0). adapter++) { D3DADAPTER_IDENTIFIER9 adapterId.Chapter 3. IDirect3DVertexBuffer9* positionsVB. Render(). // Get a CUDA-enabled adapter unsigned int adapter = 0. cudaGraphicsMapFlagsWriteDiscard). z. 0.. D3D->CreateDevice(adapter. D3DDEVTYPE_HAL. hWnd. 0. adapter < g_pD3D->GetAdapterCount().DeviceName) == cudaSuccess) break.2 . &positionsVB_CUDA. }. } // Create device . 46 CUDA C Programming Guide Version 3.. // Register device with CUDA cudaD3D9SetDirect3DDevice(device). size_t num_bytes. if (cudaD3D9GetDevice(&dev. 0). . Programming Interface IDirect3DDevice9* device.. D3DCREATE_HARDWARE_VERTEXPROCESSING. int dev. // Create vertex buffer and register it with CUDA unsigned int size = width * height * sizeof(CUSTOMVERTEX).) { .. &device).. cudaGraphicsResourceSetMapFlags(positionsVB_CUDA. for (. positionsVB. &adapterId). y. } } void Render() { // Map vertex buffer for writing from CUDA float4* positions.. &positionsVB. D3DFVF_CUSTOMVERTEX. cudaGraphicsD3D9RegisterResource(&positionsVB_CUDA. device->CreateVertexBuffer(size. adapterId. struct cudaGraphicsResource* positionsVB_CUDA. D3DPOOL_DEFAULT. DWORD color. cudaGraphicsRegisterFlagsNone). g_pD3D->GetAdapterIdentifier(adapter. int main() { // Initialize Direct3D D3D = Direct3DCreate9(D3D_SDK_VERSION). &params.. // Launch rendering loop while (. struct CUSTOMVERTEX { FLOAT x..

1). height / dimBlock. &num_bytes. z. positionsVB->Release().x * blockDim. Programming Interface cudaGraphicsResourceGetMappedPointer((void**)&positions.1. // Unmap vertex buffer cudaGraphicsUnmapResources(1. ID3D10Buffer* positionsVB.0f. // Draw and present .0f.0f. // Calculate simple sine wave pattern float freq = 4. } __global__ void createVertices(float4* positions. w. }. unsigned int height) { unsigned int x = blockIdx.x. struct CUSTOMVERTEX { FLOAT x. &positionsVB_CUDA. int main() { // Get a CUDA-enabled adapter CUDA C Programming Guide Version 3. // Execute kernel dim3 dimBlock(16.5f. height).x + threadIdx.1. v = v * 2. time. 1). dim3 dimGrid(width / dimBlock.0f . width. u = u * 2.. __int_as_float(0xff00ff00)).x. // Write positions positions[y * width + x] = make_float4(u. } Direct3D 10 Version: ID3D10Device* device. 16.y. } void releaseVB() { cudaGraphicsUnregisterResource(positionsVB_CUDA). createVertices<<<dimGrid.y + threadIdx. float v = y / (float)height. unsigned int width. dimBlock>>>(positions. unsigned int y = blockIdx. positionsVB_CUDA))..2 47 .y. v. struct cudaGraphicsResource* positionsVB_CUDA. y.y * blockDim. 0). float w = sinf(u * freq + time) * cosf(v * freq + time) * 0.Chapter 3. // Calculate uv coordinates float u = x / (float)width. float time.0f . DWORD color.

) { . !adapter. size_t num_bytes..Usage = D3D10_USAGE_DEFAULT. . cudaGraphicsResourceGetMappedPointer((void**)&positions.CPUAccessFlags = 0. &positionsVB). D3D10CreateDeviceAndSwapChain(adapter. // Create vertex buffer and register it with CUDA unsigned int size = width * height * sizeof(CUSTOMVERTEX).BindFlags = D3D10_BIND_VERTEX_BUFFER. adapter) == cudaSuccess) break. &adapter)) break.Chapter 3. (void**)&factory). Render(). D3D10_DRIVER_TYPE_HARDWARE. positionsVB. Programming Interface IDXGIFactory* factory. &positionsVB_CUDA.. &device). 48 CUDA C Programming Guide Version 3.. 0.. D3D10_CREATE_DEVICE_DEBUG. 0. } } void Render() { // Map vertex buffer for writing from CUDA float4* positions. &swapChainDesc. cudaGraphicsD3D10RegisterResource(&positionsVB_CUDA.. bufferDesc. D3D10_SDK_VERSION. bufferDesc. cudaGraphicsRegisterFlagsNone).. IDXGIAdapter* adapter = 0.MiscFlags = 0. &swapChain. ++i) { if (FAILED(factory->EnumAdapters(i. if (cudaD3D10GetDevice(&dev. } factory->Release(). D3D10_BUFFER_DESC bufferDesc. bufferDesc. device->CreateBuffer(&bufferDesc.ByteWidth = size. cudaGraphicsMapResources(1. cudaGraphicsMapFlagsWriteDiscard).2 . bufferDesc. 0). cudaGraphicsResourceSetMapFlags(positionsVB_CUDA. CreateDXGIFactory(__uuidof(IDXGIFactory). int dev. bufferDesc. // Launch rendering loop while (.. adapter->Release(). adapter->Release(). // Register device with CUDA cudaD3D10SetDirect3DDevice(device). &num_bytes. // Create swap chain and device .. for (unsigned int i = 0.

y. w. height). // Write positions positions[y * width + x] = make_float4(u. time. unsigned int y = blockIdx. unsigned int height) { unsigned int x = blockIdx. createVertices<<<dimGrid. u = u * 2.2 49 .x. CreateDXGIFactory(__uuidof(IDXGIFactory).. } __global__ void createVertices(float4* positions.0f. float v = y / (float)height.5f.x + threadIdx. // Execute kernel dim3 dimBlock(16. positionsVB->Release().x.0f .y * blockDim. struct CUSTOMVERTEX { FLOAT x. // Draw and present . Programming Interface positionsVB_CUDA)). z..x * blockDim.0f. float w = sinf(u * freq + time) * cosf(v * freq + time) * 0.y + threadIdx.0f. width.0f . CUDA C Programming Guide Version 3. float time. // Calculate uv coordinates float u = x / (float)width. height / dimBlock. // Unmap vertex buffer cudaGraphicsUnmapResources(1.Chapter 3. (void**)&factory). v = v * 2. 1). v. ID3D11Buffer* positionsVB. &positionsVB_CUDA. } void releaseVB() { cudaGraphicsUnregisterResource(positionsVB_CUDA). struct cudaGraphicsResource* positionsVB_CUDA. DWORD color. dimBlock>>>(positions. dim3 dimGrid(width / dimBlock.1. y. // Calculate simple sine wave pattern float freq = 4. unsigned int width.y.1. int main() { // Get a CUDA-enabled adapter IDXGIFactory* factory. 16. }. 0). 1). } Direct3D 11 Version: ID3D11Device* device. __int_as_float(0xff00ff00)).

featureLevels. for (unsigned int i = 0. bufferDesc. 0.. &positionsVB_CUDA. // Create swap chain and device .MiscFlags = 0. bufferDesc. &featureLevel. &adapter)) break. adapter) == cudaSuccess) break. D3D11_CREATE_DEVICE_DEBUG.. cudaGraphicsRegisterFlagsNone). 50 CUDA C Programming Guide Version 3. bufferDesc. &swapChain.2 .. D3D11_DRIVER_TYPE_HARDWARE. cudaGraphicsD3D11RegisterResource(&positionsVB_CUDA.. sFnPtr_D3D11CreateDeviceAndSwapChain(adapter. cudaGraphicsResourceSetMapFlags(positionsVB_CUDA.Chapter 3. D3D11_SDK_VERSION. !adapter. bufferDesc. } factory->Release(). . cudaGraphicsMapFlagsWriteDiscard). adapter->Release(). D3D11_BUFFER_DESC bufferDesc. 0). if (cudaD3D11GetDevice(&dev. bufferDesc. ++i) { if (FAILED(factory->EnumAdapters(i. &positionsVB). Render(). positionsVB. &swapChainDesc..Usage = D3D11_USAGE_DEFAULT. // Launch rendering loop while (. &deviceContext). Programming Interface IDXGIAdapter* adapter = 0. adapter->Release().ByteWidth = size.CPUAccessFlags = 0.BindFlags = D3D11_BIND_VERTEX_BUFFER. 0. 3.. int dev. &device. // Register device with CUDA cudaD3D11SetDirect3DDevice(device).. size_t num_bytes. // Create vertex buffer and register it with CUDA unsigned int size = width * height * sizeof(CUSTOMVERTEX). } } void Render() { // Map vertex buffer for writing from CUDA float4* positions. device->CreateBuffer(&bufferDesc.) { .. cudaGraphicsMapResources(1.

height / dimBlock. __int_as_float(0xff00ff00)).8 Error Handling All runtime functions return an error code. it will be reported by some subsequent unrelated runtime function call. width. createVertices<<<dimGrid. } void releaseVB() { cudaGraphicsUnregisterResource(positionsVB_CUDA). &positionsVB_CUDA. } __global__ void createVertices(float4* positions. dim3 dimGrid(width / dimBlock.x.0f . 0).0f . // Calculate simple sine wave pattern float freq = 4.x * blockDim. float w = sinf(u * freq + time) * cosf(v * freq + time) * 0.5f.2. 1). // Calculate uv coordinates float u = x / (float)width.x. u = u * 2. // Unmap vertex buffer cudaGraphicsUnmapResources(1.y. CUDA C Programming Guide Version 3. if an asynchronous error occurs. but for an asynchronous function (see Section 3.1. // Execute kernel dim3 dimBlock(16. 16.6).y. this error code cannot possibly report any of the asynchronous errors that could occur on the device since the function returns before the device has completed the task. time. positionsVB_CUDA)). typically related to parameter validation. Programming Interface cudaGraphicsResourceGetMappedPointer((void**)&positions.0f. w. unsigned int height) { unsigned int x = blockIdx. the error code only reports errors that occur on the host prior to executing the task. &num_bytes. float time. height).2. float v = y / (float)height. unsigned int y = blockIdx. // Write positions positions[y * width + x] = make_float4(u. 1). v = v * 2.0f.Chapter 3. } 3. unsigned int width.y * blockDim.. // Draw and present .x + threadIdx.1. v.y + threadIdx. positionsVB->Release(). dimBlock>>>(positions.0f.2 51 ..

The objects available in the driver API are summarized in Table 3-1.9 Call Stack On devices of compute capability 2. 3. otherwise. one has to make sure that the runtime error variable is set to cudaSuccess just before the kernel launch.2. Kernel launches are asynchronous. The runtime maintains an error variable for each host thread that is initialized to cudaSuccess and is overwritten by the error code every time an error occurs (be it a parameter validation error or an asynchronous error). 3. the size of the call stack can be queried using cudaThreadGetLimit() and set using cudaThreadSetLimit(). Parallel Nsight) or an unspecified launch error.6) and checking the error code returned by cudaThreadSynchronize(). cudaPeekAtLastError() returns this variable. by calling cudaGetLastError() just before the kernel launch. Table 3-1. cudaGetLastError() returns this variable and resets it to cudaSuccess. so to check for asynchronous errors. Note that cudaErrorNotReady that may be returned by cudaStreamQuery() and cudaEventQuery() is not considered an error and is therefore not reported by cudaPeekAtLastError() or cudaGetLastError(). Objects Available in the CUDA Driver API Object Device Context Module Function Handle CUdevice CUcontext CUmodule CUfunction Description CUDA-enabled device Roughly equivalent to a CPU process Roughly equivalent to a dynamic library Kernel 52 CUDA C Programming Guide Version 3. Programming Interface The only way to check for asynchronous errors just after some asynchronous function call is therefore to synchronize just after the call by calling cudaThreadSynchronize() (or by using any other synchronization mechanisms described in Section 3. When the call stack overflows. for example.3 Driver API The driver API is a handle-based.Chapter 3. the application must synchronize in-between the kernel launch and the call to cudaPeekAtLastError() or cudaGetLastError(). the kernel call fails with a stack overflow error if the application is run via a CUDA debugger (cuda-gdb. To ensure that any error returned by cudaPeekAtLastError() or cudaGetLastError() does not originate from calls prior to the kernel launch. imperative API: Most objects are referenced by opaque handles that may be specified to functions to manipulate the objects.x.2 .2. so cudaPeekAtLastError() or cudaGetLastError() must be called just after the kernel launch to retrieve any pre-launch errors. Kernel launches do not return any error code.

Here is the host code of the sample from Section 2. 0. 0). Kernels are launched using API entry points as described in Section 3. // Initialize input vectors ..1.. not binary code. // Get number of devices supporting CUDA int deviceCount = 0.. // Allocate input vectors h_A and h_B in host memory float* h_A = (float*)malloc(size).3. cuDevice). Within a CUDA context. cuCtxCreate(&cuContext. if (deviceCount == 0) { printf("There is no device supporting CUDA.3.Chapter 3. } // Get handle for device 0 CUdevice cuDevice. // Create context CUcontext cuContext. readable via texture or surface references Object that describes how to interpret texture memory data Object that describes how to read or write CUDA arrays Texture reference Surface reference CUtexref CUsurfref The driver API is implemented in the nvcuda dynamic library and all its entry points are prefixed with cu. whereas PTX code is compiled to binary code at load time by the driver. Kernels written in C must therefore be compiled separately into PTX or binary objects. // Initialize cuInit(0). exit (0)..3. kernels are explicitly loaded as PTX or binary objects by the host code as described in Section 3. The driver API must be initialized with cuInit() before any function from the driver API is called..1 written using the driver API: int main() { int N = . Any application that wants to run on future device architectures must load PTX.\n"). size_t size = N * sizeof(float). cuDeviceGet(&cuDevice. float* h_B = (float*)malloc(size).3. This is because binary code is architecture-specific and therefore incompatible with future architectures.2 53 . Programming Interface Heap memory CUDA array CUdeviceptr CUarray Pointer to device memory Opaque container for one-dimensional or two-dimensional data on the device.2. cuDeviceGetCount(&deviceCount). A CUDA context must then be created that is attached to a specific device and made current to the calling host thread as detailed in Section 3. CUDA C Programming Guide Version 3.

int blocksPerGrid = (N + threadsPerBlock – 1) / threadsPerBlock. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. 1. offset. h_A. . offset. cuModule. cuParamSetSize(vecAdd. each context has 54 CUDA C Programming Guide Version 3. Besides objects such as modules and texture or surface references. __alignof(d_A)). __alignof(N)). offset += sizeof(d_B). ALIGN_UP(offset. cuLaunchGrid(vecAdd. ALIGN_UP(offset. size). cuParamSetv(vecAdd. cuParamSeti(vecAdd. cuModuleLoad(&cuModule. cuFuncSetBlockShape(vecAdd. // Allocate vectors in device memory CUdeviceptr d_A. “VecAdd. 3.. size). __alignof(d_B)). CUdeviceptr d_B. offset += sizeof(N). // Invoke kernel #define ALIGN_UP(offset.1 Context A CUDA context is analogous to a CPU process. cuParamSetv(vecAdd.. offset. offset). __alignof(d_C)). threadsPerBlock. cuModuleGetFunction(&vecAdd. cuMemcpyHtoD(d_B. cuParamSetv(vecAdd. offset += sizeof(d_A).Chapter 3.ptx”). cuMemAlloc(&d_A. sizeof(d_A)). } Full code can be found in the vectorAddDrv SDK code sample.2 . &d_B. sizeof(d_C)). &d_C.3. ALIGN_UP(offset. size). offset. h_B. &d_A. All resources and actions performed within the driver API are encapsulated inside a CUDA context. "VecAdd"). size). size). int threadsPerBlock = 256. CUdeviceptr d_C. cuMemAlloc(&d_B. N). offset += sizeof(d_C). // Get function handle from module CUfunction vecAdd. blocksPerGrid. 1). 1). cuMemAlloc(&d_C. ALIGN_UP(offset. and the system automatically cleans up these resources when the context is destroyed. Programming Interface // Create module from binary file CUmodule cuModule. // Copy vectors from host memory to device memory cuMemcpyHtoD(d_A. sizeof(d_B)).

it is made current to the calling host thread. Usage count facilitates interoperability between third party authored code operating in the same context. Programming Interface its own distinct 32-bit address space. Libraries that wish to create their own contexts – unbeknownst to their API clients who may or may not have created contexts of their own – would use cuCtxPushCurrent() and cuCtxPopCurrent() as illustrated in Figure 3-3. that are output by nvcc (see Section 3. For example. For most libraries. CUdeviceptr values from different contexts reference different memory locations. if any.1). including functions.3. it is expected that the application will have created a context before loading or initializing the library. cuCtxAttach() increments the usage count and cuCtxDetach() decrements it. and texture or surface references.2 55 . A usage count is also maintained for each context. The context is then "floating" and may be pushed as the current context for any host thread. Library Context Management 3. the application can create the context using its own heuristics. cuCtxPopCurrent() also restores the previous current context. The names for all symbols. are CUDA C Programming Guide Version 3. When a context is created with cuCtxCreate(). A context is destroyed when the usage count goes to 0 when calling cuCtxDetach() or cuCtxDestroy(). global variables. As a result. Library Initialization Call cuCtxCreate() Initialize context cuCtxPopCurrent() Library Call cuCtxPushCurrent() Use context cuCtxPopCurrent() Figure 3-3.2 Module Modules are dynamically loadable packages of device code and data. cuCtxPopCurrent() may be called to detach the context from the host thread. cuCtxCreate() pushes the new context onto the top of the stack. akin to DLLs in Windows. A host thread may have only one device context current at a time. each library would call cuCtxAttach() to increment the usage count and cuCtxDetach() to decrement the usage count when the library is done using the context. that way. Each host thread has a stack of current contexts. cuCtxCreate() creates a context with a usage count of 1. CUDA functions that operate in a context (most functions that do not involve device enumeration or context management) will return CUDA_ERROR_INVALID_CONTEXT if a valid context is not current to the thread. and the library simply operates on the context handed to it. if three libraries are loaded to use the same context.Chapter 3.

values). ++i) { // Parse error string here } 3. CUdeviceptr is an integer. char* PTXCode = “some PTX code”. but represents a pointer. The second argument of each of the cuParam*() functions specifies the offset of the parameter in the parameter stack. options[1] = CU_ASM_ERROR_LOG_BUFFER_SIZE_BYTES. cuModuleLoadDataEx(&cuModule. cuModule. values[1] = (void*)ERROR_BUFFER_SIZE.3 Kernel Execution cuFuncSetBlockShape() sets the number of threads per block for a given function. “MyKernel”). so its alignment requirement is __alignof(void*).2 . 56 CUDA C Programming Guide Version 3. This offset must match the alignment requirement for the parameter type in device code. cuModuleLoad(&cuModule. for (int i = 0. CUjit_option options[3]. the alignment requirement in device code matches the alignment requirement in host code and can therefore be obtained using __alignof(). This code sample compiles and loads a new module from PTX code and parses compilation errors: #define ERROR_BUFFER_SIZE 100 CUmodule cuModule. The only exception is when the host compiler aligns double and long long (and long on a 64-bit system) on a one-word boundary instead of a two-word boundary (for example. void* values[3]. The following code sample uses a macro to adjust the offset of each parameter to meet its alignment requirement. cuModuleGetFunction(&myKernel. options. values[0] = (void*)malloc(ERROR_BUFFER_SIZE). PTXCode. i < values[1]. options[0] = CU_ASM_ERROR_LOG_BUFFER. For all other basic types. Programming Interface maintained at module scope so that modules written by independent third parties may interoperate in the same CUDA context. cuFuncSetSharedSize() sets the size of shared memory for the function.Chapter 3. The cuParam*() family of functions is used to specify the parameters that will be provided to the kernel the next time cuLaunchGrid() or cuLaunch() is invoked to launch the kernel. 3.3. “myModule. This code sample loads a module and retrieves a handle to some kernel: CUmodule cuModule. CUfunction myKernel.ptx”). options[2] = CU_ASM_TARGET_FROM_CUCONTEXT. values[2] = 0. Alignment requirements in device code for the built-in vector types are listed in Table B-1. using gcc‟s compilation flag -mno-aligndouble) since in device code these types are always aligned on a two-word boundary. and how their threadIDs are assigned.

blockWidth. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. sizeof(f2)). ALIGN_UP(offset. int i. ALIGN_UP(offset. offset). int offset = 0. offset. The following structure. } myStruct. cuParamSetv(cuFunction. // float4‟s alignment is 16 cuParamSetv(cuFunction. offset += sizeof(dptr). 1). __alignof(c)). offset. __alignof(f)). cuLaunchGrid(cuFunction. typedef struct { float f. cuFuncSetBlockShape(cuFunction. // float2‟s alignment is 8 cuParamSetv(cuFunction. char c. Programming Interface #define ALIGN_UP(offset. offset. &f2. but it is padded in device code with 12 bytes after field f since the alignment requirement for field f4 is 16. ALIGN_UP(offset. Any parameter of type myStruct must therefore be passed using separate calls to cuParam*(). is not padded at all in host code. might therefore differ between device code and host code. such as: myStruct s. cuParamSeti(cuFunction. ALIGN_UP(offset. offset += sizeof(f). f).2 57 . cuParamSetSize(cuFunction. The alignment requirement of a structure is equal to the maximum of the alignment requirements of its fields. cuParamSetf(cuFunction. &dptr. offset += sizeof(c). offset. float4 f4. 16). offset += sizeof(f4). __alignof(i)). cuParamSeti(cuFunction. CUdeviceptr. CUDA C Programming Guide Version 3.Chapter 3. c). ALIGN_UP(offset. offset. i). sizeof(f4)). CUdeviceptr dptr. offset. sizeof(dptr)). gridHeight). offset += sizeof(f2). __alignof(dptr)). for example. ALIGN_UP(offset. 8). float2 f2. or non-aligned double and long long. Such a structure might also be padded differently. offset += sizeof(i). blockHeight. &f4. gridWidth. The alignment requirement of a structure that contains built-in vector types. float f. float4 f4.

4 Device Memory Linear memory is allocated using cuMemAlloc() or cuMemAllocPitch() and freed using cuMemFree(). Programming Interface cuParamSetv(cuFunction.f4). } // Get handle for device 0 CUdevice cuDevice = 0. ALIGN_UP(offset. // Create module from binary file CUmodule cuModule.f4)).f)).2. cuMemAlloc(&d_C. CUdeviceptr d_C.f4. size). cuDevice). // Get number of devices supporting CUDA int deviceCount = 0.ptx”). “VecAdd. offset += sizeof(s. cuDeviceGetCount(&deviceCount).\n"). 0.3. 0). cuCtxCreate(&cuContext. cuModuleGetFunction(&vecAdd.f). // Copy vectors from host memory to device memory // h_A and h_B are input vectors stored in host memory 58 CUDA C Programming Guide Version 3. offset. &s. offset. size). CUdeviceptr d_B. cuMemAlloc(&d_B. cuModule. exit (0).f. // Allocate vectors in device memory size_t size = N * sizeof(float). CUdeviceptr d_A. 3. size). // Get function handle from module CUfunction vecAdd. &s. Here is the host code of the sample from Section 3.1 written using the driver API: // Host code int main() { // Initialize if (cuInit(0) != CUDA_SUCCESS) exit (0). cuMemAlloc(&d_A.2 . sizeof(s.Chapter 3. // Create context CUcontext cuContext. "VecAdd"). sizeof(s. if (deviceCount == 0) { printf("There is no device supporting CUDA. 16). cuDeviceGet(&cuDevice. offset += sizeof(s. cuModuleLoad(&cuModule. // float4‟s alignment is 16 cuParamSetv(cuFunction.

cuParamSetv(myKernel. cuParamSetSize(VecAdd. // Copy result from device memory to host memory // h_C contains the result in host memory cuMemcpyDtoH(h_C. sizeof(d_B)). } Linear memory can also be allocated through cuMemAllocPitch(). offset. offset += sizeof(d_A). size). cuMemFree(d_B). 1). __alignof(d_B)). threadsPerBlock. CUfunction myKernel. cuFuncSetBlockShape(myKernel. cuModuleGetFunction(&myKernel. blocksPerGrid. cuParamSetv(vecAdd. Programming Interface cuMemcpyHtoD(d_A. cuLaunchGrid(VecAdd. cuMemAllocPitch(&devPtr. width * sizeof(float). &d_A. “MyKernel”). cuFuncSetBlockShape(vecAdd. cuParamSetv(vecAdd. sizeof(d_C)). ALIGN_UP(offset.1. __alignof(d_C)). sizeof(devPtr)). size). 1). sizeof(devPtr)). cuModule. offset. 1. 1). 0. 100.2 59 . size_t pitch. // Device code __global__ void MyKernel(float* devPtr) CUDA C Programming Guide Version 3. This function is recommended for allocations of 2D arrays as it makes sure that the allocation is appropriately padded to meet the alignment requirements described in Section 5. h_A. therefore ensuring best performance when accessing the row addresses or performing copies between 2D arrays and other regions of device memory (using the cuMemcpy2D()).Chapter 3. 512. cuParamSetSize(myKernel. int threadsPerBlock = 256. offset. size). ALIGN_UP(offset. cuMemFree(d_C). sizeof(d_A)). &devPtr. offset += sizeof(d_C). ALIGN_UP(offset. int blocksPerGrid = (N + threadsPerBlock – 1) / threadsPerBlock. 1. d_C. height. offset += sizeof(d_B). // Invoke kernel #define ALIGN_UP(offset. The returned pitch (or stride) must be used to access array elements. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. 4). offset). 1). __alignof(d_A)).3. &d_B. The following code sample allocates a width×height 2D array of floating-point values and shows how to loop over the array elements in device code: // Host code (assuming cuModule has been loaded) CUdeviceptr devPtr. // Free device memory cuMemFree(d_A). cuLaunchGrid(myKernel. h_B. &pitch. cuMemcpyHtoD(d_B.2. cuParamSetv(vecAdd. &d_C.

Format = CU_AD_FORMAT_FLOAT. copyParam. cuArrayCreate(&cuArray.Height = height. &ptr. cuModuleGetGlobal(&devPtr. &value. __device__ float* devPointer. copyParam. } } } The following code sample allocates a width×height CUDA array of one 32-bit floating-point component: CUDA_ARRAY_DESCRIPTOR desc. copyParam. copyParam. “devData”). float data[256]. size_t bytes. linear memory allocated with cuMemAllocPitch(). cuMemcpyHtoD(devPtr. sizeof(float)).dstMemoryType = CU_MEMORYTYPE_ARRAY. “devPointer”). bytes). copyParam. The following code sample illustrates various ways of accessing global variables via the driver API: CUdeviceptr devPtr. desc. cuModule. float value = 3. CUdeviceptr ptr. &bytes. cuMemAlloc(&ptr.NumChannels = 1. copyParam. CUarray cuArray.srcDevice = devPtr. __constant__ float constData[256]. cuModuleGetGlobal(&devPtr. desc. Programming Interface { for (int r = 0. desc. data. 0.Width = width. The following code sample copies the 2D array to the CUDA array allocated in the previous code samples: CUDA_MEMCPY2D copyParam. “constData”). ++c) { float element = row[c].dstArray = cuArray.srcPitch = pitch. &bytes. ++r) { float* row = (float*)((char*)devPtr + r * pitch). sizeof(ptr)). and CUDA arrays.srcMemoryType = CU_MEMORYTYPE_DEVICE. The reference manual lists all the various functions used to copy memory between linear memory allocated with cuMemAlloc().WidthInBytes = width * sizeof(float). r < height. 256 * sizeof(float)). 60 CUDA C Programming Guide Version 3. memset(&copyParam. c < width.Chapter 3.14f. devPtr. bytes).Height = height. &bytes.2 . cuMemcpyHtoD(devPtr. cuMemcpyDtoH(data. &desc). cuModule. sizeof(copyParam)). cuModule. for (int c = 0. __device__ float devData. cuMemcpy2D(&copyParam). cuMemcpyHtoD(devPtr. cuModuleGetGlobal(&devPtr. desc. copyParam.

elements + row * M.width * B. shared memory is statically allocated within the kernel as opposed to allocated at runtime through cuFuncSetSharedSize(). int offset = 0. sizeof(d_C)). cuMemcpyHtoD(elements. d_B. &d_B. offset += sizeof(d_B). sizeof(d_A)). 1). CUDA C Programming Guide Version 3. sizeof(d_B)).width * C. cuMemAlloc(elements. d_B.height * sizeof(float).width = d_B. int stride. cuMemcpyHtoD(elements.height. d_A.elements = (float*)elements. &d_A. size). offset. int height. const Matrix B.5 Shared Memory The following code sample is the driver version of the host code of the sample from Section 3. d_C.width = d_A. col) = *(M. cuParamSetSize(matMulKernel.elements = (float*)elements. &d_C. d_A. BLOCK_SIZE. cuModuleGetFunction(&matMulKernel. In this sample. A. } Matrix.stride = A.2 61 . offset).height * sizeof(float). cuParamSetv(matMulKernel.height * sizeof(float).height = B.elements.stride + col) typedef struct { int width.width. // Matrix multiplication . cuParamSetv(matMulKernel. // Matrices are stored in row-major order: // M(row.elements.2. // Load A and B to device memory Matrix d_A. cuMemAlloc(&elements.height. // Invoke kernel (assuming cuModule has been loaded) CUfunction matMulKernel. offset. offset. size).Chapter 3. size = C.width = d_C. cuLaunchGrid(matMulKernel.height = A. size_t size = A.height = C. d_C.width. size).elements = (float*)elements.Host code // Matrix dimensions are assumed to be multiples of BLOCK_SIZE void MatMul(const Matrix A. offset += sizeof(d_A). B. d_B.height.width * A. Matrix d_B. size = B. d_C.width.2. Matrix C) { CUdeviceptr elements. size).3. // Allocate C in device memory Matrix d_C. d_A. float* elements. cuParamSetv(matMulKernel. offset += sizeof(d_C). "MatMulKernel"). Programming Interface 3. cuModule.stride = C. size). BLOCK_SIZE. cuMemAlloc(&elements. cuFuncSetBlockShape(matMulKernel.stride = B.

elements). CU_TRSA_OVERRIDE_FORMAT). (CUdeviceptr)d_C. filter mode. cuModule. &minor. ++device) { CUdevice cuDevice. } 3. int device.y). 2.elements. A. // Read C from device memory cuMemcpyDtoH(C.2 . size). cuDevice). 62 CUDA C Programming Guide Version 3. cuArray. “texRef”). cuMemFree((CUdeviceptr)d_B. cuDeviceGet(&cuDevice. } 3. minor.Chapter 3. cuDeviceGetCount(&deviceCount). cudaReadModeElementType> texRef. the following code sample retrieves texRef„s handle: CUtexref cuTexRef. for (int device = 0.1 Texture and Surface Memory Texture Memory Texure binding is done using cuTexRefSetAddress() for linear memory and cuTexRefSetArray() for CUDA arrays. cuTexRefSetAddress2D(cuTexRef.elements). cuDeviceComputeCapability(&major. The reference manual lists various functions used to set address mode.elements). The following code samples bind texRef to a CUDA array cuArray: cuTexRefSetArray(cuTexRef.3. format. otherwise. cuMemFree((CUdeviceptr)d_C.width / dimBlock. and other flags for some texture reference. cuModuleGetTexRef(&cuTexRef. // Free device memory cuMemFree((CUdeviceptr)d_A. The following code sample binds texRef to some linear memory pointed to by devPtr: CUDA_ARRAY_DESCRIPTOR desc. device < deviceCount. The format specified when binding a texture to a texture reference must match the parameters specified when declaring the texture reference. pitch).x.6 Multiple Devices cuDeviceGetCount() and cuDeviceGet() provide a way to enumerate the devices present in the system and other functions (described in the reference manual) to retrieve their properties: int deviceCount.height / dimBlock. If a module cuModule contains some texture reference texRef defined as texture<float. &desc. device).3. devPtr. Programming Interface B.7 3.7. int major.elements. the results of texture fetches are undefined.3.

Height = height. CU_TR_ADDRESS_MODE_WRAP).3. __alignof(width)). offset += sizeof(width). // Copy to device memory some data located at address h_data // in host memory CUDA_MEMCPY2D copyParam.srcPitch = width * sizeof(float). &desc). 1. offset. CU_AD_FORMAT_FLOAT.srcMemoryType = CU_MEMORYTYPE_HOST. // Allocate result of transformation in device memory CUdeviceptr output.Format = CU_AD_FORMAT_FLOAT. cuTexRefSetFormat(texRef. desc. copyParam. // Bind the array to the texture reference cuTexRefSetArray(texRef. 1).dstMemoryType = CU_MEMORYTYPE_ARRAY. #define ALIGN_UP(offset. offset += sizeof(output). // Invoke kernel (assuming cuModule has been loaded) CUfunction transformKernel.Width = width.NumChannels = 1. copyParam. CU_TR_ADDRESS_MODE_WRAP). cuModule. cuMemAlloc(&output. Programming Interface The following code sample is the driver version of the host code of the sample from Section 3. offset.2. memset(&copyParam. cuModule. // Host code int main() { // Allocate CUDA array in device memory CUarray cuArray.1. 0. cuParamSetv(transformKernel. copyParam. // Set texture parameters CUtexref texRef. CUDA_ARRAY_DESCRIPTOR desc. desc. cuTexRefSetAddressMode(texRef. cuTexRefSetFilterMode(texRef. copyParam. sizeof(output)). desc. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. CU_TRSF_NORMALIZED_COORDINATES). cuMemcpy2D(&copyParam).Chapter 3. CUDA C Programming Guide Version 3. cuArrayCreate(&cuArray. copyParam. CU_TR_FILTER_MODE_LINEAR). width).srcPitch. cuModuleGetTexRef(&texRef. CU_TRSA_OVERRIDE_FORMAT). desc.WidthInBytes = copyParam. __alignof(output)). ALIGN_UP(offset. cuParamSeti(transformKernel. copyParam. width * height * sizeof(float)). sizeof(copyParam)). "texRef")).srcHost = h_data.4. copyParam.dstArray = cuArray. &output. ALIGN_UP(offset. "transformKernel").2 63 . cuTexRefSetAddressMode(texRef. cuArray. 0. cuTexRefSetFlags(texRef.Height = height. cuModuleGetFunction(&transformKernel.

copyParam.srcPitch = width * sizeof(float).Format = CU_AD_FORMAT_UNSIGNED_INT8. cuParamSeti(transformKernel.2 . copyParam. 64 CUDA C Programming Guide Version 3.dstMemoryType = CU_MEMORYTYPE_ARRAY.Height = height. Programming Interface ALIGN_UP(offset. cuArrayCreate(&cuInputArray.Height = height.2. angle). // Copy to device memory some data located at address h_data // in host memory CUDA_MEMCPY2D copyParam.srcHost = h_data. cuArray. // Host code int main() { // Allocate CUDA arrays in device memory CUDA_ARRAY_DESCRIPTOR desc. 0. (height + dimBlock. cuFuncSetBlockShape(transformKernel. copyParam. CUarray cuInputArray. cuMemFree(output). offset.Width = width. desc. “surfRef”). offset += sizeof(angle). cuLaunchGrid(transformKernel. (width + dimBlock.2 Surface Memory Surface binding is done using cuSurfRefSetArray() for CUDA arrays. The following code samples bind surfRef to a CUDA array cuArray: cuSurfRefSetArray(cuSurfRef. __alignof(angle)). ALIGN_UP(offset. 1).dstArray = cuInputArray. desc.x. cuParamSetf(transformKernel. copyParam. cuArrayCreate(&cuOutputArray.4.srcMemoryType = CU_MEMORYTYPE_HOST.3. copyParam. 16.NumChannels = 4. cuParamSetSize(transformKernel.y). CU_SRSA_USE_ARRAY_FORMAT). &desc). offset += sizeof(height). memset(&copyParam.1. desc. __alignof(height)). CUarray cuOutputArray. 16. cuModuleGetSurfRef(&cuSurfRef.7.Chapter 3.WidthInBytes = copyParam.x – 1) / dimBlock.4. The following code sample is the driver version of the host code of the sample from Section 3. the following code sample retrieves surfRef„s handle: CUsurfref cuSurfRef. offset)). } 3. &desc). height). If a module cuModule contains some surface reference surfRef defined as surface<void. 2> surfRef. desc. sizeof(copyParam)). cuModule.y – 1) / dimBlock. offset. copyParam. copyParam. // Free device memory cuArrayDestroy(cuArray).srcPitch.

16. Page-locked memory mapping is enabled for a CUDA context by creating the context with the CU_CTX_MAP_HOST flag and device pointers to mapped pagelocked memory are retrieved using cuMemHostGetDevicePointer().5. cuSurfRefSetArray(outputSurfRef. cuModule. offset += sizeof(height). cuOutputArray. cuParamSeti(copyKernel. // Invoke kernel (assuming cuModule has been loaded) CUfunction copyKernel. cuFuncSetBlockShape(copyKernel. cuLaunchGrid(copyKernel. CU_MEMHOSTALLOC_DEVICEMAP to allocate mapped page-locked memory (see Section 3. } 3.2. __alignof(height)). CU_SRSA_USE_ARRAY_FORMAT). cuArrayDestroy(cuOutputArray). alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. // Bind the arrays to the surface references cuSurfRefSetArray(inputSurfRef. (height + dimBlock. offset += sizeof(width). offset)). CU_MEMHOSTALLOC_WRITECOMBINED to allocate memory as write- combining (see Section 3. cuModuleGetFunction(&copyKernel. height). 16.2. 1). Programming Interface cuMemcpy2D(&copyParam). offset.1). __alignof(width)).x. ALIGN_UP(offset. ALIGN_UP(offset.3. cuParamSetSize(copyKernel. CUDA C Programming Guide Version 3. "copyKernel").3). #define ALIGN_UP(offset. cuInputArray. cuParamSeti(copyKernel. Applications may query whether a device supports mapped page-locked host memory or not by checking the CU_DEVICE_ATTRIBUTE_CAN_MAP_HOST_MEMORY attribute using cuDeviceGetAttribute(). Page-locked host memory is freed using cuMemFreeHost(). width). (width + dimBlock.y).5. // Free device memory cuArrayDestroy(cuInputArray).5. CU_SRSA_USE_ARRAY_FORMAT).2.2). offset.x – 1) / dimBlock.8 Page-Locked Host Memory Page-locked host memory can be allocated using cuMemHostAlloc() with optional mutually non-exclusive flags:    CU_MEMHOSTALLOC_PORTABLE to allocate memory that is portable across CUDA contexts (see Section 3.y – 1) / dimBlock.Chapter 3.2 65 .

2. &outputDevPtr. ++i) cuMemcpyDtoHAsync(hostPtr + i * size. size. sizeof(inputDevPtr)). ++i) cuMemcpyHtoDAsync(inputDevPtr + i * size.3. for (int i = 0. for (int i = 0.6. cuParamSeti(cuFunction. CUstream stream[2]. i < 2. for (int i = 0. float* hostPtr. 1). &inputDevPtr. offset += sizeof(int). offset). ++i) cuStreamCreate(&stream[i]. The following code sample is the driver version of the code sample from Section 3. 2 * size). Applications may query if a device supports multiple kernels running concurrently by checking the CU_DEVICE_ATTRIBUTE_CONCURRENT_KERNELS attribute using cuDeviceGetAttribute(). stream[i]). for (int i = 0. 3. offset += sizeof(inputDevPtr). offset. ++i) cuStreamDestroy(&stream[i]). hostPtr + i * size. offset.2 . cuParamSetv(cuFunction. 0). 512. stream[i]). i < 2. __alignof(outputDevPtr)). ALIGN_UP(offset. offset.9. ++i) { #define ALIGN_UP(offset. cuParamSetSize(cuFunction. cuParamSetv(cuFunction. i < 2. cuFuncSetBlockShape(cuFunction. offset += sizeof(outputDevPtr). sizeof(outputDevPtr)). stream[i]). i < 2. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. cuCtxSynchronize().4. size. i < 2.3. 66 CUDA C Programming Guide Version 3. size). 100. outputDevPtr + i * size. 1.Chapter 3. ALIGN_UP(offset. cuLaunchGridAsync(cuFunction. } for (int i = 0.1 Stream The driver API provides functions similar to the runtime API to manage streams. ALIGN_UP(offset.9 Asynchronous Concurrent Execution Applications may query if a device can perform copies between page-locked host memory and device memory concurrently with kernel execution by checking the CU_DEVICE_ATTRIBUTE_GPU_OVERLAP attribute using cuDeviceGetAttribute(). 1. cuMemAllocHost(&hostPtr. __alignof(inputDevPtr)). Programming Interface 3. __alignof(size)).

start. They are destroyed this way: cuEventDestroy(start). cuParamSeti(cuFunction.2 Event Management The driver API provides functions similar to the runtime API to manage events. for (int i = 0. sizeof(inputDevPtr)). CUevent start.6. i < 2. offset += sizeof(size). cuParamSetv(cuFunction. sizeof(outputDevPtr)).3.3. cuEventDestroy(stop). ALIGN_UP(offset. 1). stop). ALIGN_UP(offset. offset += sizeof(outputDevPtr). ALIGN_UP(offset. 0). ++i) cuMemcpyHtoDAsync(inputDevPtr + i * size. Programming Interface 3. size.10 Graphics Interoperability The driver API provides functions similar to the runtime API to manage graphics interoperability. stream[i]). cuEventCreate(&stop). stream[i]). block. size. offset. ++i) { #define ALIGN_UP(offset. or spin on a synchronous function call can be specified by calling cuCtxCreate() with some specific flags as described in the reference manual.3 Synchronous Calls Whether the host thread will yield. 1. 1. &outputDevPtr.2 67 . 100. for (int i = 0. cuParamSetSize(cuFunction. i < 2. offset. size). 0). cuParamSetv(cuFunction. 3. cuLaunchGridAsync(cuFunction.9. The following code sample is the driver version of the code sample from Section 3. hostPtr + i * size. offset += sizeof(inputDevPtr).6. __alignof(size)). stream[i]). __alignof(inputDevPtr)).Chapter 3. offset. cuEventSynchronize(stop). float elapsedTime. cuFuncSetBlockShape(cuFunction. CUDA C Programming Guide Version 3. } for (int i = 0. ++i) cuMemcpyDtoHAsync(hostPtr + i * size. cuEventCreate(&start).2. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0.3. cuEventRecord(stop. i < 2.9. 3. outputDevPtr + i * size. cuEventElapsedTime(&elapsedTime. 512. cuEventRecord(start. __alignof(outputDevPtr)). offset). &inputDevPtr. stop.

10.1 and 3. 3. read-only) that the CUDA driver can use to optimize resource management.7. cuModuleLoad(&cuModule.1 apply.ptx”). Registering a resource is potentially high-overhead and therefore typically called only once per resource. A mapped resource can be read from or written to by kernels using the device memory address returned by cuGraphicsResourceGetMappedPointer() for buffers and cuGraphicsSubResourceGetMappedArray() for CUDA arrays.10. Accessing a resource through OpenGL or Direct3D while it is mapped to CUDA produces undefined results.3. Once a resource is registered to CUDA.2. These functions return a CUDA graphics resource of type CUgraphicsResource..1 and 3.2. // Create module from binary file CUmodule cuModule. // Get handle for device 0 CUdevice cuDevice = 0. CUfunction createVertices. 68 CUDA C Programming Guide Version 3.7. int main() { // Initialize driver API . The following code sample is the driver version of the code sample from Section 3.10.3. The same restrictions described in Section 3.10. “createVertices. Programming Interface A resource must be registered to CUDA before it can be mapped using the functions mentioned in Sections 3. GLuint positionsVBO. texture. A buffer object is registered using cuGraphicsGLRegisterBuffer(). A CUDA graphics resource is unregistered using cuGraphicsUnregisterResource(). and renderbuffer objects.Chapter 3. struct cudaGraphicsResource* positionsVBO_CUDA.1 OpenGL Interoperability Interoperability with OpenGL requires that the CUDA context be specifically created using cuGLCtxCreate() instead of cuCtxCreate(). // Create context CUcontext cuContext. it can be mapped and unmapped as many times as necessary using cuGraphicsMapResources() and cuGraphicsUnmapResources(). cuDevice). The OpenGL resources that may be mapped into the address space of CUDA are OpenGL buffer. cuGLCtxCreate(&cuContext.2. Sections 3.2 . 0). 0. cuDeviceGet(&cuDevice.1. A texture or renderbuffer object is registered using cuGraphicsGLRegisterImage().3.2 give specifics for each graphics API and some code samples.10. cuGraphicsResourceSetMapFlags() can be called to specify usage hints (write-only..3.3.

&positions. offset). time). &num_bytes. unsigned int size = width * height * 4 * sizeof(float). offset. sizeof(positions)). "createVertices"). height). __alignof(time)).. cuLaunchGrid(createVertices. } void display() { // Map OpenGL buffer object for writing from CUDA CUdeviceptr positions. __alignof(height)). ALIGN_UP(offset. cudaGraphicsMapFlagsWriteDiscard). glBufferData(GL_ARRAY_BUFFER. GL_DYNAMIC_DRAW). positionsVBO_CUDA)). height / threadsPerBlock). ALIGN_UP(offset. glutDisplayFunc(display). // Execute kernel #define ALIGN_UP(offset. Programming Interface // Get function handle from module cuModuleGetFunction(&createVertices. cuGraphicsMapResources(1. positionsVBO). size. ALIGN_UP(offset. ALIGN_UP(offset. // Create buffer object and register it with CUDA glGenBuffers(1. 0). threadsPerBlock. positionsVBO. size_t num_bytes.2 69 . glBindBuffer(GL_ARRAY_BUFFER. offset += sizeof(positions). 0. width / threadsPerBlock. width). // Launch rendering loop glutMainLoop(). threadsPerBlock. &vbo). offset += sizeof(width). int threadsPerBlock = 16. __alignof(positions)).Chapter 3. cuParamSetv(createVertices. 0). glBindBuffer(GL_ARRAY_BUFFER.. // Unmap buffer object CUDA C Programming Guide Version 3. cuParamSetSize(createVertices. 1). offset += sizeof(height). &positionsVBO_CUDA. cuParamSetf(createVertices. cuGraphicsGLRegisterBuffer(&positionsVBO_CUDA. __alignof(width)). offset += sizeof(time). offset. cuFuncSetBlockShape(createVertices. cuParamSeti(createVertices. cuParamSeti(createVertices. // Initialize OpenGL and GLUT . offset. cuGraphicsResourceGetMappedPointer((void**)&positions. offset. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. cuModule.

0. 0. glBindBuffer(GL_ARRAY_BUFFER. 70 CUDA C Programming Guide Version 3. &positionsVBO_CUDA.Chapter 3.2 . and surfaces. GL_FLOAT. cuGraphicsD3D10RegisterResource(). } void deleteVBO() { cuGraphicsUnregisterResource(positionsVBO_CUDA). glutPostRedisplay(). See Section 4.3. glDisableClientState(GL_VERTEX_ARRAY). positionsVBO). 0). This is done by creating the CUDA context using cuD3D9CtxCreate() or cuD3D9CtxCreateOnDevice() (resp. Applications that intend to support interoperability between Direct3D devices in SLI configurations and CUDA should be written to only use these calls instead of the cuD3D[9|10|11]CtxCreate() calls. glEnableClientState(GL_VERTEX_ARRAY). // Render from buffer object glClear(GL_COLOR_BUFFER_BIT | GL_DEPTH_BUFFER_BIT). These resources are registered using cuGraphicsD3D9RegisterResource(). textures. } On Windows and for Quadro GPUs.2 Direct3D Interoperability Interoperability with Direct3D requires that the Direct3D device be specified when the CUDA context is created.3 for general recommendations related to interoperability between Direct3D devices using SLI and CUDA contexts.10. cuD3D10CtxCreate()or cuD3D10CtxCreateOnDevice() and cuD3D11CtxCreate()or cuD3D11CtxCreateOnDevice()) instead of cuCtxCreate(). glDeleteBuffers(1. glVertexPointer(4. they can call cuCtxPushCurrent() and cuCtxPopCurrent()to change the CUDA context active at a given time. The Direct3D resources that may be mapped into the address space of CUDA are Direct3D buffers. cuWGLGetDevice() can be used to retrieve the CUDA device associated to the handle returned by wglEnumGpusNV(). glDrawArrays(GL_POINTS. and cuGraphicsD3D11RegisterResource(). Programming Interface cuGraphicsUnmapResources(1. width * height). // Swap buffers glutSwapBuffers(). A call to cuD3D[9|10|11]GetDevices()should be used to obtain a list of CUDA device handles that can be passed as the last parameter to cuD3D[9|10|11]CtxCreateOnDevice(). These two new sets of calls are cuD3D[9|10|11]CtxCreateOnDevice() and cuD3D[9|10|11]GetDevices(). 0). &positionsVBO). Two sets of calls are also available to allow the creation of CUDA devices with interoperability with Direct3D devices that use NVIDIA SLI in AFR (Alternate Frame Rendering) mode. In addition. 3.

. hWnd. cuModule. }. 0. // Create context CUdevice cuDevice. for (. adapter++) { D3DADAPTER_IDENTIFIER9 adapterId. 0. // Get function handle from module cuModuleGetFunction(&createVertices. z. device->CreateVertexBuffer(size. if (cuD3D9GetDevice(&dev. D3DFVF_CUSTOMVERTEX.Chapter 3. D3D->CreateDevice(adapter. struct cudaGraphicsResource* positionsVB_CUDA. struct CUSTOMVERTEX { FLOAT x. cuD3D9CtxCreate(&cuContext. &cuDevice. // Create vertex buffer and register it with CUDA unsigned int size = width * height * sizeof(CUSTOMVERTEX).2. Direct3D 9 Version: IDirect3D9* D3D. // Create module from binary file CUmodule cuModule. IDirect3DVertexBuffer9* positionsVB. g_pD3D->GetAdapterIdentifier(adapter.7.DeviceName) == cudaSuccess) break.ptx”). &device). D3DDEVTYPE_HAL. adapter < g_pD3D->GetAdapterCount(). int main() { // Initialize Direct3D D3D = Direct3DCreate9(D3D_SDK_VERSION). // Initialize driver API . device).2 71 .. // Get a CUDA-enabled adapter unsigned int adapter = 0. &positionsVB. D3DCREATE_HARDWARE_VERTEXPROCESSING. adapterId. cuGraphicsD3D9RegisterResource(&positionsVB_CUDA.2. CUDA C Programming Guide Version 3. 0). DWORD color. Programming Interface The following code sample is the driver version of the host code of the sample from Section 3.. y. “createVertices. &adapterId).. cuModuleLoad(&cuModule. } // Create device . D3DPOOL_DEFAULT. CUcontext cuContext. IDirect3DDevice9 device. 0. "createVertices"). &params. int dev.

// Launch rendering loop while (. offset). __alignof(positions)). // Unmap vertex buffer cuGraphicsUnmapResources(1. . cuGraphicsResourceGetMappedPointer((void**)&positions. height). cuLaunchGrid(createVertices. 72 CUDA C Programming Guide Version 3. } void releaseVB() { cuGraphicsUnregisterResource(positionsVB_CUDA). } } void Render() { // Map vertex buffer for writing from CUDA float4* positions. height / threadsPerBlock). threadsPerBlock.Chapter 3. int threadsPerBlock = 16. cuParamSetv(createVertices. __alignof(width)). cuFuncSetBlockShape(createVertices.. Programming Interface positionsVB. cuParamSeti(createVertices.. width / threadsPerBlock. offset.. Render(). ALIGN_UP(offset. __alignof(time)). cudaGraphicsMapFlagsWriteDiscard).. cuGraphicsMapResources(1. offset += sizeof(time). cuParamSetSize(createVertices. offset += sizeof(height). width). &positions. // Draw and present . ALIGN_UP(offset. cuParamSeti(createVertices.. size_t num_bytes. offset. 0). &num_bytes. &positionsVB_CUDA. ALIGN_UP(offset. offset += sizeof(positions). alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0.) { . // Execute kernel #define ALIGN_UP(offset. __alignof(height)). offset.. offset. cuGraphicsResourceSetMapFlags(positionsVB_CUDA. cuParamSetf(createVertices. positionsVB_CUDA)). threadsPerBlock. time). cudaGraphicsRegisterFlagsNone).2 .. 1). 0). offset += sizeof(width). sizeof(positions)). ALIGN_UP(offset. &positionsVB_CUDA..

D3D10_SDK_VERSION.ptx”). 0. int main() { // Get a CUDA-enabled adapter IDXGIFactory* factory. // Create module from binary file CUmodule cuModule. !adapter. D3D10_BUFFER_DESC bufferDesc. cuD3D10CtxCreate(&cuContext. CUDA C Programming Guide Version 3. } factory->Release(). Programming Interface positionsVB->Release(). struct CUSTOMVERTEX { FLOAT x. IDXGIAdapter* adapter = 0. "createVertices"). cuModule. ++i) { if (FAILED(factory->EnumAdapters(i. // Create context CUdevice cuDevice. &device). }. // Create vertex buffer and register it with CUDA unsigned int size = width * height * sizeof(CUSTOMVERTEX). z. adapter) == cudaSuccess) break. &cuDevice. 0. int dev. &swapChainDesc &swapChain. D3D10_DRIVER_TYPE_HARDWARE. struct cudaGraphicsResource* positionsVB_CUDA. } Direct3D 10 Version: ID3D10Device* device. CUcontext cuContext. ID3D10Buffer* positionsVB.. CreateDXGIFactory(__uuidof(IDXGIFactory).2 73 . // Initialize driver API . “createVertices. &adapter)) break. cuModuleLoad(&cuModule. device).Chapter 3. D3D10CreateDeviceAndSwapChain(adapter... D3D10_CREATE_DEVICE_DEBUG. DWORD color. if (cuD3D10GetDevice(&dev. y.. for (unsigned int i = 0. adapter->Release(). // Create swap chain and device . (void**)&factory). // Get function handle from module cuModuleGetFunction(&createVertices. adapter->Release().

bufferDesc. cuParamSetv(createVertices. width / threadsPerBlock. Render(). Programming Interface bufferDesc. cuGraphicsResourceSetMapFlags(positionsVB_CUDA. cudaGraphicsRegisterFlagsNone). height). cuParamSetSize(createVertices.MiscFlags = 0. size_t num_bytes. &positionsVB_CUDA. ALIGN_UP(offset. // Execute kernel #define ALIGN_UP(offset. threadsPerBlock. time).Chapter 3. cuGraphicsResourceGetMappedPointer((void**)&positions. __alignof(height)).. offset. 74 CUDA C Programming Guide Version 3.. bufferDesc. width).. ALIGN_UP(offset. cuLaunchGrid(createVertices. 0). offset += sizeof(height). device->CreateBuffer(&bufferDesc. cuGraphicsD3D10RegisterResource(&positionsVB_CUDA. __alignof(width)). &positionsVB_CUDA.) { .ByteWidth = size.2 . height / threadsPerBlock).. 1). positionsVB_CUDA)). . offset. offset += sizeof(width). __alignof(positions)). // Unmap vertex buffer cuGraphicsUnmapResources(1. &positionsVB). 0. &num_bytes. cuGraphicsMapResources(1. offset. __alignof(time)). alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0.CPUAccessFlags = 0. int threadsPerBlock = 16. // Launch rendering loop while (. bufferDesc. sizeof(positions)). offset += sizeof(positions). offset). &positions. threadsPerBlock.. cuParamSeti(createVertices. offset. ALIGN_UP(offset. 0). cudaGraphicsMapFlagsWriteDiscard). cuParamSetf(createVertices.. positionsVB. bufferDesc. cuParamSeti(createVertices.Usage = D3D10_USAGE_DEFAULT. ALIGN_UP(offset. offset += sizeof(time). cuFuncSetBlockShape(createVertices. } } void Render() { // Map vertex buffer for writing from CUDA float4* positions.BindFlags = D3D10_BIND_VERTEX_BUFFER.

&cuDevice. } void releaseVB() { cuGraphicsUnregisterResource(positionsVB_CUDA). CUcontext cuContext. positionsVB->Release(). adapter->Release(). CUDA C Programming Guide Version 3. cuD3D11CtxCreate(&cuContext. D3D11_CREATE_DEVICE_DEBUG. }.. } factory->Release(). featureLevels. &swapChainDesc. for (unsigned int i = 0. IDXGIAdapter* adapter = 0. ID3D11Buffer* positionsVB.. int main() { // Get a CUDA-enabled adapter IDXGIFactory* factory. } Direct3D 11 Version: ID3D11Device* device. device). Programming Interface // Draw and present .. &device.2 75 .Chapter 3. adapter) == cudaSuccess) break. 0. D3D11_SDK_VERSION. &deviceContext). 0. DWORD color. int dev. struct cudaGraphicsResource* positionsVB_CUDA. &swapChain. !adapter. 3.. sFnPtr_D3D11CreateDeviceAndSwapChain(adapter. y. &featureLevel. if (cuD3D11GetDevice(&dev. z. // Create context CUdevice cuDevice. ++i) { if (FAILED(factory->EnumAdapters(i. D3D11_DRIVER_TYPE_HARDWARE. // Initialize driver API . struct CUSTOMVERTEX { FLOAT x. CreateDXGIFactory(__uuidof(IDXGIFactory). (void**)&factory). adapter->Release(). // Create swap chain and device . &adapter)) break...

&num_bytes. "createVertices"). &positions. alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. . Render(). cuModule.ptx”). bufferDesc. width). } } void Render() { // Map vertex buffer for writing from CUDA float4* positions. bufferDesc.) { . // Create vertex buffer and register it with CUDA unsigned int size = width * height * sizeof(CUSTOMVERTEX). ALIGN_UP(offset. offset. height). cuGraphicsMapResources(1. offset. cuParamSetv(createVertices. // Get function handle from module cuModuleGetFunction(&createVertices. offset += sizeof(time). &positionsVB_CUDA. Programming Interface // Create module from binary file CUmodule cuModule... time). positionsVB.Usage = D3D11_USAGE_DEFAULT.2 . ALIGN_UP(offset. // Launch rendering loop while (. // Execute kernel #define ALIGN_UP(offset... cuParamSeti(createVertices.CPUAccessFlags = 0. 0.Chapter 3. &positionsVB). __alignof(time)). 0). ALIGN_UP(offset. cuModuleLoad(&cuModule. offset. __alignof(positions)). offset.ByteWidth = size. cudaGraphicsMapFlagsWriteDiscard).MiscFlags = 0. __alignof(width)). cuParamSetf(createVertices.. cuGraphicsD3D11RegisterResource(&positionsVB_CUDA. __alignof(height)). D3D11_BUFFER_DESC bufferDesc.. 76 CUDA C Programming Guide Version 3. positionsVB_CUDA)). “createVertices. sizeof(positions)). offset += sizeof(width). device->CreateBuffer(&bufferDesc.BindFlags = D3D10_BIND_VERTEX_BUFFER. cuGraphicsResourceGetMappedPointer((void**)&positions. offset += sizeof(positions). ALIGN_UP(offset. cuGraphicsResourceSetMapFlags(positionsVB_CUDA. size_t num_bytes. bufferDesc. bufferDesc. cuParamSeti(createVertices. bufferDesc. cudaGraphicsRegisterFlagsNone).

. typically related to parameter validation. 1). 3.3. int threadsPerBlock = 16.9) and checking the error code returned by cuCtxSynchronize(). the size of the call stack can be queried using cuCtxGetLimit() and set using cuCtxSetLimit(). cuLaunchGrid(createVertices. it will be reported by some subsequent unrelated runtime function call. // Draw and present . this error code cannot possibly report any of the asynchronous errors that could occur on the device since the function returns before the device has completed the task. threadsPerBlock. } void releaseVB() { cuGraphicsUnregisterResource(positionsVB_CUDA). but for an asynchronous function (see Section 3. // Unmap vertex buffer cuGraphicsUnmapResources(1. subsequent runtime calls will pick up this context instead of creating a new one. offset). the error code only reports errors that occur on the host prior to executing the task. width / threadsPerBlock. CUDA C Programming Guide Version 3. The only way to check for asynchronous errors just after some asynchronous function call is therefore to synchronize just after the call by calling cuCtxSynchronize() (or by using any other synchronization mechanisms described in Section 3.2 77 .Chapter 3. } 3.11 Error Handling All driver functions return an error code.12 Call Stack On devices of compute capability 2.4 Interoperability between Runtime and Driver APIs An application can mix runtime API code with driver API code. cuFuncSetBlockShape(createVertices. if an asynchronous error occurs.6). positionsVB->Release(). Programming Interface offset += sizeof(height).3. cuParamSetSize(createVertices.. threadsPerBlock. If a context is created and made current via the driver API.3. height / threadsPerBlock). &positionsVB_CUDA.x. 0). 3.2.

because the driver API is backward compatible. and libraries (including the C runtime) compiled against a particular version of the driver API will not work on previous versions of the driver. cuCtxAttach() can be used to retrieve the context created during initialization. // Allocation using driver API cuMemAlloc(&devPtr. Programming Interface If the runtime is initialized (implicitly as mentioned in Section 3. size). this means that applications written using the driver API can invoke libraries written using the runtime API (such as CUFFT. size). 3. This is important.5 Versioning and Compatibility There are two version numbers that developers should care about when developing a CUDA application: The compute capability that describes the general specifications and features of the compute device (see Section 2. devPtr = (CUdeviceptr)d_data.Chapter 3.2 . specifically: All applications. plug-ins. The driver API is not forward compatible. d_data = (float*)devPtr. meaning that applications. CUBLAS.5) and the version of the CUDA driver API that describes the features supported by the driver API and runtime. float* d_data. plug-ins. which means that applications. …). plug-ins. and libraries on a system must use the same version of the CUDA driver API. It allows developers to check whether their application requires a newer driver than the one currently installed.  All plug-ins and libraries used by an application must use the same version of any libraries that use the runtime (such as CUFFT.  78 CUDA C Programming Guide Version 3. CUdeviceptr can be cast to regular pointers and vice-versa: CUdeviceptr devPtr.2).  All plug-ins and libraries used by an application must use the same version of the runtime. It is important to note that mixing and matching versions is not supported. and libraries (including the C runtime) compiled against a particular version of the driver API will continue to work on subsequent driver releases as illustrated in Figure 3-4. since only one version of the CUDA driver can be installed on a system. …). CUBLAS. // Allocation using runtime API cudaMalloc(&d_data. All functions from the device and version management sections of the reference manual can be used interchangeably. In particular. The version of the driver API is defined in the driver header file as CUDA_VERSION. This context can be used by subsequent driver API calls. Device memory can be allocated and freed using either API.

Programming Interface Apps. The Driver API is Backward.  Prohibited compute mode: No host thread can use the device. when using the driver API) at the same time.  Exclusive compute mode: Only one host thread can use the device at any given time. Figure 3-4. 3. When users initiate CUDA C Programming Guide Version 3. Libs & Plug-ins Apps.7 Mode Switches GPUs dedicate some DRAM memory to the so-called primary surface.0 Driver Compatible 1.. or by making current a context associated to the device.1 Driver Incompatible 2. but Not Forward Compatible 3. 1. Libs & Plug-ins ...Chapter 3.  Applications may query the compute mode of a device by calling cudaGetDeviceProperties() and checking the computeMode property or checking the CU_DEVICE_COMPUTE_MODE attribute using cuDeviceGetAttribute(). when using the runtime API. This means. which is used to refresh the display device whose output is viewed by the user. cudaSetValidDevices() can be used to set a device from a prioritized list of devices. that a host thread using the runtime API without explicitly calling cudaSetDevice() might be associated with a device other than device 0 if device 0 turns out to be in prohibited compute mode or in exclusive compute mode and used by another host thread.2 79 . Libs & Plug-ins Apps.0 Driver .. one can set any device in a system in one of the three following modes using NVIDIA‟s System Management Interface (nvidia-smi). which is a tool distributed as part of the Linux driver: Default compute mode: Multiple host threads can use the device (by calling cudaSetDevice() on this device. in particular.6 Compute Modes On Tesla solutions running Linux.

(Fullscreen graphics applications running with anti-aliasing enabled may require much more display memory for the primary surface. if the user changes the display resolution from 1280x1024x32-bit to 1600x1200x32-bit. Therefore. a mode switch results in any call to the CUDA runtime to fail and return an invalid context error. or hitting Ctrl+Alt+Del to lock the computer. Programming Interface a mode switch of the display by changing the resolution or bit depth of the display (using NVIDIA control panel or the Display control panel on Windows). If a mode switch increases the amount of memory needed for the primary surface. the system must dedicate 7.Chapter 3. other events that may initiate display mode switches include launching a full-screen DirectX application.68 MB to the primary surface rather than 5.2 .24 MB. For example. the amount of memory needed for the primary surface changes.) On Windows. hitting Alt+Tab to task switch away from a full-screen DirectX application. the system may have to cannibalize memory allocations dedicated to CUDA applications. 80 CUDA C Programming Guide Version 3.

but they have their own instruction address counter and register state and are therefore free to branch and execute independently.Chapter 4. it employs a unique architecture called SIMT (Single-Instruction. A half-warp is either the first or second half of a warp. Multiple-Thread) that is described in Section 4. second. The threads of a thread block execute concurrently on one multiprocessor.x. CUDA C Programming Guide Version 3. The way a block is partitioned into warps is always the same.2. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity.2 describe the architecture features of the streaming multiprocessor that are common to all devices. Hardware Implementation The CUDA architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). new blocks are launched on the vacated multiprocessors. and multiple thread blocks can execute concurrently on one multiprocessor. it leverages thread-level parallelism by using hardware multithreading as detailed in Section 4. more so than instruction-level parallelism within a single thread (instructions are pipelined. it partitions them into warps that get scheduled by a warp scheduler for execution. Section 2. To maximize utilization of its functional units. manages. each warp contains threads of consecutive. When a CUDA program on the host CPU invokes a kernel grid. 4. or fourth quarter of a warp.1 81 .4. The term warp originates from weaving.1 and 4.1 SIMT Architecture The multiprocessor creates. Sections G. To manage such a large amount of threads.2 describes how thread IDs relate to thread indices in the block. but unlike CPU cores they are executed in order and there is no branch prediction and no speculative execution).1. When a multiprocessor is given one or more thread blocks to execute. schedules. Individual threads composing a warp start together at the same program address.1 provide the specifics for devices of compute capabilities 1. A quarter-warp is either the first. the first parallel thread technology.x and 2. third. Sections 4. respectively. A multiprocessor is designed to execute hundreds of threads concurrently. As thread blocks terminate. increasing thread IDs with the first warp containing thread 0. and executes threads in groups of 32 parallel threads called warps.1 and G.3.

4. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. different warps execute independently regardless of whether they are executing common or disjoint code paths. the threads converge back to the same execution path. the number of serialized writes that occur to that location varies depending on the compute capability of the device (see Sections G. and G. Vector architectures.2 . The number of blocks and warps that can reside and be processed together on the multiprocessor for a given kernel depends on the amount of registers and shared memory used by the kernel and the amount of registers and shared memory available on the multiprocessor. modify. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. modifies.Chapter 4. SIMT enables programmers to write thread-level parallel code for independent. Hardware Implementation A warp executes one common instruction at a time. the programmer can essentially ignore the SIMT behavior.3. and at every instruction issue time.3. These limits as well the amount of registers and shared memory available on the multiprocessor 82 CUDA C Programming Guide Version 3. but the order in which they occur is undefined.2.2.2 Hardware Multithreading The execution context (program counters. If an atomic instruction (see Section B. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance.3. 4. each read. etc) for each warp processed by a multiprocessor is maintained on-chip during the entire lifetime of the warp. Switching from one execution context to another therefore has no cost. and a parallel data cache or shared memory that is partitioned among the thread blocks.11) executed by a warp reads. write to that location occurs and they are all serialized. as well as data-parallel code for coordinated threads. a warp scheduler selects a warp that has threads ready to execute its next instruction (active threads) and issues the instruction to those threads. In practice. For the purposes of correctness. however. Branch divergence occurs only within a warp. If threads of a warp diverge via a data-dependent conditional branch. whereas SIMT instructions specify the execution and branching behavior of a single thread. The SIMT architecture is akin to SIMD (Single Instruction. the warp serially executes each branch path taken.3) and which thread performs the final write is undefined.4. and writes to the same location in global memory for more than one of the threads of the warp. There are also a maximum number of resident blocks and a maximum number of resident warps per multiprocessor. A key difference is that SIMD vector organizations expose the SIMD width to the software. so full efficiency is realized when all 32 threads of a warp agree on their execution path. registers. on the other hand. require the software to coalesce loads into vectors and manage divergence manually. disabling threads that are not on that path. In contrast with SIMD vector machines. each multiprocessor has a set of 32-bit registers that are partitioned among the warps. In particular. scalar threads. and when all paths complete. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. G. G.

GW )  Wsize  Rk .x only). and 512 for devices of compute capability 1.1) Wsize T is the number of threads per block. one for each GPU in the SLI configuration and deal with the fact that a different GPU is used for rendering by the Direct3D device at every frame. The total amount of shared memory Sblock in bytes allocated for a block is as follows:  S block  ceil (S k .3 Multiple Devices In a system with multiple GPUs.1.x: Rblock  ceil (ceil (Wblock . equal to 256 for devices of compute capability 1.x. Second. y) is equal to x rounded up to the nearest multiple of y. The total number of registers Rblock allocated for a block is as follows: For devices of compute capability 1.  GT is the thread allocation granularity. The total number of warps Wblock in a block is as follows: Wblock  ceil (  T . There are however special considerations as described below when the system is in SLI mode.3. Given this information the application will typically map Direct3D resources to the CUDA context corresponding to the CUDA device returned by cuD3D[9|10|11]GetDevices() when the deviceList parameter is set to CUDA C Programming Guide Version 3. and 64 for devices of compute capability 2. The application can use the cuD3D[9|10|11]GetDevices() set of calls to identify the CUDA device handle(s) for the GPU(s) that are performing the rendering in the current and next frame. GT ) For devices of compute capability 2.  Wsize is the warp size. which is equal to 32. First.2 83 .0 and 1.  ceil(x. which is equal to 512 for devices of compute capability 1. an allocation in one CUDA device on one GPU will consume memory on other GPUs that are part of the SLI configuration of the Direct3D device. GT )  Wblock GW is the warp allocation granularity.x and 128 for devices of compute capability 2.x: Rblock  ceil ( Rk  Wsize . all CUDA-enabled GPUs are accessible via the CUDA driver and runtime as separate devices. the kernel will fail to launch.  GS is the shared memory allocation granularity. applications have to create multiple CUDA contexts. If there are not enough registers or shared memory available per multiprocessor to process at least one block.  Rk is the number of registers used by the kernel.x. GS ) Sk is the amount of shared memory used by the kernel in bytes.  4. allocations may fail earlier than otherwise expected. Because of this. equal to 2 (compute capability 1.2 and 1.Chapter 4: Hardware Implementation are a function of the compute capability of the device and are given in Appendix G.

See Sections 3.2 and 3.2 .Chapter 4.3. 84 CUDA C Programming Guide Version 3.2. Hardware Implementation CU_D3D10_DEVICE_LIST_CURRENT_FRAME.7.2 for details on how to use CUDA-Direct3D interoperability.10.

2. the devices.  Optimize memory usage to achieve maximum memory throughput. for example. Performance Guidelines 5. Optimization efforts should therefore be constantly directed by measuring and monitoring the performance limiters. It should assign to each processor the type of work it does best: serial workloads to the host. optimizing instruction usage of a kernel that is mostly limited by memory accesses will not yield any significant performance gain.1 Overall Performance Optimization Strategies Performance optimization revolves around three basic strategies: Maximize parallel execution to achieve maximum utilization.2 Maximize Utilization To maximize utilization the application should be structured in a way that it exposes as much parallelism as possible and efficiently maps this parallelism to the various components of the system to keep them busy most of the time.  5. parallel workloads to the devices. For the parallel workloads. by using asynchronous functions calls and streams as described in Section 3.2. at points in the algorithm where parallelism is broken because some threads need to synchronize in order to share data with each other.1 85 . for example using the CUDA profiler.Chapter 5.  Optimize instruction usage to achieve maximum instruction throughput. Also. the application should maximize parallel execution between the host.6. Which strategies will yield the best performance gain for a particular portion of an application depends on the performance limiters for that portion. 5. in which case CUDA C Programming Guide Version 3. and the bus connecting the host to the devices. comparing the floating-point operation throughput or memory throughput – whichever makes more sense – of a particular kernel to the corresponding peak theoretical throughput of the device indicates how much room for improvement there is for the kernel.1 Application Level At a high level. there are two cases: Either these threads belong to the same block.

Performance Guidelines they should use __syncthreads() and share data through shared memory within the same kernel invocation. and issues the instruction to the active threads of the warp.4.  L (rounded up to nearest integer) for devices of compute capability 2.1. At every instruction issue time. 5.3 Multiprocessor Level At an even lower level.4. a warp scheduler selects a warp that is ready to execute its next instruction. For devices of compute capability 2. when latency is completely “hidden”.1 for the throughputs of various arithmetic instructions).2. For devices of compute capability 1. assuming maximum throughput for all instructions. multiple kernels can execute concurrently on a device. as mentioned in Section G.4. a GPU multiprocessor relies on thread-level parallelism to maximize utilization of its functional units.2 .x. and full utilization is achieved when all warp schedulers always have some instruction to issue for some warp at every clock cycle during that latency period.1 since a multiprocessor issues a pair of instructions per warp over 2 clock cycles for 2 warps at a time.Chapter 5. in which case they must share data through global memory using two separate kernel invocations. or in other words. The number of clock cycles it takes for a warp to be ready to execute its next instruction is called the latency. so the kernel should be launched with at least as many thread blocks as there are multiprocessors in the device. so maximum utilization can also be achieved by using streams to enable enough kernels to execute concurrently as described in Section 3. one for writing to and one for reading from global memory. only one kernel can execute on a device at one time. or they belong to different blocks. Utilization is therefore directly linked to the number of resident warps. As described in Section 4.6. Its occurrence should therefore be minimized by mapping the algorithm to the CUDA programming model in such a way that the computations that require inter-thread communication are performed within a single thread block as much as possible.x since a multiprocessor issues one instruction per warp over 4 clock cycles. as mentioned in Section G.1.  2L (rounded up to nearest integer) for devices of compute capability 2.  86 CUDA C Programming Guide Version 3. The number of instructions required to hide a latency of L clock cycles depends on the respective throughputs of these instructions (see Section 5.1.2.2. it is: L/4 (rounded up to nearest integer) for devices of compute capability 1.x. the application should maximize parallel execution between the multiprocessors of a device. 5.3. as mentioned in Section G.2 Device Level At a lower level.2. The second case is much less optimal since it adds the overhead of extra kernel invocations and global memory traffic. if any.0 since a multiprocessor issues one instruction per warp over 2 clock cycles for 2 warps at a time. the application should maximize parallel execution between the various functional units within a multiprocessor.

the amount of shared memory used to pass the kernel‟s arguments (see Section B. Register.1. Execution time varies depending on the instruction. The number of blocks and warps residing on each multiprocessor for a given kernel call depends on the execution configuration of the call (Section B. then to hide latencies of about 600 clock cycles. The number of warps required to keep the warp schedulers busy during such high latency periods depends on the kernel code. the latency is much higher: 400 to 800 clock cycles.16). more warps are required if the ratio of the number of instructions with no off-chip memory operands (i.4). and constant memory usages are reported by the compiler when compiling with the --ptxas-options=-v option. the two instructions issued every other cycle are for two different warps. in general.x and about 40 for devices of compute capability 2.e. arithmetic instructions most of the time) to the number of instructions with off-chip memory operands is low (this ratio is commonly called the arithmetic intensity of the program). If some input operand resides in off-chip memory. In the case of a back-to-back register dependency (i.1.x. If this ratio is 15. some of the input operands are written by some previous instruction(s) whose execution has not completed yet. Another reason a warp is not ready to execute its next instruction is that it is waiting at some memory fence (Section B. the latency is equal to the execution time of the previous instruction and the warp scheduler must schedule instructions for different warps during that time. as warps from different blocks do not need to wait for each other at synchronization points. The most common reason a warp is not ready to execute its next instruction is that the instruction‟s input operands are not yet available. shared.x.x and 22 warps for devices of compute capability 2. for example. and for devices of compute capability 1. which translates to 6 warps for devices of compute capability 1.e.Chapter 5. To assist programmers in choosing thread block size based on register and shared memory requirements. the CUDA Software Development Kit provides a spreadsheet. the four instructions issued every other cycle are two pairs for two different warps. Performance Guidelines For devices of compute capability 2. the memory resources of the multiprocessor.e.2.x.2 87 . about 10 warps are required for devices of compute capability 1. For devices of compute capability 2. The total amount of shared memory required for a block is equal to the sum of the amount of statically allocated shared memory. but it is typically about 22 clock cycles. for devices of compute capability 1. If all input operands are registers. called the CUDA Occupancy Calculator. i. Having multiple resident blocks per multiprocessor can help reduce idling in this case. local.5) or synchronization point (Section B. A synchronization point can force the multiprocessor to idle as more and more warps wait for other warps in the same block to complete execution of instructions prior to the synchronization point. and the resource requirements of the kernel as described in Section 4. if a CUDA C Programming Guide Version 3. the amount of dynamically allocated shared memory. For example.2. latency is caused by register dependencies.6). each pair being for the same warp.0. some input operand is written by the previous instruction). The number of registers used by a kernel can have a significant impact on the number of resident warps. where occupancy is defined as the ratio of the number of resident warps to the maximum number of resident warps (given in Appendix G for various compute capabilities).

2) and the number of instructions to a minimum. which exactly matches the number of registers available on the multiprocessor. a typical programming pattern is to stage data coming from device memory into shared memory. devices of compute capability 1.2 and higher) and each long long variable uses two registers. since these have much lower bandwidth than data transfers between global memory and the device.3 Maximize Memory Throughput The first step in maximizing overall memory throughput for the application is to minimize data transfers with low bandwidth. in other words. However. the compiler attempts to minimize register usage while keeping register spilling (see Section 5. Each double variable (on devices that supports native double precision. Shared memory is equivalent to a user-managed cache: The application explicitly allocates and accesses it. 5.x. which depends on the compute capability of the device.3. 32 warps) can reside on the multiprocessor since they require 2x512x16 registers. as detailed in Section 5. which are more registers than are available on the multiprocessor.e. to have each thread of a block: Load data from device memory to shared memory.3.17. But as soon as the kernel uses one more register. devices of compute capability 1. 16 warps) can be resident since two blocks would require 2x512x17 registers.  88 CUDA C Programming Guide Version 3.e. texture cache and constant cache available on all devices). Performance Guidelines kernel uses 16 registers and each block has 512 threads and requires very little shared memory. then two blocks (i.1. as well as on the number of multiprocessors and memory bandwidth of the device. Register usage can be controlled using the -maxrregcount compiler option or launch bounds as described in Section B.2. As illustrated in Section 3. Applications can also parameterize execution configurations based on register file size and shared memory size. Therefore.  Synchronize with all the other threads of the block so that each thread can safely read shared memory locations that were populated by different threads.2 and higher have at least twice as many registers per multiprocessor as devices with lower compute capability. That means minimizing data transfers between the host and the device. only one block (i. That also means minimizing data transfers between global memory and the device by maximizing use of on-chip memory: shared memory and caches (i.e.  Process the data in shared memory. Experimentation is therefore recommended.2. L1/L2 caches available on devices of compute capability 2. The effect of execution configuration on performance for a given kernel call generally depends on the kernel code.e. The number of threads per block should be chosen as a multiple of the warp size to avoid wasting computing resources with under-populated warps as much as possible.2. all of which can be queried using the runtime or driver API (see reference manual).2 .  Synchronize again if necessary to make sure that shared memory has been updated with the results.Chapter 5. i.

using mapped page-locked memory instead of explicit copies between device and host memory can be a win for performance. the same on-chip memory is used for both L1 and shared memory.  The throughput of memory accesses by a kernel can vary by an order of magnitude depending on access pattern for each type of memory. Performance Guidelines Write the results back to device memory.2 89 .2.3. a traditional hardware-managed cache is more appropriate to exploit data locality. As mentioned in Section G.1.x. constant.3.1).3. so non-optimal global memory accesses have a higher impact on performance. Assuming that they are and that the mapped memory is read or written only once. 5.2.Chapter 5. This optimization is especially important for global memory accesses as global memory bandwidth is low. operated on by the device. these memory accesses must be coalesced as with accesses to global memory (see Section 5. and how much of it is dedicated to L1 versus shared memory is configurable for each kernel call.5. Also. global.3.3).4. batching many small transfers into a single large transfer always performs better than making each transfer separately. local. shared. 5. any copy between host and device memory is superfluous and mapped pagelocked memory should be used instead.4.2.3.5.1. for devices of compute capability 2.e. On integrated systems where device memory and host memory are physically the same. even if that means running kernels with low parallelism computations. when using mapped page-locked memory (Section 3. or texture memory) might need to be re-issued multiple times depending on the CUDA C Programming Guide Version 3. Data transfers are implicitly performed each time the kernel accesses the mapped memory.1 Data Transfer between Host and Device Applications should strive to minimize data transfer between the host and the device. In addition.2. 5. because of the overhead associated with each transfer. On systems with a front-side bus.2. there is no need to allocate any device memory and explicitly copy data between device and host memory. 5.3. The next step in maximizing memory throughput is therefore to organize memory accesses as optimally as possible based on the optimal memory access patterns described in Sections 5. One way to accomplish this is to move more code from the host to the device. and destroyed without ever being mapped by the host or copied to host memory. for which global memory accesses are data-dependent). For maximum performance.3.2.2. Intermediate data structures may be created in device memory.4. Applications may query whether a device is integrated or not by calling cudaGetDeviceProperties() and checking the integrated property or checking the CU_DEVICE_ATTRIBUTE_INTEGRATED attribute using cuDeviceGetAttribute(). and 5.2 Device Memory Accesses An instruction that accesses addressable memory (i.1.3.g. For some applications (e. higher performance for data transfers between host and device is achieved by using page-locked host memory as described in Section 3.4.

For example.2. the requirements on the distribution of the addresses across the threads to get any coalescing at all are very strict.2. It is therefore recommended to use types that meet this requirement for data that resides in global memory. To maximize global memory throughput. 2. so data locality is exploited to reduce impact on throughput.2 .0 and 1.2. 64-. Using data types that meet the size and alignment requirement detailed in Section 5. for example.1.2. for global memory.2 and G. These memory transactions must be naturally aligned: Only the 32-. 4.2 and G.3.e. if a 32-byte memory transaction is generated for each thread‟s 4-byte access.3.1 Size and Alignment Requirement Global memory instructions support reading or writing words of size equal to 1.3. the more scattered the addresses are. or 16 bytes and the data is naturally aligned (i. or 128-byte memory transactions.4. reducing the instruction throughput accordingly. the access compiles to multiple instructions with interleaved access patterns that prevent these instructions from fully coalescing.1.   5. it coalesces the memory accesses of the threads within the warp into one or more of these memory transactions depending on the size of the word accessed by each thread and the distribution of the memory addresses across the threads. its address is a multiple of that size). whose first address is a multiple of their size) can be read or written by memory transactions. 8. throughput is divided by 8.2 give more details on how global memory accesses are handled for various compute capabilities. 64-.3. 2. How the distribution affects the instruction throughput this way is specific to each type of memory and described in the following sections. when accessing a two-dimensional array as described in Section 5. Performance Guidelines distribution of the memory addresses across the threads within the warp. the more unused words are transferred in addition to the words accessed by the threads.1.  Padding data in some cases.3.4. 4. the memory transactions are cached. it is therefore important to maximize coalescing by: Following the most optimal access patterns based on Sections G. If this size and alignment requirement is not fulfilled. Sections G.Chapter 5. They are much more relaxed for devices of higher compute capabilities. or 128-byte segments of device memory that are aligned to their size (i. For example. 5.3.2. For devices of compute capability 2.2. the more reduced the throughput is. or 16 bytes. Any access (via a variable or a pointer) to data residing in global memory compiles to a single global memory instruction if and only if the size of the data type is 1. When a warp executes an instruction that accesses global memory. 8. How many transactions are necessary and how throughput is ultimately affected varies with the compute capability of the device.1 Global Memory Global memory resides in device memory and device memory is accessed via 32-.1.x.1. the more transactions are necessary. For devices of compute capability 1. as a general rule. 90 CUDA C Programming Guide Version 3. In general.e.

ty) uses the following address to access one element of a 2D array of width width. 5.2 Local Memory Local memory accesses only occur for some automatic variables as mentioned in Section B. in which case the starting address of each array is offset from the block‟s starting address. }. Any address of a variable residing in global memory or returned by one of the memory allocation routines from the driver or runtime API is always aligned to at least 256 bytes. the size and alignment requirements can be enforced by the compiler using the alignment specifiers __align__(8) or __align__(16). both the width of the thread block and the width of the array must be a multiple of the warp size (or only half the warp size for devices of compute capability 1.2 Two-Dimensional Arrays A common global memory access pattern is when each thread of index (tx.2. float z.3. 5. or struct __align__(16) { float x.3.1): BaseAddress + width * ty + tx For these accesses to be fully coalesced. whereby the allocations of multiple arrays (with multiple calls to cudaMalloc() or cuMemAlloc()) is replaced by the allocation of a single large block of memory partitioned into multiple arrays.x).2.3. A typical case where this might be easily overlooked is when using some custom global memory allocation scheme. float y. located at address BaseAddress of type type* (where type meets the requirement described in Section 5. The cudaMallocPitch() and cuMemAllocPitch() functions and associated memory copy functions described in the reference manual enable programmers to write non-hardware-dependent code to allocate arrays that conform to these constraints. so special care must be taken to maintain alignment of the starting address of any value or array of values of these types. Automatic variables that the compiler is likely to place in local memory are: CUDA C Programming Guide Version 3.1. For structures.1 like float2 or float4. }. Performance Guidelines The alignment requirement is automatically fulfilled for the built-in types of Section B. this means that an array whose width is not a multiple of this size will be accessed much more efficiently if it is actually allocated with a width rounded up to the closest multiple of this size and its rows padded accordingly. In particular.2 91 .Chapter 5.2.1.4. float y. such as struct __align__(8) { float x.3. Reading non-naturally aligned 8-byte or 16-byte words produces incorrect results (off by a few words).2.

there is a bank conflict and the access has to be serialized. 5. so local memory accesses have same high latency and low bandwidth as global memory accesses and are subject to the same requirements for memory coalescing as described in Section 5. Accesses are therefore fully coalesced as long as all threads in a warp access the same relative address (e.1. it is therefore important to understand how memory addresses map to memory banks in order to schedule the memory requests so as to minimize bank conflicts. called banks.4. However.3 and G.local and st. To achieve high bandwidth.4.3. yielding an overall bandwidth that is n times as high as the bandwidth of a single module. On devices of compute capability 2. if two addresses of a memory request fall in the same memory bank. The hardware splits a memory request with bank conflicts into as many separate conflict-free requests as necessary. 92 CUDA C Programming Guide Version 3. accessing shared memory is fast as long as there are no bank conflicts between the threads. 5. decreasing throughput by a factor equal to the number of separate memory requests.1. the shared memory space is much faster than the local and global memory spaces.2.  The local memory space resides in device memory.Chapter 5.2.3.2. same member in a structure variable).  Large structures or arrays that would consume too much register space.3. Any memory read or write request made of n addresses that fall in n distinct memory banks can therefore be serviced simultaneously. Note that some mathematical functions have implementation paths that might access local memory.local mnemonics.  Any variable if the kernel uses more registers than available (this is also known as register spilling). the initial memory request is said to cause n-way bank conflicts.g. This is described in Sections G.4.3 for devices of compute capability 1.4 Constant Memory The constant memory space resides in device memory and is cached in the constant cache mentioned in Sections G. subsequent compilation phases might still decide otherwise though if they find it consumes too much register space for the targeted architecture: Inspection of the cubin object using cuobjdump will tell if this is the case. Local memory is however organized such that consecutive 32-bit words are accessed by consecutive thread IDs.x.2 . for all threads of a warp. local memory accesses are always cached in L1 and L2 in the same way as global memory accesses (see Section G.2). as detailed below. respectively.x. Performance Guidelines Arrays for which it cannot determine that they are indexed with constant quantities.local mnemonic and accessed using the ld. the compiler reports total local memory usage per kernel (lmem) when compiling with the --ptxas-options=-v option. same index in an array variable.3 Shared Memory Because it is on-chip.3. which can be accessed simultaneously.1 and G. In fact. shared memory is divided into equally-sized memory modules. To get maximum performance.x and 2. Even if it has not. If the number of separate memory requests is n. Also. Inspection of the PTX assembly code (obtained by compiling with the –ptx or -keep option) will tell if a variable has been placed in local memory during the first compilation phases as it will be declared using the .3.

by optimizing out synchronization points whenever possible as described in Section 5. otherwise it just costs one read from texture cache.  Minimize divergent warps caused by control flow instructions as detailed in Section 5.3.3.  Reduce the number of instructions. For a warp size of 32.0] (see Section 3. decreasing throughput by a factor equal to the number of separate requests.2. higher bandwidth can be achieved providing that there is locality in the texture fetches or surface reads (this is less likely for devices of compute capability 2. this includes trading precision for speed when it does not affect the end result. Performance Guidelines For devices of compute capability 1.  5.Chapter 5. for example.1).3. or at the throughput of device memory otherwise.0] or [-1. The resulting requests are then serviced at the throughput of the constant cache in case of a cache hit. a constant memory request for a warp is first split into two requests.  Addressing calculations are performed outside the kernel by dedicated units. throughputs are given in number of operations per clock cycle per multiprocessor.3. Reading device memory through texture or surface fetching present some benefits that can make it an advantageous alternative to reading device memory from global or constant memory: If the memory reads do not follow the access patterns that global or constant memory reads must respect to get good performance (see Sections 5. such as using intrinsic instead of regular functions (intrinsic functions are listed in Section C. it is designed for streaming fetches with a constant latency.0.4 Maximize Instruction Throughput To maximize instruction throughput the application should: Minimize the use of arithmetic instructions with low throughput. 1.1.4. Therefore.x.2. A request is then split into as many separate requests as there are different memory addresses in the initial request.5 Texture and Surface Memory The texture and surface memory spaces reside in device memory and are cached in texture cache. 1. 5.2. The texture cache is optimized for 2D spatial locality. so threads of the same warp that read texture or surface addresses that are close together in 2D will achieve best performance.  Packed data may be broadcast to separate variables in a single operation.  CUDA C Programming Guide Version 3. a cache hit reduces DRAM bandwidth demand but not fetch latency. if T is the number of operations per clock cycle. the instruction throughput is one instruction every 32/T clock cycles.2). one for each half-warp.2 93 .2.0.3 or by using restricted pointers as described in Section E. one instruction results in 32 operations.2. Also.4.4.1 and 5. that are issued independently. or flushing denormalized numbers to zero.  8-bit and 16-bit integer input data may be optionally converted to 32-bit floating-point values in the range [0. single-precision instead of double-precision.x given that global memory reads are cached on these devices). so a texture fetch or surface read costs one memory read from device memory only on a cache miss.4). In this section.

Table 5-1. and 94 CUDA C Programming Guide Version 3. sine (__sinf). reciprocal square root. there can be multiple code paths depending on input. multiply. device_functions.1 48 4 48 16 32-bit floating-point add.x and devices of compute capability 2.x Compute Capability 2. Throughput of Native Arithmetic Instructions (Operations per Clock Cycle per Multiprocessor) Compute Capability 1.Chapter 5.2 .4. multiply. base-2 exponential (exp2f). logical operation 32-bit integer shift. multiply-add. Similarly. They must be multiplied by the number of multiprocessors in the device to get throughput for the whole device. The implementation may be different for devices of compute capability 1. …). The implementation of some functions are readily available on the CUDA header files (math_functions.0 32 16 32 16 Compute Capability 2. and the number of native instructions after compilation may fluctuate with every compiler version.1 Arithmetic Instructions Table 5-1 gives the throughputs of the arithmetic instructions that are natively supported in hardware for devices of various compute capabilities. compare 32-bit integer multiply. sum of absolute difference 24-bit integer multiply (__[u]mul24) 32-bit floating-point reciprocal. 5. In general. code compiled with -prec-div=false (less precise division) tends to have higher performance code than code compiled with -prec-div=true. Performance Guidelines All throughputs are for one multiprocessor. For complicated functions.h. multiply-add 32-bit integer add. base-2 logarithm (__log2f).h. cosine (__cosf) Type conversions 8 1 8 8 Multiple instructions 8 16 Multiple instructions 16 Multiple instructions 2 4 8 8 16 16 Other instructions and functions are implemented on top of the native instructions.x. code compiled with -ftz=true (denormalized numbers are flushed to zero) tends to have higher performance than code compiled with -ftz=false. multiply-add 64-bit floating-point add. cuobjdump can be used to inspect a particular implementation in a cubin object.

Single-Precision Floating-Point Square Root Single-precision floating-point square root is implemented as a reciprocal square root followed by a reciprocal instead of a reciprocal square root followed by a multiplication so that it gives correct results for 0 and infinity.x.0/sqrtf() into rsqrtf() only when both reciprocal and square root are approximate.0f for the singleprecision functions. Single-Precision Floating-Point Division __fdividef(x.u].2. (i.0 for the double-precision functions.x and 2 operations per clock cycle for devices of compute capability 2. and __fmaf_r[n. the argument reduction code (see math_functions. with -prec-div=false and -prec-sqrt=false). As the slow path requires more registers than the fast path.1) compile to tens of instructions for devices of compute capability 1. Single-Precision Floating-Point Reciprocal Square Root To preserve IEEE-754 semantics the compiler can optimize 1.u] (see Section C. At present. and 44 bytes are used by doubleprecision functions.x. The slow path is used for arguments large in magnitude and consists of lengthy computations required to achieve correct results over the entire argument range. The fast path is used for arguments sufficiently small in magnitude and essentially consists of a few multiply-add operations. Sine and Cosine sinf(x).2.1) provides faster single-precision floating- point division than the division operator.2. At present.Chapter 5. The nvcc user manual describes these compilation flags in more details. and less than 2147483648. __fmul_r[d. CUDA C Programming Guide Version 3. y) (see Section C. 28 bytes of local memory are used by single-precision functions. Single-Precision Floating-Point Addition and Multiplication Intrinsics __fadd_r[d. an attempt has been made to reduce register pressure in the slow path by storing some intermediate variables in local memory.u]. respectively. its throughput is 1 operation per clock cycle for devices of compute capability 1. the argument reduction code for the trigonometric functions selects the fast path for arguments whose magnitude is less than 48039.2 95 . but map to a single native instruction for devices of compute capability 2.d. However. the exact amount is subject to change. Therefore. sincosf(x). More precisely. tanf(x). which may affect performance because of local memory high latency and bandwidth (see Section 5.2). It is therefore recommended to invoke rsqrtf() directly where desired. and corresponding double- precision instructions are much more expensive and even more so if the argument x is large in magnitude.z. cosf(x).h for implementation) comprises two code paths referred to as the fast path and the slow path. Performance Guidelines code compiled with -prec-sqrt=false (less precise square root) tends to have higher performance than code compiled with -prec-sqrt=true.3.x.e.

__clzll.x and __brevll and __popcll to just a few. the threads converge back to the same execution path.3) compile to tens of instructions for devices of compute capability 1.x.x.2 96 . Using __[u]mul24 instead of the 32-bit multiplication operator whenever possible usually improves performance for instruction bound kernels. 24-bit integer multiplication is natively supported however via the __[u]mul24 intrinsic (see Section C. do.Chapter 5. for. __[u]mul24 is therefore implemented using multiple instructions and should not be used.x than for devices of compute capability 1.e. They can be replaced with bitwise operations in some cases: If n is a power of 2. but __brev and __popc map to a single instruction for devices of compute capability 2.x. 1.0f. but 24-bit integer multiplication is not. 32-bit integer multiplication is natively supported. It can have the opposite effect however in cases where the use of __[u]mul24 inhibits compiler optimizations.  5.141592653589793f.e.x. __brev. 32-bit integer multiplication is implemented using multiple instructions as it is not natively supported. the throughput of these trigonometric functions is lower by one order of magnitude when the slow path reduction is required as opposed to the fast path reduction.3). below 20 instructions on devices of compute capability 2. __clz. CUDA C Programming Guide Version 3. those constants defined without any type suffix) used as input to single-precision floating-point computations (as mandated by C/C++ standards). switch. If this happens.x. and __ffsll (see Section C. 0. Integer Arithmetic On devices of compute capability 1.4.2 Control Flow Instructions Any flow control instruction (if. When all the different execution paths have completed. the compiler will perform these conversions if n is literal. This last case can be avoided by using single-precision floating-point constants.3) compile to fewer instructions for devices of compute capability 2. and __popcll (see Section C. On devices of compute capability 2. the compiler must insert conversion instructions.  Double-precision floating-point constants (i. __popc. introducing additional execution cycles. This is the case for: Functions operating on variables of type char or short whose operands generally need to be converted to int.x. Integer division and modulo operation are costly: tens of instructions on devices of compute capability 1. defined with an f suffix such as 3.2. to follow different execution paths). Type Conversion Sometimes. while) can significantly impact the effective instruction throughput by causing threads of the same warp to diverge (i.5f.2.2. increasing the total number of instructions executed for this warp. __brevll. the different executions paths have to be serialized. __ffs. (i/n) is equivalent to (i>>log2(n)) and (i%n) is equivalent to (i&(n-1)). Performance Guidelines Due to the lengthy computations and use of local memory in the slow path.

Instructions with a false predicate do not write results. otherwise it is 4. Note that __syncthreads() can impact performance by forcing the multiprocessor to idle as detailed in Section 5. Instead. Performance Guidelines To obtain best performance in cases where the control flow depends on the thread ID.x and 16 operations per clock cycle for devices of compute capability 2. no warp can ever diverge. for example. When using branch predication none of the instructions whose execution depends on the controlling condition gets skipped. Because a warp executes one common instruction at a time. In this case. In the following code sample.1. // myArray is an array of integers located in global or shared // memory __global__ void MyKernel(int* result) { int tid = threadIdx.2. __syncthreads(). the controlling condition should be written so as to minimize the number of divergent warps.e. Without synchronization. and also do not evaluate addresses or read operands.. only the instructions with a true predicate are actually executed.3 Synchronization Instruction Throughput for __syncthreads() is 8 operations per clock cycle for devices of compute capability 1. both calls to __syncthreads() are required to get the expected result (i. depending on whether the memory read occurs before or after the memory write from myArray[tid + 1] = 2. any of the two references to myArray[tid] could return either 2 or the value initially stored in myArray.2).3. In these cases. This is possible because the distribution of the warps across the block is deterministic as mentioned in Section 4. int ref1 = myArray[tid]. each of them is associated with a per-thread condition code or predicate that is set to true or false based on the controlling condition and although each of these instructions gets scheduled for execution.2 97 . CUDA C Programming Guide Version 3. myArray[tid + 1] = 2. . A trivial example is when the controlling condition only depends on (threadIdx / warpSize) where warpSize is the warp size. as detailed below. threads within a warp are implicitly synchronized and this can sometimes be used to omit __syncthreads() for better performance. The compiler replaces a branch instruction with predicated instructions only if the number of instructions controlled by the branch condition is less or equal to a certain threshold: If the compiler determines that the condition is likely to produce many divergent warps. no warp diverges since the controlling condition is perfectly aligned with the warps.4. this threshold is 7. the compiler may unroll loops or it may optimize out if or switch statements by using branch predication instead.Chapter 5. result[i] = 2 * myArray[i] for i > 0).. __syncthreads().x.x. Sometimes. 5. The programmer can also control loop unrolling using the #pragma unroll directive (see Section E.

threads are guaranteed to belong to the same warp. . result[tid] = ref1 * ref2..Chapter 5.. in the following slightly modified code sample..5.x.2 .. } . 98 CUDA C Programming Guide Version 3. . if (tid < warpSize) { int ref1 = myArray[tid]. Performance Guidelines int ref2 = myArray[tid].. myArray[tid + 1] = 2. int ref2 = myArray[tid].2. } Simply removing the __syncthreads() is not enough however. result[tid] = ref1 * ref2. myArray must also be declared as volatile as described in Section B. } However. // myArray is an array of integers located in global or shared // memory __global__ void MyKernel(int* result) { int tid = threadIdx. so that there is no need for any __syncthreads()..

8800 GTX GeForce 9800 GT. GTX 275 GeForce GTX 260 GeForce 9800 GX2 GeForce GTS 250. GTX 260M.0 2. CUDA-Enabled GPUs Table A-1 lists all CUDA-enabled devices with their compute capability. number of multiprocessors.0 2. GTX 480M GeForce GTX 295 GeForce GTX 285. GTS 150. 9800M GTX 2.0 1. GTX 460M GeForce GT 445M GeForce GT 435M.1 99 .1 2.1 1.0 1.1 2. GT 425M. GT 420M GeForce GT 415M GeForce GTX 580 GeForce GTX 480 GeForce GTX 470 GeForce GTX 465. and Number of CUDA Cores Compute Capability Number of Multiprocessors 7 6 4 3 2 1 16 15 14 11 2x30 30 24 2x16 16 Number of CUDA Cores 336 288 192 144 96 48 512 480 448 352 2x240 240 192 2x128 128 GeForce GTX 460 GeForce GTX 470M GeForce GTS 450. Number of Multiprocessors. CUDA-Enabled Devices with Compute Capability.1 1. 9800 GTX+.1 16 14 128 112 CUDA C Programming Guide Version 3. as well as the clock frequency and the total amount of device memory. These. Table A-1. can be queried using the runtime or driver API (see reference manual). GTX 280M GeForce 8800 Ultra.Appendix A.0 2. 8800 GTS 512.3 1. GTX 285M. 8800 GT.1 2.1 2.1 2.3 1. GTX 280. and number of CUDA cores.1 2.3 1. 9800 GTX.

8300 mGPU. 9800M GT GeForce 8800 GTS GeForce GT 335M GeForce 9600 GT.0 2. G210M.3 1.1 1.3 1.1 2. 9100M G. 8600 GT. 8100 mGPU.2 1. GTS 350M GeForce GT 130. 9200M GS. 8400M G.2 1.1 1. 9300 mGPU. 310M. 9300M G. 8600M GS GeForce 210. 9400 mGPU. 9500 GT.2 .0 2.1 Number of Multiprocessors 12 12 Number of CUDA Cores 96 96 1.3 1. 8600M GT.0 2. 9600M GS. 8500 GT.Appendix A.1 2.3 1. 9800M GTS GeForce GT 220. 305M GeForce G100. GT 325M. 8200 mGPU.1 12 9 8 6 6 4 96 72 64 48 48 32 1. 8700M GT.1 1. 8400M GS. GT 230M GeForce GT 120.0 1. 8800 GS. 8600 GTS. GT 330M. 8800M GTS. GTS 250M. CUDA-Enabled GPUs Compute Capability GeForce GT 240.0 1.2 1.0 1 14 4x30 30 4x16 2x16 16 4 2 14 11 10 8 2x30 4x14 4x16 2x16 30 24 2x14 16 16 8 448 4x240 240 4x128 2x128 128 192 96 448 352 320 256 2x240 4x112 4x128 2x128 240 192 2x112 128 128 100 CUDA C Programming Guide Version 3. GTS 360M. 9700M GT.1 1. G105M Tesla C2050 Tesla S1070 Tesla C1060 Tesla S870 Tesla D870 Tesla C870 Quadro 2000 Quadro 600 Quadro 6000 Quadro 5000 Quadro 5000M Quadro 4000 Quadro Plex 2200 D2 Quadro Plex 2100 D4 Quadro Plex 2100 Model S4 Quadro Plex 1000 Model IV Quadro FX 5800 Quadro FX 4800 Quadro FX 4700 X2 Quadro FX 3700M. GT 240M GeForce 9700M GT. 8800M GTX. GTS 260M. 9500M G. FX 3800M Quadro FX 5600 1.1 2 2 16 16 1.0 1.1 1. 9600M GT. 9500M GS. 9600 GSO. 9650M GS.0 1.0 1.0 1. G110M GeForce 9300M GS.0 1.1 2. 8400M GT.0 2.3 1. 8400 GS.2 1.

CUDA-Enabled GPUs Compute Capability Quadro FX 3700 Quadro FX 2800M Quadro FX 4600 Quadro FX 1800M Quadro FX 3600M Quadro FX 880M.2 1. FX 570. NVS 290. NVS 150M.1 1 8 CUDA C Programming Guide Version 3. NVS 2100M Quadro FX 370. NVS 3100M. NVS 160M.0 1. FX 360M Quadro FX 370M. NVS 130M 1. NVS 140M.1 1.Appendix A. NVS 320M.2 1.1 Number of Multiprocessors 14 12 12 9 8 6 6 4 Number of CUDA Cores 112 96 96 72 64 48 48 32 1. FX 1600M.2 101 .1 1. FX 1700M.1 2 2 16 16 1. FX 380M. NVS 135M.1 1.1 1. NVS 5100M Quadro FX 2700M Quadro FX 1700. FX 570M Quadro FX 380 LP. FX 770M.2 1.

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1. meaning it returns before the device has completed its execution.1 103 .  Callable from the host only. B.1. a __device__ function is always inlined by default. In device code compiled for devices of compute capability 1.x.  Any call to a __global__ function must specify its execution configuration as described in Section B. __global__ functions must have void return type. C Language Extensions B. A call to a __global__ function is asynchronous.1. The __noinline__ function qualifier however can be used as a hint for the compiler not to inline the function if possible (see Section E.1 __device__ The __device__ qualifier declares a function that is: Executed on the device  Callable from the device only.Appendix B. Such a function is: Executed on the device.2 __global__ The __global__ qualifier declares a function as being a kernel.1 Function Type Qualifiers Function type qualifiers specify whether a function executes on the host or on the device and whether it is callable from the host or from the device. B.3 __host__ The __host__ qualifier declares a function that is: CUDA C Programming Guide Version 3.  B.1).16.

in either case the function is compiled for the host only. It is not allowed to take the address of a __device__ function in host code. Static Variables __device__ and __global__ functions cannot declare static variables inside their body.1.x. It is equivalent to declare a function with only the __host__ qualifier or to declare it without any of the __host__.4 can be used to differentiate code paths between host and device: __host__ __device__ func() { #if __CUDA_ARCH__ == 100 // Device code path for compute capability 1.4.4. in which case the function is compiled for both the host and the device. but function pointers to __device__ functions are only supported in device code compiled for devices of compute capability 2.0 #elif __CUDA_ARCH__ == 200 // Device code path for compute capability 2. The __CUDA_ARCH__ macro introduced in Section 3.1.0 #elif !defined(__CUDA_ARCH__) // Host code path #endif } B.5 Recursion __global__ functions do not support recursion.  B.3 B.1.1 Restrictions Functions Parameters __global__ function parameters are passed to the device: via shared memory and are limited to 256 bytes on devices of compute capability 1. Function Pointers Function pointers to __global__ functions are supported. C Language Extensions Executed on the host. 104 CUDA C Programming Guide Version 3.4 Variadic Functions __device__ and __global__ functions cannot have a variable number of arguments. The __device__ and __host__ qualifiers can be used together however. or __global__ qualifier.1.1.  via constant memory and are limited to 4 KB on devices of compute capability 2.1. B.2 B.x.  Callable from the host only.Appendix B.4.4.1.  The __global__ and __host__ qualifiers cannot be used together.4 B.4.2 .x. __device__.

 Is only accessible from all the threads within the block. the variable: Resides in global memory space.2 B. All variables declared in this fashion. the size of the array is determined at launch time (see Section B.2 __constant__ The __constant__ qualifier.  Is accessible from all the threads within the grid and from the host through the runtime library (cudaGetSymbolAddress() / cudaGetSymbolSize() / cudaMemcpyToSymbol() / cudaMemcpyFromSymbol() for the runtime API and cuModuleGetGlobal() for the driver API).  B.x.16). When declaring a variable in shared memory as an external array such as  extern __shared__ float shared[]. At most one of the other type qualifiers defined in the next three sections may be used together with __device__ to further specify which memory space the variable belongs to. Has the lifetime of an application. so that the layout of CUDA C Programming Guide Version 3. optionally used together with __device__.3 __shared__ The __shared__ qualifier.  Is accessible from all the threads within the grid and from the host through the runtime library (cudaGetSymbolAddress() / cudaGetSymbolSize() / cudaMemcpyToSymbol() / cudaMemcpyFromSymbol() for the runtime API and cuModuleGetGlobal() for the driver API). __device__ The __device__ qualifier declares a variable that resides on the device.  Has the lifetime of the block. C Language Extensions __device__ functions only support recursion in device code compiled for devices of compute capability 2. declares a variable that: Resides in the shared memory space of a thread block.2. declares a variable that: Resides in constant memory space. B.2 105 .2.1 Variable Type Qualifiers Variable type qualifiers specify the memory location on the device of a variable. If none of them is present.  Has the lifetime of an application.Appendix B. start at the same address in memory. optionally used together with __device__.2.   B.

2. __device__ void func() // __device__ or __global__ function { short* array0 = (short*)array. one could declare and initialize the arrays the following way: extern __shared__ float array[]. which can have adverse performance consequences as detailed in Section 5.2. extern __shared__ float array[]. __shared__ variables cannot have an initialization as part of their declaration.2. int* array2 = (int*)&array1[64].4. on formal parameters and on local variables within a function that executes on the host. B.2. However in some cases the compiler might choose to place it in local memory.2 . B. so the following code. float array1[64]. float* array1 = (float*)&array0[128].2.3.3 Automatic Variable An automatic variable declared in device code without any of the __device__.1 Storage and Scope __shared__ and __constant__ variables have implied static storage.3. For example. if one wants the equivalent of short array0[128].2 Assignment __constant__ variables cannot be assigned to from the device. 106 CUDA C Programming Guide Version 3.4.1 and 3.4). in dynamically allocated shared memory. The only exception is for dynamically allocated __shared__ variables as described in Section B. B. only from the host through host runtime functions (Sections 3.4. B. __device__. int array2[256]. C Language Extensions the variables in the array must be explicitly managed through offsets. __shared__ and __constant__ qualifiers generally resides in a register. __device__ and __constant__ variables are only allowed at file scope. } Note that pointers need to be aligned to the type they point to. does not work since array1 is not aligned to 4 bytes. for example.4 Restrictions The __device__. __device__ void func() // __device__ or __global__ function { short* array0 = (short*)array.2. } Alignment requirements for the built-in vector types are listed in Table B-1.2.Appendix B.3. __shared__ and __constant__ variables cannot be defined as external using the extern keyword.2. __shared__ and __constant__ qualifiers are not allowed on struct and union members. float* array1 = (float*)&array0[127].

3. that ref2 will be equal to 2 in thread tid since thread tid might read myArray[tid] into ref2 before thread tid-1 overwrites its value by 2. in general.2. B. in the code sample below. Note that even if myArray is declared as volatile in the code sample above. This behavior can be changed using the volatile keyword: If a variable located in global or shared memory is declared as volatile. C Language Extensions B.x. As long as this requirement is met.5 volatile Only after the execution of a __threadfence_block().x.2. the compiler is free to optimize reads and writes to global or shared memory. pointers in code that is executed on the device are supported as long as the compiler is able to resolve whether they point to either the shared memory space or the global memory space. } Therefore. or __syncthreads() (Sections B. result[tid] = ref1 * ref2.Appendix B.4 can only be used in host code. there is no guarantee. __threadfence().6) are prior writes to global or shared memory guaranteed to be visible by other threads.x. but the second reference does not as the compiler simply reuses the result of the first read. __shared__ or __constant__ variable can only be used in device code. Synchronization is required as mentioned in Section 5. most often in a segmentation fault and application termination.4.3.5 and B. ref2 cannot possibly be equal to 2 in thread tid as a result of thread tid-1 overwriting myArray[tid] by 2. For devices of compute capability 2.2 107 . the first reference to myArray[tid] compiles into a global or shared memory read instruction. pointers are supported without any restriction. int ref2 = myArray[tid] * 1. The address obtained by taking the address of a __device__. // myArray is an array of non-zero integers // located in global or shared memory __global__ void MyKernel(int* result) { int tid = threadIdx. myArray[tid + 1] = 2. The address of a __device__ or __constant__ variable obtained through cudaGetSymbolAddress() as described in Section 3. CUDA C Programming Guide Version 3. For example. otherwise they are restricted to only point to memory allocated or declared in the global memory space. Dereferencing a pointer either to global or shared memory in code that is executed on the host or to host memory in code that is executed on the device results in an undefined behavior.4 Pointers For devices of compute capability 1.4. the compiler assumes that its value can be changed at any time by another thread and therefore any reference to this variable compiles to an actual memory read instruction. int ref1 = myArray[tid] * 1.

Appendix B.

C Language Extensions

B.3
B.3.1

Built-in Vector Types
char1, uchar1, char2, uchar2, char3, uchar3, char4, uchar4, short1, ushort1, short2, ushort2, short3, ushort3, short4, ushort4, int1, uint1, int2, uint2, int3, uint3, int4, uint4, long1, ulong1, long2, ulong2, long3, ulong3, long4, ulong4, longlong1, ulonglong1, longlong2, ulonglong2, float1, float2, float3, float4, double1, double2
These are vector types derived from the basic integer and floating-point types. They are structures and the 1st, 2nd, 3rd, and 4th components are accessible through the fields x, y, z, and w, respectively. They all come with a constructor function of the form make_<type name>; for example,
int2 make_int2(int x, int y);

which creates a vector of type int2 with value (x, y). In host code, the alignment requirement of a vector type is equal to the alignment requirement of its base type. This is not always the case in device code as detailed in Table B-1.

Table B-1. Alignment Requirements in Device Code
Type
char1, uchar1 char2, uchar2 char3, uchar3 char4, uchar4 short1, ushort1 short2, ushort2 short3, ushort3 short4, ushort4 int1, uint1 int2, uint2 int3, uint3 int4, uint4 long1, ulong1 long2, ulong2 long3, ulong3 long4, ulong4

Alignment
1 2 1 4 2 4 2 8 4 8 4 16 4 if sizeof(long) is equal to sizeof(int), 8, otherwise 8 if sizeof(long) is equal to sizeof(int), 16, otherwise 4 if sizeof(long) is equal to sizeof(int), 8, otherwise 16

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Appendix B.

C Language Extensions

longlong1, ulonglong1 longlong2, ulonglong2 float1 float2 float3 float4 double1 double2

8 16 4 8 4 16 8 16

B.3.2

dim3
This type is an integer vector type based on uint3 that is used to specify dimensions. When defining a variable of type dim3, any component left unspecified is initialized to 1.

B.4

Built-in Variables
Built-in variables specify the grid and block dimensions and the block and thread indices. They are only valid within functions that are executed on the device.

B.4.1

gridDim
This variable is of type dim3 (see Section B.3.2) and contains the dimensions of the grid.

B.4.2

blockIdx
This variable is of type uint3 (see Section B.3.1) and contains the block index within the grid.

B.4.3

blockDim
This variable is of type dim3 (see Section B.3.2) and contains the dimensions of the block.

B.4.4

threadIdx
This variable is of type uint3 (see Section B.3.1) and contains the thread index within the block.

CUDA C Programming Guide Version 3.2

109

Appendix B.

C Language Extensions

B.4.5

warpSize
This variable is of type int and contains the warp size in threads (see Section 4.1 for the definition of a warp).

B.4.6

Restrictions
It is not allowed to take the address of any of the built-in variables.  It is not allowed to assign values to any of the built-in variables.

B.5

Memory Fence Functions
void __threadfence_block();

waits until all global and shared memory accesses made by the calling thread prior to __threadfence_block() are visible to all threads in the thread block.
void __threadfence();

waits until all global and shared memory accesses made by the calling thread prior to __threadfence() are visible to: All threads in the thread block for shared memory accesses,  All threads in the device for global memory accesses.
 void __threadfence_system();

waits until all global and shared memory accesses made by the calling thread prior to __threadfence_system() are visible to: All threads in the thread block for shared memory accesses,  All threads in the device for global memory accesses,  Host threads for page-locked host memory accesses (see Section 3.2.5.3). __threadfence_system() is only supported by devices of compute capability 2.x.

In general, when a thread issues a series of writes to memory in a particular order, other threads may see the effects of these memory writes in a different order. __threadfence_block(), __threadfence(), and __threadfence_system() can be used to enforce some ordering. One use case is when threads consume some data produced by other threads as illustrated by the following code sample of a kernel that computes the sum of an array of N numbers in one call. Each block first sums a subset of the array and stores the result in global memory. When all blocks are done, the last block done reads each of these partial sums from global memory and sums them to obtain the final result. In order to determine which block is finished last, each block atomically increments a counter to signal that it is done with computing and storing its partial sum (see Section B.11 about atomic functions). The last block is the one that receives the counter value equal to gridDim.x-1. If no fence is placed between storing the partial sum and incrementing the counter, the counter might increment before the partial sum is stored and therefore, might reach gridDim.x-1 and let

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gridDim. unsigned int N. // Thread 0 makes sure its result is visible to // all other threads __threadfence(). __shared__ bool isLastBlockDone. if (threadIdx. CUDA C Programming Guide Version 3.x] = partialSum. } // Synchronize to make sure that each thread reads // the correct value of isLastBlockDone __syncthreads(). // Thread 0 of each block signals that it is done unsigned int value = atomicInc(&count.x-1] float totalSum = calculateTotalSum(result).Appendix B. gridDim. // Thread 0 of each block determines if its block is // the last block to be done isLastBlockDone = (value == (gridDim. __device__ unsigned int count = 0..x == 0) { // Thread 0 of last block stores total sum // to global memory and resets count so that // next kernel call works properly result[0] = totalSum. __global__ void sum(const float* array. if (isLastBlockDone) { // The last block sums the partial sums // stored in result[0 . N). if (threadIdx.x).x == 0) { // Thread 0 of each block stores the partial sum // to global memory result[blockIdx.x . } } } B. float* result) { // Each block sums a subset of the input array float partialSum = calculatePartialSum(array. count = 0. C Language Extensions the last block start reading partial sums before they have been actually updated in memory.6 Synchronization Functions void __syncthreads().2 111 .1)).

When executed in host code. a less accurate. The compiler has an option (-use_fast_math) that forces each function in Table B-2 to compile to its intrinsic counterpart. is identical to __syncthreads() with the additional feature that it evaluates predicate for all threads of the block and returns non-zero if and only if predicate evaluates to non-zero for all of them. it may also cause some differences in special case handling. but faster version exists in the device runtime component. C Language Extensions waits until all threads in the thread block have reached this point and all global and shared memory accesses made by these threads prior to __syncthreads() are visible to all threads in the block. A more robust approach is to selectively replace mathematical function calls by calls to intrinsic functions only where it is merited by the performance gains and where changed properties such as reduced accuracy and different special case handling can be tolerated. along with their respective error bounds. int __syncthreads_or(int predicate).7 Mathematical Functions Section C.1 contains a comprehensive list of the C/C++ standard library mathematical functions that are currently supported in device code. or write-after-write hazards for some of these memory accesses. Functions Affected by –use_fast_math 112 CUDA C Programming Guide Version 3. is identical to __syncthreads() with the additional feature that it evaluates predicate for all threads of the block and returns the number of threads for which predicate evaluates to non-zero.2 . For some of the functions of Section C. int __syncthreads_and(int predicate). otherwise the code execution is likely to hang or produce unintended side effects. These intrinsic functions are listed in Section C. __syncthreads() is allowed in conditional code but only if the conditional evaluates identically across the entire thread block. a given function uses the C runtime implementation if available.2. is identical to __syncthreads() with the additional feature that it evaluates predicate for all threads of the block and returns non-zero if and only if predicate evaluates to non-zero for any of them. B. Devices of compute capability 2. When some threads within a block access the same addresses in shared or global memory. along with their respective error bounds. write-after-read. there are potential read-after-write. it has the same name prefixed with __ (such as __sinf(x)).Appendix B. int __syncthreads_count(int predicate). Table B-2. These data hazards can be avoided by synchronizing threads in-between these accesses. __syncthreads() is used to coordinate communication between the threads of the same block. In addition to reduce accuracy of the affected functions.x support three variations of __syncthreads() described below.1.

For integer types.y) __sinf(x) __cosf(x) __tanf(x) __sincosf(x.2 113 .1. compile-time) and mutable (i. int x). runtime) attributes determine how the texture coordinates are interpreted.4. 1.y) B. 1. fetch the region of linear memory bound to texture reference texRef using integer texture coordinate x. C Language Extensions Operator/Function x/y sinf(x) cosf(x) tanf(x) sincosf(x.2.2. float tex1Dfetch( texture<unsigned short. float tex1Dfetch( texture<signed short. int x). 1. 1.cptr) logf(x) log2f(x) log10f(x) expf(x) exp10f(x) powf(x. and the return value delivered by the texture fetch. cudaReadModeNormalizedFloat> texRef.4.2. 1. cudaReadModeNormalizedFloat> texRef.1 tex1Dfetch() template<class Type> Type tex1Dfetch( texture<Type.e. what processing occurs during the texture fetch.1.Appendix B. CUDA C Programming Guide Version 3.8. these functions may optionally promote the integer to single-precision floating point. float tex1Dfetch( texture<unsigned char.cptr) __logf(x) __log2f(x) __log10f(x) __expf(x) __exp10f(x) __powf(x.sptr. a combination of the texture reference‟s immutable (i.8 Texture Functions For texture functions. int x). int x).1. float tex1Dfetch( texture<signed char. cudaReadModeElementType> texRef. int x). cudaReadModeNormalizedFloat> texRef. B. Immutable attributes are described in Section 3.sptr. cudaReadModeNormalizedFloat> texRef.y) Device Function __fdividef(x. Texture fetching is described in Appendix F.e. No texture filtering and addressing modes are supported. Mutable attributes are described in Section 3.

114 CUDA C Programming Guide Version 3. in which case out-of-range reads return zero and out-of-range writes are ignored.2.2. Surface reference declaration is described in Section 3. float y.3 tex2D() template<class Type.2 . in which case out-of-range accesses cause the kernel execution to fail. and 4-tuples are supported.9 Surface Functions Surface functions are only supported by devices of compute capability 2. 2-. B.8.2. readMode> texRef. float x.1 and surface binding in Section 3. float y).4. C Language Extensions Besides the functions shown above. 1. boundaryMode specifies the boundary mode. In the sections below.0 and higher.4. B. 2. y. enum cudaTextureReadMode readMode> Type tex3D(texture<Type. B.2 tex1D() template<class Type. float z).2. enum cudaTextureReadMode readMode> Type tex1D(texture<Type. int x). it is equal to either cudaBoundaryModeClamp. or cudaBoundaryModeZero.8. or cudaBoundaryModeTrap. in which case out-of-range coordinates are clamped to the valid range. 1. and z. float x). for example: float4 tex1Dfetch( texture<uchar4. that is how out-of-range surface coordinates are handled. float x. fetches the region of linear memory bound to texture reference texRef using texture coordinate x. fetches the CUDA array bound to texture reference texRef using texture coordinates x. fetches the CUDA array or the region of linear memory bound to texture reference texRef using texture coordinates x and y.Appendix B. readMode> texRef. readMode> texRef. fetches the CUDA array bound to texture reference texRef using texture coordinate x.8. enum cudaTextureReadMode readMode> Type tex2D(texture<Type.4 tex3D() template<class Type. cudaReadModeNormalizedFloat> texRef.2. B. 3.

reads the CUDA array bound to surface reference surfRef using coordinates x and y.Appendix B.2 115 . int y.9. B.9. writes value data to the CUDA array bound to surface reference surfRef at coordinate x. and recording the result per thread provides a measure for each thread of the number of clock cycles taken by the device to completely execute the thread. Sampling this counter at the beginning and at the end of a kernel. int y. B.2 surf1Dwrite() template<class Type> void surf1Dwrite(Type data. int x. but not of the number of clock cycles the device actually spent executing thread instructions. taking the difference of the two samples. when executed in device code. 1> surfRef. boundaryMode = cudaBoundaryModeTrap).1 surf1Dread() template<class Type> Type surf1Dread(surface<void. 1> surfRef. The former number is greater that the latter since threads are time sliced. surface<void.10 Time Function clock_t clock(). int x.4 surf2Dwrite() template<class Type> void surf2Dwrite(Type data. writes value data to the CUDA array bound to surface reference surfRef at coordinate x and y. surface<void. returns the value of a per-multiprocessor counter that is incremented every clock cycle. int x. 2> surfRef. C Language Extensions B. CUDA C Programming Guide Version 3. B. boundaryMode = cudaBoundaryModeTrap). boundaryMode = cudaBoundaryModeTrap).9. B. 2> surfRef. int x.9. boundaryMode = cudaBoundaryModeTrap).3 surf2Dread() template<class Type> Type surf2Dread(surface<void. reads the CUDA array bound to surface reference surfRef using coordinate x.

and stores the result back to memory at 116 CUDA C Programming Guide Version 3.2.11. unsigned long long int val). float val). Atomic functions operating on shared memory and atomic functions operating on 64-bit words are only available for devices of compute capability 1. atomicAdd() for double-precision floating-point numbers can be implemented as follows: __device__ double atomicAdd(double* address. unsigned int atomicAdd(unsigned int* address. In other words. } while (assumed != old). __double_as_longlong(val + assumed))).1 and above. that also work for single-precision floating-point numbers. Atomic functions can only be used in device functions and are only available for devices of compute capability 1. do { assumed = old. Atomic operations only work with signed and unsigned integers with the exception of atomicAdd() for devices of compute capability 2. and writes the result back to the same address. For example. For example. reads the 32-bit or 64-bit word old located at the address address in global or shared memory.x and higher.2 and above. Note however that any atomic operation can be implemented based on atomicCAS() (Compare And Swap).1. int val). } B.Appendix B. atomicAdd() reads a 32-bit word at some address in global or shared memory. computes (old + val).1 Arithmetic Functions atomicAdd() int atomicAdd(int* address.x and atomicExch() for all devices. float atomicAdd(float* address. old = __longlong_as_double( atomicCAS((unsigned long long int*)address. unsigned long long int atomicAdd(unsigned long long int* address. no other thread can access this address until the operation is complete. adds a number to it. return old. Atomic functions operating on 64-bit words in shared memory are only available for devices of compute capability 2. __double_as_longlong(assumed).11.3) are not atomic from the point of view of the host or other devices. Atomic functions operating on mapped page-locked memory (Section 3. double val) { double old = *address.11 Atomic Functions An atomic function performs a read-modify-write atomic operation on one 32-bit or 64-bit word residing in global or shared memory. unsigned int val).5. C Language Extensions B.1 B. assumed.2 . The operation is atomic in the sense that it is guaranteed to be performed without interference from other threads.

int val). These three operations are performed in one atomic transaction. unsigned int val). reads the 32-bit or 64-bit word old located at the address address in global or shared memory and stores val back to memory at the same address. unsigned int atomicExch(unsigned int* address. float val). The floating-point version of atomicAdd() is only supported by devices of compute capability 2. These three operations are performed in one atomic transaction.1. unsigned int atomicMin(unsigned int* address. B.11. unsigned int val). int val).Appendix B. These three operations are performed in one atomic transaction. and stores the result back to memory at the same address. The function returns old. The function returns old. unsigned long long int val). and stores the result back to memory at the same address. unsigned int val). These two operations are performed in one atomic transaction. float atomicExch(float* address. computes the maximum of old and val. reads the 32-bit word old located at the address address in global or shared memory. These three operations are performed in one atomic transaction.11. reads the 32-bit word old located at the address address in global or shared memory. The function returns old. computes (old . The function returns old. computes ((old >= val) ? 0 : (old+1)). The function returns old.x. int val). These three operations are performed in one atomic transaction. B.1. B.2 117 . computes the minimum of old and val. unsigned int atomicSub(unsigned int* address. unsigned long long int atomicExch(unsigned long long int* address. and stores the result back to memory at the same address. unsigned int val). The function returns old. C Language Extensions the same address. unsigned int val). reads the 32-bit word old located at the address address in global or shared memory.1.5 atomicMax() int atomicMax(int* address. int val).6 atomicInc() unsigned int atomicInc(unsigned int* address.1.3 atomicExch() int atomicExch(int* address.11.4 atomicMin() int atomicMin(int* address. B.1. and stores the result back to memory at the same address. B.val). unsigned int atomicMax(unsigned int* address.11.2 atomicSub() int atomicSub(int* address.11. CUDA C Programming Guide Version 3. reads the 32-bit word old located at the address address in global or shared memory.

int compare. and stores the result back to memory at the same address. computes (old & val). and stores the result back to memory at the same address. unsigned int val). unsigned int val). B.11.3 atomicXor() int atomicXor(int* address.Appendix B. and stores the result back to memory at the same address.1 Bitwise Functions atomicAnd() int atomicAnd(int* address. unsigned long long int atomicCAS(unsigned long long int* address.2 B. unsigned long long int compare. C Language Extensions B. These three operations are performed in one atomic transaction. int val). unsigned long long int val). unsigned int atomicXor(unsigned int* address.2.11. unsigned int atomicAnd(unsigned int* address.11.2. unsigned int atomicCAS(unsigned int* address.2 .8 atomicCAS() int atomicCAS(int* address. These three operations are performed in one atomic transaction. unsigned int atomicOr(unsigned int* address. computes (old == compare ? val : old). The function returns old. B. int val).2 atomicOr() int atomicOr(int* address. int val). computes (((old == 0) | (old > val)) ? val : (old-1)).11. reads the 32-bit word old located at the address address in global or shared memory. reads the 32-bit word old located at the address address in global or shared memory. 118 CUDA C Programming Guide Version 3.7 atomicDec() unsigned int atomicDec(unsigned int* address. unsigned int compare. These three operations are performed in one atomic transaction.11.1.11. These three operations are performed in one atomic transaction. unsigned int val). unsigned int val). computes (old | val). unsigned int val). reads the 32-bit or 64-bit word old located at the address address in global or shared memory.1.2. The function returns old. reads the 32-bit word old located at the address address in global or shared memory. B. B. The function returns old (Compare And Swap). int val). and stores the result back to memory at the same address. The function returns old.

…. increments by one per warp the per-multiprocessor hardware counter of index counter.14 Formatted Output Formatted output is only supported by devices of compute capability 2. Parallel Nsight). B. computes (old ^ val).1 for the definition of a warp).2 119 ..Appendix B. the string passed in as format is output to a stream on the host.. In essence. in the profiler. all launches are synchronous).2 and higher (see Section 4. C Language Extensions reads the 32-bit word old located at the address address in global or shared memory. B. prints formatted output from a kernel to a host-side output stream.13 Profiler Counter Function Each multiprocessor has a set of sixteen hardware counters that an application can increment with a single instruction by calling the __prof_trigger() function. 7 for the first multiprocessor can be obtained via the CUDA profiler by listing prof_trigger_00. arg. unsigned int __ballot(int predicate). The function returns old. All counters are reset before each kernel call (note that when an application is run via a CUDA debugger or profiler (cuda-gdb.x. …. B. int printf(const char *format[. CUDA Visual Profiler. .conf file (see the profiler manual for more details). int __any(int predicate). These three operations are performed in one atomic transaction. 1. int __all(int predicate). The in-kernel printf() function behaves in a similar way to the standard C-library printf() function. etc. prof_trigger_07.12 Warp Vote Functions Warp vote functions are only supported by devices of compute capability 1. prof_trigger_01. evaluates predicate for all threads of the warp and returns an integer whose Nth bit is set if and only if predicate evaluates to non-zero for the Nth thread of the warp.x. and the user is referred to the host system‟s manual pages for a complete description of printf() behavior. void __prof_trigger(int counter). Counters 8 to 15 are reserved and should not be used by applications. and stores the result back to memory at the same address. The value of counters 0. evaluates predicate for all threads of the warp and returns non-zero if and only if predicate evaluates to non-zero for any of them.]). This function is only supported by devices of compute capability 2. with substitutions made from the CUDA C Programming Guide Version 3. evaluates predicate for all threads of the warp and returns non-zero if and only if predicate evaluates to non-zero for all of them.

width. using that thread‟s data as specified.14. If the format string is NULL. -2 is returned. this means that a straightforward call to printf() will be executed by every thread. but exact behavior will be host-O/S-dependent.4 for an illustrative example). This is because it cannot determine what will and will not be valid on the host system where the final output is formatted. precision.14. C Language Extensions argument list wherever a format specifier is encountered. From a multi-threaded kernel.14. In other words.Appendix B. format specifiers take the form: %[flags][width][. Supported format specifiers are listed below. If an internal error occurs. size and type. This means that the format string must be understood by the host-system‟s compiler and C library. As described in Section B.precision][size]type The following fields are supported (see widely-available documentation for a complete description of all behaviors): Flags: „#‟ „ „ „0‟ „+‟ „-„  Width: „*‟ „0-9‟  Precision: „0-9‟  Size: „h‟ „l‟ „ll‟  Type: „%cdiouxXpeEfgGaAs‟ Note that CUDA‟s printf() will accept any combination of flag. and is flushed at any host-side synchronisation point 120 CUDA C Programming Guide Version 3.2 Limitations Final formatting of the printf() output takes place on the host system.  B. The printf() command is executed as any other device-side function: per-thread.2 . B. once for each thread which encountered the printf(). whether or not overall they form a valid format specifier. Every effort has been made to ensure that the format specifiers supported by CUDA‟s printf function form a universal subset from the most common host compilers. which returns the number of characters printed. Multiple versions of the output string will then appear at the host stream. This buffer is circular. The effect of this is that output may be undefined if the program emits a format string which contains invalid combinations. If no arguments follow the format string. 0 is returned. printf() will accept all combinations of valid flags and types.1 Format Specifiers As for standard printf(). -1 is returned. It is up to the programmer to limit the output to a single thread if only a single output string is desired (see Section B. and in the context of the calling thread. “%hd” will be accepted and printf will expect a double-precision variable in the corresponding location in the argument list.1. CUDA‟s printf() returns the number of arguments parsed.14. The output buffer for printf() is set to a fixed size before kernel launch (see below). Unlike the C-standard printf().

Appendix B.

C Language Extensions

and at when the context is explicitly destroyed; if more output is produced during kernel execution than can fit in the buffer, older output is overwritten. The printf() command can accept at most 32 arguments in addition to the format string. Additional arguments beyond this will be ignored, and the format specifier output as-is. Owing to the differing size of the long type on 64-bit Windows platforms (four bytes on 64-bit Windows platforms, eight bytes on other 64-bit platforms), a kernel which is compiled on a non-Windows 64-bit machine but then run on a win64 machine will see corrupted output for all format strings which include “%ld”. It is recommended that the compilation platform matches the execution platform to ensure safety. The output buffer for printf() is not flushed automatically to the output stream, but instead is flushed only when one of these actions is performed: Kernel launch via <<<>>> or cuLaunch(),  Synchronization via cudaThreadSynchronize(), cuCtxSynchronize(), cudaStreamSynchronize(), or cuStreamSynchronize(),  Module loading/unloading via cuModuleLoad() or cuModuleUnload(),  Context destruction via cudaThreadExit() or cuCtxDestroy(). Note that the buffer is not flushed automatically when the program exits. The user must call cudaThreadExit() or cuCtxDestroy() explicitly, as shown in the examples below.

B.14.3

Associated Host-Side API
The following API functions get and set the size of the buffer used to transfer the printf() arguments and internal metadata to the host (default is 1 megabyte):

Driver API:
cuCtxGetLimit(size_t* size, CU_LIMIT_PRINTF_FIFO_SIZE) cuCtxSetLimit(CU_LIMIT_PRINTF_FIFO_SIZE, size_t size)

Runtime API:
cudaThreadGetLimit(size_t* size,cudaLimitPrintfFifoSize) cudaThreadSetLimit(cudaLimitPrintfFifoSize, size_t size)

B.14.4

Examples
The following code sample:
__global__ void helloCUDA(float f) { printf(“Hello thread %d, f=%f\n”, threadIdx.x, f) ; } void main() { helloCUDA<<<1, 5>>>(1.2345f);

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C Language Extensions
cudaThreadExit(); }

will output:
Hello Hello Hello Hello Hello thread thread thread thread thread 0, 1, 2, 3, 4, f=1.2345 f=1.2345 f=1.2345 f=1.2345 f=1.2345

Notice how each thread encounters the printf() command, so there are as many lines of output as there were threads launched in the grid. As expected, global values (i.e. float f) are common between all threads, and local values (i.e. threadIdx.x) are distinct per-thread. The following code sample:
__global__ void helloCUDA(float f) { if (threadIdx.x == 0) printf(“Hello thread %d, f=%f\n”, threadIdx.x, f) ; } void main() { helloCUDA<<<1, 5>>>(1.2345f); cudaThreadExit(); }

will output:
Hello thread 0, f=1.2345

Self-evidently, the if() statement limits which threads will call printf, so that only a single line of output is seen.

B.15

Dynamic Global Memory Allocation
void* malloc(size_t size); void free(void* ptr);

allocate and free memory dynamically from a fixed-size heap in global memory. The CUDA in-kernel malloc() function allocates at least size bytes from the device heap and returns a pointer to the allocated memory or NULL if insufficient memory exists to fulfill the request. The returned pointer is guaranteed to be aligned to a 16-byte boundary. The CUDA in-kernel free() function deallocates the memory pointed to by ptr, which must have been returned by a previous call to malloc(). If ptr is NULL, the call to free() is ignored. Repeated calls to free() with the same ptr has undefined behavior. The memory allocated by a given CUDA thread via malloc() remains allocated for the lifetime of the CUDA context, or until it is explicitly released by a call to free(). It can be used by any other CUDA threads even from subsequent kernel launches. Any CUDA thread may free memory allocated by another thread, but care should be taken to ensure that the same pointer is not freed more than once.

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Appendix B.

C Language Extensions

B.15.1

Heap Memory Allocation
The device memory heap has a fixed size that must be specified before any program using malloc() or free() is loaded into the context. A default heap of eight megabytes is allocated if any program uses malloc() without explicitly specifying the heap size. The following API functions get and set the heap size:

Driver API:
cuCtxGetLimit(size_t* size, CU_LIMIT_MALLOC_HEAP_SIZE) cuCtxSetLimit(CU_LIMIT_MALLOC_HEAP_SIZE, size_t size)

Runtime API:
cudaThreadGetLimit(size_t* size, cudaLimitMallocHeapSize) cudaThreadSetLimit(cudaLimitMallocHeapSize, size_t size)

The heap size granted will be at least size bytes. cuCtxGetLimit() and cudaThreadGetLimit() return the currently requested heap size. The actual memory allocation for the heap occurs when a module is loaded into the context, either explicitly via the CUDA driver API (see Section 3.3.2), or implicitly via the CUDA runtime API (see Section 3.2). If the memory allocation fails, the module load will generate a CUDA_ERROR_SHARED_OBJECT_INIT_FAILED error. Heap size cannot be changed once a module load has occurred and it does not resize dynamically according to need. Memory reserved for the device heap is in addition to memory allocated through host-side CUDA API calls such as cudaMalloc().

B.15.2

Interoperability with Host Memory API
Memory allocated via malloc() cannot be freed using the runtime or driver API (i.e. by calling any of the free memory functions from Sections 3.2.1 and 3.3.4). Similarly, memory allocated via the runtime or driver API (i.e. by calling any of the memory allocation functions from Sections 3.2.1 and 3.3.4) cannot be freed via free(). Memory allocated via malloc() can be copied using the runtime or driver API (i.e. by calling any of the copy memory functions from Sections 3.2.1 and 3.3.4).

B.15.3
B.15.3.1

Examples
Per Thread Allocation
The following code sample:
__global__ void mallocTest() { char* ptr = (char*)malloc(123); printf(“Thread %d got pointer: %p\n”, threadIdx.x, ptr); free(ptr);

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5>>>(). (Exact pointer values will vary: these are illustrative. 64 bytes per thread are allocated. i < 64.2 Per Thread Block Allocation __global__ void mallocTest() { __shared__ int* data.x] = threadIdx. Note that this must // be done before any kernel is launched. } void main() { cudaThreadSetLimit(cudaLimitMallocHeapSize.x == 0) data = (int*)malloc(blockDim. for (int i = 0. 124 CUDA C Programming Guide Version 3. // // // // if The first thread in the block does the allocation and then shares the pointer with all other threads through shared memory.x. ensuring coalescence int* ptr = data. cudaThreadSynchronize(). 128*1024*1024).3.) B.15.2 . 128*1024*1024). // Check for failure if (data == NULL) return. // Only one thread may free the memory! if (threadIdx. 128>>>(). // Threads index into the memory. C Language Extensions } void main() { // Set a heap size of 128 megabytes. mallocTest<<<10. cudaThreadSynchronize(). } will output: Thread Thread Thread Thread Thread 0 1 2 3 4 got got got got got pointer: pointer: pointer: pointer: pointer: 00057020 0005708c 000570f8 00057164 000571d0 Notice how each thread encounters the malloc() command and so receives its own allocation. ++i) ptr[i * blockDim. mallocTest<<<1.Appendix B. // Ensure all threads complete before freeing __syncthreads(). cudaThreadSetLimit(cudaLimitMallocHeapSize. so that access can easily be coalesced.x * 64). (threadIdx.x + threadIdx.x == 0) free(data). __syncthreads().

Appendix B.

C Language Extensions

}

B.15.3.3

Allocation Persisting Between Kernel Launches
#define NUM_BLOCKS 20 __device__ int* dataptr[NUM_BLOCKS]; // Per-block pointer __global__ void allocmem() { // Only the first thread in the block does the allocation // since we want only one allocation per block. if (threadIdx.x == 0) dataptr[blockIdx.x] = (int*)malloc(blockDim.x * 4); __syncthreads(); // Check for failure if (dataptr[blockIdx.x] == NULL) return; // Zero the data with all threads in parallel dataptr[blockIdx.x][threadIdx.x] = 0; } // Simple example: store thread ID into each element __global__ void usemem() { int* ptr = dataptr[blockIdx.x]; if (ptr != NULL) ptr[threadIdx.x] += threadIdx.x; } // Print the content of the buffer before freeing it __global__ void freemem() { int* ptr = dataptr[blockIdx.x]; if (ptr != NULL) printf(“Block %d, Thread %d: final value = %d\n”, blockIdx.x, threadIdx.x, ptr[threadIdx.x]); // Only free from one thread! if (threadIdx.x == 0) free(ptr); } void main() { cudaThreadSetLimit(cudaLimitMallocHeapSize, 128*1024*1024); // Allocate memory allocmem<<< NUM_BLOCKS, 10 >>>(); // Use memory usemem<<< NUM_BLOCKS, 10 >>>(); usemem<<< NUM_BLOCKS, 10 >>>(); usemem<<< NUM_BLOCKS, 10 >>>(); // Free memory

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Appendix B.

C Language Extensions
freemem<<< NUM_BLOCKS, 10 >>>(); cudaThreadSynchronize(); }

B.16

Execution Configuration
Any call to a __global__ function must specify the execution configuration for that call. The execution configuration defines the dimension of the grid and blocks that will be used to execute the function on the device, as well as the associated stream (see Section 3.3.9.1 for a description of streams). When using the driver API, the execution configuration is specified through a series of driver function calls as detailed in Section 3.3.3. When using the runtime API (Section 3.2), the execution configuration is specified by inserting an expression of the form <<< Dg, Db, Ns, S >>> between the function name and the parenthesized argument list, where:

Dg is of type dim3 (see Section B.3.2) and specifies the dimension and size of the grid, such that Dg.x * Dg.y equals the number of blocks being launched; Dg.z must be equal to 1; Db is of type dim3 (see Section B.3.2) and specifies the dimension and size of each block, such that Db.x * Db.y * Db.z equals the number of threads

per block; Ns is of type size_t and specifies the number of bytes in shared memory that is dynamically allocated per block for this call in addition to the statically allocated memory; this dynamically allocated memory is used by any of the variables declared as an external array as mentioned in Section B.2.3; Ns is an optional argument which defaults to 0;  S is of type cudaStream_t and specifies the associated stream; S is an optional argument which defaults to 0. As an example, a function declared as
 __global__ void Func(float* parameter);

must be called like this:
Func<<< Dg, Db, Ns >>>(parameter);

The arguments to the execution configuration are evaluated before the actual function arguments and like the function arguments, are currently passed via shared memory to the device. The function call will fail if Dg or Db are greater than the maximum sizes allowed for the device as specified in Appendix G, or if Ns is greater than the maximum amount of shared memory available on the device, minus the amount of shared memory required for static allocation, functions arguments (for devices of compute capability 1.x), and execution configuration.

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Appendix B.

C Language Extensions

B.17

Launch Bounds
As discussed in detail in Section 5.2.3, the fewer registers a kernel uses, the more threads and thread blocks are likely to reside on a multiprocessor, which can improve performance. Therefore, the compiler uses heuristics to minimize register usage while keeping register spilling (see Section 5.3.2.2) and instruction count to a minimum. An application can optionally aid these heuristics by providing additional information to the compiler in the form of launch bounds that are specified using the __launch_bounds__() qualifier in the definition of a __global__ function:
__global__ void __launch_bounds__(maxThreadsPerBlock, minBlocksPerMultiprocessor) MyKernel(...) { ... } 

maxThreadsPerBlock specifies the maximum number of threads per block with which the application will ever launch MyKernel(); it compiles to the .maxntid PTX directive; minBlocksPerMultiprocessor is optional and specifies the desired

minimum number of resident blocks per multiprocessor; it compiles to the .minnctapersm PTX directive. If launch bounds are specified, the compiler first derives from them the upper limit L on the number of registers the kernel should use to ensure that minBlocksPerMultiprocessor blocks (or a single block if minBlocksPerMultiprocessor is not specified) of maxThreadsPerBlock threads can reside on the multiprocessor (see Section 4.2 for the relationship between the number of registers used by a kernel and the number of registers allocated per block). The compiler then optimizes register usage in the following way: If the initial register usage is higher than L, the compiler reduces it further until it becomes less or equal to L, usually at the expense of more local memory usage and/or higher number of instructions;  If the initial register usage is lower than L,  If maxThreadsPerBlock is specified and minBlocksPerMultiprocessor is not, the compiler uses maxThreadsPerBlock to determine the register usage thresholds for the transitions between n and n+1 resident blocks (i.e. when using one less register makes room for an additional resident block as in the example of Section 5.2.3) and then applies similar heuristics as when no launch bounds are specified;  If both minBlocksPerMultiprocessor and maxThreadsPerBlock are specified, the compiler may increase register usage as high as L to reduce the number of instructions and better hide single thread instruction latency. A kernel will fail to launch if it is executed with more threads per block than its launch bound maxThreadsPerBlock.

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..2. The sample code below shows how this is typically handled in device code using the __CUDA_ARCH__ macro introduced in Section 3. C Language Extensions Optimal launch bounds for a given kernel will usually differ across major architecture revisions.2 . so MyKernel will launch with 256 threads per block even when __CUDA_ARCH__ is greater or equal to 200. threadsPerBlock>>>(..1. The value of -maxrregcount is ignored for functions with launch bounds.. it is tempting to use MY_KERNEL_MAX_THREADS as the number of threads per block in the execution configuration: // Host code MyKernel<<<blocksPerGrid.1.). } In the common case where MyKernel is invoked with the maximum number of threads per block (specified as the first parameter of __launch_bounds__())..4.). #define THREADS_PER_BLOCK #if __CUDA_ARCH__ >= 200 #define MY_KERNEL_MAX_THREADS #define MY_KERNEL_MIN_BLOCKS #else #define MY_KERNEL_MAX_THREADS #define MY_KERNEL_MIN_BLOCKS #endif 256 (2 * THREADS_PER_BLOCK) 3 THREADS_PER_BLOCK 2 // Device code __global__ void __launch_bounds__(MY_KERNEL_MAX_THREADS. 128 CUDA C Programming Guide Version 3.Appendix B. Register usage is reported by the --ptxas-options=-v compiler option.3 for a definition of occupancy). MyKernel<<<blocksPerGrid.) { . device). This will not work however since __CUDA_ARCH__ is undefined in host code as mentioned in Section 3....). int threadsPerBlock = (deviceProp. Instead the number of threads per block should be determined:  Either at compile time using a macro that does not depend on __CUDA_ARCH__. MY_KERNEL_MIN_BLOCKS) MyKernel(. MY_KERNEL_MAX_THREADS>>>(.. THREADS_PER_BLOCK>>>(. The number of resident blocks can be derived from the occupancy reported by the CUDA profiler (see Section 5..4.major >= 2 ? 2 * THREADS_PER_BLOCK : THREADS_PER_BLOCK).  Or at runtime based on the compute capability // Host code cudaGetDeviceProperties(&deviceProp. for example // Host code MyKernel<<<blocksPerGrid. Register usage can also be controlled for all __global__ functions in a file using the -maxrregcount compiler option.

so have a maximum error of 0. that passing a float argument always results in a float result (variants (2) and (3) above). Mathematical Functions Functions from Section C. and floorf() each map to a single instruction as well.1 Standard Functions This section lists all the mathematical standard library functions supported in device code. e. on the device.Appendix C. so they are not guaranteed bounds. float log(float) (3) float <func-name>f(float). so that in general.x.g. double log(double) (2) float <func-name>(float). in particular. the compiler often combines them into a single multiply-add instruction (FMAD) and for devices of compute capability 1.1 Single-Precision Floating-Point Functions Addition and multiplication are IEEE-compliant. They are generated from extensive but not exhaustive tests.g.2). These error bounds also apply when the function is executed on the host in the case where the host does not supply the function. e.1 can be used in both host and device code whereas functions from Section C. there are three prototypes for a given function <func-name>: (1) double <func-name>(double). The reason is that roundf() maps to an 8-instruction sequence on the device.1 129 . ceilf(). However. truncf(). CUDA C Programming Guide Version 3.2 can only be used in device code. not roundf(). Note that floating-point functions are overloaded. float logf(float) This means.5 ulp.2. with the result being a single-precision floating-point number is rintf(). e. C. This combination can be avoided by using the __fadd_rn() and __fmul_rn() intrinsic functions (see Section C. FMAD truncates the intermediate result of the multiplication as mentioned in Section G. whereas rintf() maps to a single instruction.g. It also specifies the error bounds of each function when executed on the device. The recommended way to round a single-precision floating-point operand to an integer.1. C.

Appendix C.sptr. Mathematical Functions Table C-1. otherwise 1 (full range) 2 (full range) 3 (full range) 2 (full range) 2 (full range) 2 (full range) 1 (full range) 1 (full range) 3 (full range) 3 (full range) 2 (full range) 2 (full range) 2 (full range) 4 (full range) 2 (full range) 2 (full range) 4 (full range) 3 (full range) 2 (full range) 3 (full range) 3 (full range) 2 (full range) x*y x/y 1/x rsqrtf(x) 1/sqrtf(x) sqrtf(x) cbrtf(x) rcbrtf(x) hypotf(x.y) expf(x) exp2f(x) exp10f(x) expm1f(x) logf(x) log2f(x) log10f(x) log1pf(x) sinf(x) cosf(x) tanf(x) sincosf(x. 0 for compute capability ≥ 2 when compiled with -prec-sqrt=true 3 (full range). Function x+y Maximum ulp error 0 (IEEE-754 round-to-nearest-even) (except for devices of compute capability 1. otherwise 2 (full range) Applies to 1/sqrtf(x) only when it is converted to rsqrtf(x) by the compiler.x) sinhf(x) coshf(x) 130 CUDA C Programming Guide Version 3.x when addition is merged into an FMAD) 0 (IEEE-754 round-to-nearest-even) (except for devices of compute capability 1.x when multiplication is merged into an FMAD) 0 for compute capability ≥ 2 when compiled with -prec-div=true 2 (full range). Mathematical Standard Library Functions with Maximum ULP Error The maximum error is stated as the absolute value of the difference in ulps between a correctly rounded single-precision result and the result returned by the CUDA library function.2 .cptr) sinpif(x) asinf(x) acosf(x) atanf(x) atan2f(y. otherwise 0 for compute capability ≥ 2 when compiled with -prec-div=true 1 (full range).

Appendix C.l) logbf(x) ilogbf(x) fmodf(x.y) fabsf(x) nanf(cptr) Maximum ulp error 2 (full range) 3 (full range) 4 (full range) 3 (full range) 8 (full range) 3 (full range) 6 (full range) 3 (full range) 7 (full range) 6 (outside interval -10.exp) scalbnf(x.y.z) frexpf(x.y) fminf(x.001 .y.y) remquof(x.y) remainderf(x.y) fmaxf(x.n) scalblnf(x.y) erff(x) erfcf(x) erfinvf(x) erfcinvf(x) lgammaf(x) tgammaf(x) fmaf(x.264.exp) ldexpf(x. Mathematical Functions Function tanhf(x) asinhf(x) acoshf(x) atanhf(x) powf(x.y) truncf(x) roundf(x) rintf(x) nearbyintf(x) ceilf(x) floorf(x) lrintf(x) lroundf(x) llrintf(x) llroundf(x) signbit(x) isinf(x) isnan(x) isfinite(x) copysignf(x..iptr) fdimf(x. -2.. larger inside) 11 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) N/A N/A N/A N/A N/A N/A N/A N/A N/A CUDA C Programming Guide Version 3.iptr) modff(x.2 131 .

trunc(). such as devices of compute capability 1. and floor() each map to a single instruction as well. Function x+y x*y x/y 1/x sqrt(x) rsqrt(x) cbrt(x) rcbrt(x) hypot(x.y) Maximum ulp error N/A C. with the result being a double-precision floating-point number is rint().2 Double-Precision Floating-Point Functions The errors listed below only apply when compiling for devices with native doubleprecision support.2 .Appendix C. The recommended way to round a double-precision floating-point operand to an integer. When compiling for devices without such support. Mathematical Standard Library Functions with Maximum ULP Error The maximum error is stated as the absolute value of the difference in ulps between a correctly rounded double-precision result and the result returned by the CUDA library function. the double type gets demoted to float by default and the double-precision math functions are mapped to their single-precision equivalents. ceil(). Mathematical Functions Function nextafterf(x. whereas rint() maps to a single instruction.2 and lower.cptr) sinpi(x) Maximum ulp error 0 (IEEE-754 round-to-nearest-even) 0 (IEEE-754 round-to-nearest-even) 0 (IEEE-754 round-to-nearest-even) 0 (IEEE-754 round-to-nearest-even) 0 (IEEE-754 round-to-nearest-even) 1 (full range) 1 (full range) 1 (full range) 2 (full range) 1 (full range) 1 (full range) 1 (full range) 1 (full range) 1 (full range) 1 (full range) 1 (full range) 1 (full range) 2 (full range) 2 (full range) 2 (full range) 2 (full range) 2 (full range) 132 CUDA C Programming Guide Version 3.1. The reason is that round() maps to an 8-instruction sequence on the device. Table C-2.y) exp(x) exp2(x) exp10(x) expm1(x) log(x) log2(x) log10(x) log1p(x) sin(x) cos(x) tan(x) sincos(x.sptr. not round().

x) sinh(x) cosh(x) tanh(x) asinh(x) acosh(x) atanh(x) pow(x.n) scalbln(x.iptr) fdim(x.y) remquo(x.exp) ldexp(x.. larger inside) 8 (full range) 0 (IEEE-754 round-to-nearest-even) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) 0 (full range) N/A N/A N/A CUDA C Programming Guide Version 3.2637..y.l) logb(x) ilogb(x) fmod(x.y) trunc(x) round(x) rint(x) nearbyint(x) ceil(x) floor(x) lrint(x) lround(x) llrint(x) llround(x) signbit(x) isinf(x) isnan(x) Maximum ulp error 2 (full range) 2 (full range) 2 (full range) 2 (full range) 1 (full range) 1 (full range) 1 (full range) 2 (full range) 2 (full range) 2 (full range) 2 (full range) 2 (full range) 5 (full range) 8 (full range) 8 (full range) 4 (outside interval -11.Appendix C. Mathematical Functions Function asin(x) acos(x) atan(x) atan2(y.2 133 . -2.y) remainder(x.0001 .iptr) modf(x.y.exp) scalbn(x.y) erf(x) erfc(x) erfinv(x) erfcinv(x) lgamma(x) tgamma(x) fma(x.z) frexp(x.

Also. Functions suffixed with _rd operate using the round-down (to negative infinity) rounding mode.2. for 2126 < y < 2128. The accuracy of floating-point division varies depending on the compute capability of the device and whether the code is compiled with -prec-div=false or -prec-div=true. By contrast. if x is infinity.3 Integer Functions Integer min(x.2 . For 134 CUDA C Programming Guide Version 3.2 Intrinsic Functions This section lists the intrinsic functions that are only supported in device code. but for 2126 < y < 2128. C. Functions suffixed with _rz operate using the round-towards-zero rounding mode.y) Maximum ulp error N/A N/A N/A N/A N/A N/A N/A C.Appendix C.x or for devices of compute capability 2.x when the code is compiled with -prec-div=false. additions and multiplications generated from the '*' and '+' operators will frequently be combined into FMADs. __fdividef(x. __fdividef(x. whereas the “/” operator delivers the correct result to within the accuracy stated in Table C-3. Functions suffixed with _ru operate using the round-up (to positive infinity) rounding mode. but faster versions of some of the functions of Section C.y) delivers a NaN (as a result of multiplying infinity by zero). Among these functions are the less accurate.1.y) are supported and map to a single instruction on the device. C. For devices of compute capability 1. while the “/” operator returns infinity.y) and max(x. both the regular division “/” operator and __fdividef(x. Functions suffixed with _rn operate using the round-to-nearest-even rounding mode. they have the same name prefixed with __ (such as __sinf(x)).y) fmin(x. Mathematical Functions Function isfinite(x) copysign(x.1.y) delivers a result of zero.y) fabs(x) nan(cptr) nextafter(x.1 Single-Precision Floating-Point Functions __fadd_rn() and __fmul_rn() map to addition and multiplication operations that the compiler never merges into FMADs.y) fmax(x.y) have the same accuracy.

ru.41. IEEE-compliant.ru.19.5. Table C-3.41. IEEE-compliant. IEEE-compliant.rz. the maximum ulp error is 3.sptr.rd](x. 2]. Single-Precision Floating-Point Intrinsic Functions Supported by the CUDA Runtime Library with Respective Error Bounds Error bounds IEEE-compliant.ru. the maximum absolute error is 2-24. the maximum absolute error is 2-21.rd](x) (respectively __float2ull_[rn. ].x when the code is compiled with -prec-div=true. IEEE-compliant. N/A __log2f(x) __log10f(x) __sinf(x) __cosf(x) __sincosf(x.ru. The maximum ulp error is The maximum ulp error is Function __fadd_[rn. For x in [0.1. 1 if x is more than 1. For x in [0. the “/” operator is IEEE compliant as mentioned in Section C.rz.y) __fdividef(x. the maximum absolute error is 2-22.rd](x) __fsqrt_[rn.95 * x)).ru. For y in [2-126.rd](x.5. Same as sinf(x) and cosf(x). For x in [-. 2 + floor(abs(2.rz.rz. the maximum absolute error is 2-21. ]. Mathematical Functions devices of compute capability 2.rz.cptr) __tanf(x) __powf(x.rd](x. and larger otherwise.rz. __float2ll_[rn. 2].rd](x)) converts single-precision floating-point parameter x to 64-bit signed (respectively unsigned) integer with specified IEEE- 754 rounding modes. otherwise. CUDA C Programming Guide Version 3.ru.rz. __saturate(x) returns 0 if x is less than 0.1.y. and larger otherwise.y) __fmaf_[rn. and x otherwise. For x in [-.ru.y) __fmul_[rn. the maximum ulp error is 2.16 * x)). the maximum ulp error is 2.5.z) __frcp_[rn.rd](x) __fdiv_[rn.2 135 . otherwise. IEEE-compliant. Derived from its implementation as Derived from its implementation as exp2f(y * __log2f(x)).rd](x.rz. 2]. 2126]. the maximum absolute error is 2-21. otherwise. y) __saturate(x) __sinf(x) * (1 / __cosf(x)). For x in [0. the maximum ulp error is 3.y) __expf(x) __exp10f(x) __logf(x) 2 + floor(abs(1.ru.Appendix C.

rz. Note that this is identical to the Linux function ffs.y) __fma_[rn. __[u]mulhi(x. between 0 and 64 inclusive. If x is 0.y) computes the product of the 64-bit integer parameters x and y and delivers the 64 most significant bits of the 128-bit result.z) __ddiv_[rn. Table C-4.y) __dmul_[rn. Double-Precision Floating-Point Intrinsic Functions Supported by the CUDA Runtime Library with Respective Error Bounds Error bounds IEEE-compliant. The 8 most significant bits of x or y are ignored.ru. between 0 and 32 inclusive.ru. Requires compute capability ≥ 2 IEEE-compliant. __[u]mul64hi(x.2 Double-Precision Floating-Point Functions __dadd_rn() and __dmul_rn() map to addition and multiplication operations that the compiler never merges into FMADs.ru.rz. 136 CUDA C Programming Guide Version 3.2. __ffsll() returns 0. __[u]sad(x. IEEE-compliant.y. IEEE-compliant.rd](x. By contrast. The least significant bit is position 1. __ffsll(x) returns the position of the first (least significant) bit set in 64-bit integer parameter x.rz. Requires compute capability ≥ 2 Function __dadd_[rn. __clz(x) returns the number. bit 31) of integer parameter x.rz.rz. The least significant bit is position 1.z) (Sum of Absolute Difference) returns the sum of integer parameter z and the absolute value of the difference between integer parameters x and y.y) __drcp_[rn.y)(x. of consecutive zero bits starting at the most significant bit (i.y) computes the product of the 24 least significant bits of the integer parameters x and y and delivers the 32 least significant bits of the result. __clzll(x) returns the number.rd](x.e.ru. __ffs(x) returns the position of the first (least significant) bit set in integer parameter x. of consecutive zero bits starting at the most significant bit (i. IEEE-compliant.3 Integer Functions __[u]mul24(x. Requires compute capability ≥ 2. bit 63) of 64-bit integer parameter x.rd](x) C. Note that this is identical to the Linux function ffsll.y. IEEE-compliant.2 .Appendix C.rd](x) __dsqrt_[rn.2.rd](x. __ffs() returns 0. If x is 0. Mathematical Functions C.y) computes the product of the integer parameters x and y and delivers the 32 most significant bits of the 64-bit result.rz. additions and multiplications generated from the '*' and '+' operators will frequently be combined into FMADs.ru.ru.e.rd](x.

Appendix C.2 137 . i. __float2int_rn(1. A type reinterpretation function does not change the binary representation of its input value.rd](x) __float2ll_[rn.rd](x) __int2float_[rn.rz. C. __float_as_int(1.0f) is equal to 1. four bytes from eight input bytes provided in the two input integers x and y. bit N of the result corresponds to bit 63-N of x.ru.rz. bit N of the result corresponds to bit 31-N of x.ru.rd](x) __float2uint_[rn.rz. __int2float_rn(0xC0000000) is equal to -1073741824. The input bytes are indexed as follows: input[0] = x<0:7> input[2] = x<16:23> input[4] = y<0:7> input[6] = y<16:23> input[1] = x<8:15> input[3] = x<24:31> input[5] = y<8:15> input[7] = y<24:31> The selector indices are stored in 4-bit nibbles (with the upper 16-bit of the selector not being used): selector[0] = s<0:3> selector[2] = s<8:11> selector[1] = s<4:7> selector[3] = s<12:15> The returned value r is computed to be: result[n] := input[selector[n]] where result[n] is the nth byte of r.ru. Mathematical Functions __popc(x) returns the number of bits that are set to 1 in the binary representation of 32-bit integer parameter x.y.4 Type Casting Functions There are two categories of type casting functions: the type conversion functions (Table C-5) and the type reinterpretation functions (Table C-6). For example. A type conversion function may change the binary representation of its input value.2. __brev(x) reverses the bits of 32-bit unsigned integer parameter x.s) returns. __brevll(x) reverses the bits of 64-bit unsigned long long parameter x. as a 32-bit integer r.rd](x) CUDA C Programming Guide Version 3.rz. __popcll(x) returns the number of bits that are set to 1 in the binary representation of 64-bit integer parameter x.e.e. Type Conversion Functions __float2int_[rn.ru.0f. __byte_perm(x.rz.rz. Table C-5. __int_as_float(0xC0000000) is equal to -2.0f) is equal to 0x3f800000. i.rd](x) __uint2float_[rn.ru. For example.ru.rd](x) __float2ull_[rn.0f.

Mathematical Functions __ll2float_[rn.ru.Appendix C.rd](x) Table C-6.rd](x) __int2double_rn(x) __uint2double_rn(x) __ll2double_[rn.rd](x) __double2ll_[rn.ru.ru.rz.rz.rd](x) __float2half_rn(x) __half2float(x) __double2float_[rn.rz.rz.rd](x) __double2int_[rn.rz.rd](x) __ull2double_[rn.rz.ru.ru.ru.rz.rz.ru.rd](x) __double2uint_[rn. Type Reinterpretation Functions __int_as_float(x) __float_as_int(x) __double_as_longlong(x) __longlong_as_double(x) __double2hiint(x) __double2loint(x) __hiloint2double(hi. lo) 138 CUDA C Programming Guide Version 3.rz.ru.ru.rd](x) __double2ull_[rn.2 .rd](x) __ull2float_[rn.

In practical terms. D. When either of the multiple functions gets invoked the compiler resolves to the function‟s implementation that matches the function signature.cu CUDA files for host.Appendix D. device. still apply.  The following subsections provide examples of the various constructs. It is valid to use any of these constructs in . Because of implicit typecasting. Any restrictions detailed in previous parts of this programming guide. In practice this means that the compiler will pick the closest match in case of multiple potential matches.1 Polymorphism Generally. this means that it is permissible to define two different functions within the same scope (namespace) as long as they have a distinguishable function signature. Example: The following is valid CUDA code: __device__ void f(float x) { CUDA C Programming Guide Version 3. a compiler may encounter multiple potential matches for a function invocation and in that case the matching rules as described in the C++ Language Standard apply.1 139 . This is also referred to as function (and operator. like the lack of support for recursion. and kernel (__global__) functions. polymorphism is the ability to define that functions or operators behave differently in different contexts.x These C++ constructs are implemented as specified in “The C++ Programming Langue” reference. C++ Language Constructs CUDA supports the following C++ language constructs for device code: Polymorphism  Default Parameters  Operator Overloading  Namespaces  Function Templates  Classes for devices of compute capability 2. That means that the two functions either consume a different number of parameters or parameters of different types. see below) overloading.

0f) { // do something with x } Kernel or other device functions can now invoke this version of f in one of two ways: f(). b. Example: __device__ void f(float x = 0.. /.2 Default Parameters With support for polymorphism as described in the previous subsection and the function signature matching rules in place it becomes possible to provide support for default values for function parameters. Example: The following is valid CUDA code. etc. Default parameters can only be given for the last n parameters of a function. double y) { // do something with x and y } D. a = b = /* some initial value */. &.. Examples of overloadable operators in C++ are: +. []. // or float x = /* some value */.2 . r. . C++ Language Constructs // do something with x } __device__ void f(int i) { // do something with i } __device__ void f(double x. -. f(x). } This new operator can now be used like this: uchar4 a. *. 140 CUDA C Programming Guide Version 3.x = a.x + b. D. const uchar4 & b) { uchar4 r. return r. c.Appendix D. +=.x.3 Operator Overloading Operator overloading allows programmers to define operators for new data-types. implementing the + operation between two uchar4 vectors: __device__ uchar4 operator+ (const uchar4 & a.

All the symbols inside a namespace can be used within this namespaces without additional syntax.4 Namespaces Namespaces in C++ allow for the creation of a hierarchy of scopes of visibility. D.} } namespace other { __device__ void f(float x) { /* do something with x */ .5 Function Templates Function templates are a form of meta-programming that allows writing a generic function in a data-type independent fashion. f() can be invoked in two ways: int x = 1.   Example: template <T> __device__ bool f(T x) { return /* some clever code that turns x into a bool here */ } This function will convert x of any data-type to a bool as long as the code in the function‟s body can be compiled for the actually type (T) of the variable x.5f). Explicit instantiation. CUDA supports function templates to the full extent of the C++ standard. D. CUDA C Programming Guide Version 3. which commonly occurs when using multiple function libraries from different sources. All the symbols in a namespace can be imported into another namespace (scope) like this: using namespace nvidia. including the following concepts: Implicit template parameter deduction.} } The functions can now be used anywhere via fully qualified names: nvidia::f(0.5f). C++ Language Constructs c = a + b. Example: The following code defines two functions “f()” in two separate namespaces (“nvidia” and “other”): namespace nvidia { __device__ void f(float x) { /* do something with x */ .Appendix D.  Template specialization.2 141 . f(0. The use of namespaces can be used to solve the problem of name-clashes (two different symbols using identical names).

 Functor classes. 2D and 3D points. E.2 142 . data types like pixels (r. C++ Language Constructs bool result = f(x). g.  D. The use of functors is necessitated by the fact that devicefunction pointers are not supported and thus it is not possible to pass functions as template parameters.6. } template <> __device__ bool f<int>(T x) { return true. } CUDA C Programming Guide Version 3. A workaround for this restriction is the use of functor classes (see code sample below). Function templates may be specialized: template <T> __device__ bool f(T x) { return false. a_(0) { . a). g_(0). The complete set of matching rules (for implicitly deducing template parameters) and matching polymorphous functions apply as specified in the C++ standard. This first type of invocation relies on the compiler‟s ability to implicitly deduce the correct function type for T. The second type of invoking the template function is via explicit instantiation like this: bool result = f<double>(0.Appendix D. all other types will be caught by the more general template and return false. etc. b. vectors. There are two common use cases for classes without virtual member functions: Small-data aggregations. as long as none of the member functions are virtual (this restriction will be removed in some future release). D. b_(0).6 Classes Code compiled for devices with compute capability 2. In this case the compiler would deduce T to be int and instantiate f<int>(x). } In this case the implementation for T representing the int type are specialized to return true.x and higher may make use of C++ classes.g.1 Example 1 Pixel Data Type The following is an example of a data type for RGBA pixels with 8 bit per channel depth: class PixelRGBA { public: __device__ PixelRGBA(): r_(0).5).

g_. p1.] initialization of p1 and p2 here PixelRGBA p3 = p1 + p2. // [. p1. unsigned char g.a_ + p2.r_ + p2.a_). __device__ PixelRGBA operator+(const PixelRGBA & p1.. }. Here are two functors for float addition and subtraction: class Add { public: __device__ float operator() (float a. unsigned char b. a_(a) { .b_.6.Appendix D. p1.2 Example 2 Functor Class The following example shows how functors may be used as function template parameters to implement a set of vector arithmetic operations.b_ + p2. } // other methods and operators left out for sake of brevity private: unsigned char r_.2 143 . class Sub { public: __device__ float CUDA C Programming Guide Version 3. p2. b_.g_. } Other device code can now make use of this new data type as one would expect: PixelRGBA p1.r_. C++ Language Constructs __device__ PixelRGBA(unsigned char r. const PixelRGBA &). const PixelRGBA & p2) { return PixelRGBA(p1.g_ + p2. a_.. b_(b). float b) const { return a + b. friend PixelRGBA operator+(const PixelRGBA &. } }. D. g_(g). unsigned char a = 255): r_(r).

144 CUDA C Programming Guide Version 3.b. } }.x. v3.x + threadIdx. } } The VectorOperation kernel may now be launched like this in order to get a vector addition: // Host code VectorOperation<<<blocks.2 . The following templatized kernel makes use of the functors like the ones above in order to implement operations on vectors of floats: // Device code template<class O> __global__ void VectorOperation(const float * A. N. if (iElement < N) { C[iElement] = op(A[iElement]. threads>>>(v1. const float * B. float * C.Appendix D. unsigned int N. v2. Add()). C++ Language Constructs operator() (float a. B[iElement]). float b) const { return a . O op) { unsigned int iElement = blockDim.x * blockIdx.

When compiling code for devices of compute capability 2.x. a __device__ function is always inlined by default. It is optionally followed by a number that specifies how many times the loop must be unrolled. NVCC Specifics E. ++i) the loop will be unrolled 5 times. the compiler unrolls small loops with a known trip count. the compiler will always honor the __noinline__ qualifier. The __noinline__ function qualifier can be used as a hint for the compiler not to inline the function if possible. For devices of compute capability 1. It must be placed immediately before the loop and only applies to that loop. for example).1 145 . The function body must still be in the same file where it is called. i < n.1 __noinline__ and __forceinline__ When compiling code for devices of compute capability 1. It is up to the programmer to make sure that the specified unroll number gives the best performance.x. For devices of compute capability 2. The compiler will also insert code to ensure correctness (in the example above. a __device__ function is only inlined when deemed appropriate by the compiler. The #pragma unroll directive however can be used to control unrolling of any given loop.2 #pragma unroll By default. The __forceinline__ function qualifier can be used to force the compiler to inline the function. For example. CUDA C Programming Guide Version 3. in this code sample: #pragma unroll 5 for (int i = 0. #pragma unroll 1 will prevent the compiler from ever unrolling a loop. to ensure that there will only be n iterations if n is less than 5. the compiler will not honor the __noinline__ qualifier for functions with pointer parameters and for functions with large parameter lists.x.x.Appendix E. E.

. c[4] = a[0] * b[0]. const float* __restrict__ b. const float* b. float* c) { c[0] = a[0] * b[0]. the pointers a. where use of restricted pointer can help the compiler to reduce the number of instructions: void foo(const float* a. NVCC Specifics If no number is specified after #pragma unroll. which in this case means writes through c would never overwrite elements of a or b.Appendix E. float* __restrict__ c). and c restricted pointers. and c may be aliased. b. c[1] = a[0] * b[0]. otherwise it is not unrolled at all. the compiler cannot load a[0] and b[0] into registers. and which inhibits all kind of optimization from code reordering to common sub-expression elimination. 146 CUDA C Programming Guide Version 3. so any write through c could modify elements of a or b. E. c[2] = a[0] * b[0] * a[1]. This means that to guarantee functional correctness.. the compiler cannot just reorder the computation of c[4] into the proximity of the computation of c[0] and c[1] because the preceding write to c[3] could change the inputs to the computation of c[4]. Likewise.2 . say. Restricted pointers were introduced in C99 to alleviate the aliasing problem that exists in C-type languages. float* __restrict__ c) { float t0 = a[0]. } In C-type languages. const float* __restrict__ b. multiply them.3 __restrict__ nvcc supports restricted pointers via the __restrict__ keyword. With the __restrict keywords added. This changes the function prototype as follows: void foo(const float* __restrict__ a. c[5] = b[0]. By making a. Here is an example subject to the aliasing issue. while retaining functionality identical with the abstract execution model: void foo(const float* __restrict__ a. because the results would differ from the abstract execution model if.. b. the compiler can now reorder and do common sub-expression elimination at will. So the compiler cannot take advantage of the common sub-expression. the loop is completely unrolled if its trip count is constant. the programmer asserts to the compiler that the pointers are in fact not aliased. Note that all pointer arguments need to be made restricted for the compiler optimizer to derive any benefit. and store the result to both c[0] and c[1]. c[3] = a[0] * a[1]. a[0] is really the same location as c[0].

CUDA C Programming Guide Version 3.2 147 . float t3 = a[1]. c[4] = t2. NVCC Specifics float t1 = b[0]. c[2] = t2 * t3. c[3] = t0 * t3. due to reduced occupancy. Since register pressure is a critical issue in many CUDA codes. use of restricted pointers can have negative performance impact on CUDA code. This is balanced by an increase in register pressure due to "cached" loads and common sub-expressions. } The effects here are a reduced number of memory accesses and reduced number of computations. . c[5] = t1.. float t2 = t0 * t2. c[1] = t2..Appendix E. c[0] = t2.

.

2. x .Appendix F. x is replaced by 0 if x  0 and 1  1 N if 1  x . y . If x is non-normalized. or N  M  L texels for a three-dimensional texture. CUDA C Programming Guide Version 3. y . In the remaining of the appendix. In wrap addressing mode. y . The texture bound to the texture reference is represented as an array T of N texels for a one-dimensional texture. and z are the non-normalized texture coordinates remapped to T ‟s valid addressing range. The addressing mode specifies how an out-of-range texture coordinate x is remapped to the valid range. y .1 149 . and z as such: x  Nx . y  My . and ˆ z  Lz . A texture coordinate must fall within T ‟s valid addressing range before it can be used to address T . where frac( x)  x  floor( x) and floor(x) is the largest integer not greater than x .4). x . x is replaced by frac(x) . and z are derived from ˆ ˆ ˆ ˆ ˆ the normalized texture coordinates x . and z . If x is normalized:   In clamp addressing mode. Texture Fetching This appendix gives the formula used to compute the value returned by the texture functions of Section B. It is fetched using texture coordinates x . N  M texels for a two-dimensional texture. only the clamp addressing mode is supported and x is replaced by 0 if x  0 and N  1 if N  x .8 depending on the various attributes of the texture reference (see Section 3.

which is only available for floating-point textures.5 3 0. k ] for a three-dimensional texture.2 .1 Nearest-Point Sampling In this filtering mode.Appendix F. For integer textures. 150 CUDA C Programming Guide Version 3. the value returned by the texture fetch can be optionally remapped to [0. the value returned by the texture fetch is    tex( x)  T [i] for a one-dimensional texture. j ] for a two-dimensional texture. Nearest-Point Sampling of a One-Dimensional Texture of Four Texels F. tex( x.4.1). y.2. z)  T [i. j. 1. Texture Fetching F. y)  T [i. j  floor(y) .1.0.25 2 0. and k  floor(z) . Figure D-1 illustrates nearest-point sampling for a one-dimensional texture with N 4. where i  floor(x) .75 4 1 Non-Normalized Normalized Figure F-1.2 Linear Filtering In this filtering mode. tex(x) T[3] T[0] T[2] T[1] x 0 0 1 0. tex( x.0] (see Section 3. the value returned by the texture fetch is  tex( x)  (1   )T [i]  T [i  1] for a one-dimensional texture.

and  are stored in 9-bit fixed point format with 8 bits of fractional value (so 1.   frac( y B ) . k ]   (1   )T [i  1. j  1. j . where:    i  floor( x B ) . j  floor( y B ) .75 4 1 Non-Normalized Normalized Figure F-2. j  1] for a two-dimensional texture. j  1]   T [i  1. .5 . j  1. k ]  (1   )  (1   )T [i. x B  x  0. tex(x) T[3] T[0] T[2] T[1] x 0 0 1 0.  . y B  y  0.   frac( z B ) . j ]  (1   )T [i. j . k ]   (1   )(1   )T [i  1. k  1]  (1   ) T [i. k  floor( z B ) . j ]   (1   )T [i  1.5 3 0. y)  (1   )(1   )T [i. Texture Fetching   tex( x. k  1]   (1   )T [i  1. j  1.2 151 .5 .Appendix F. j  1.25 2 0. k  1]  T [i  1. z B  z  0. tex( x. j . k ]  (1   )(1   )T [i. j .5 . k  1]  for a three-dimensional texture. y. z )  (1   )(1   )(1   )T [i.0 is exactly represented). Linear Filtering of a One-Dimensional Texture of Four Texels in Clamp Addressing Mode CUDA C Programming Guide Version 3.   frac( x B ) .  Figure F-2 illustrates nearest-point sampling for a one-dimensional texture with N 4.

3 Table Lookup A table lookup TL(x) where TL( x)  tex ( x spans the interval [0. TL(x) T[3] T[0] T[2] T[1] x 0 0 4/3 1/3 8/3 2/3 4 1 Figure F-3. One-Dimensional Table Lookup Using Linear Filtering 152 CUDA C Programming Guide Version 3. R] can be implemented as N 1 x  0.Appendix F.5) in order to ensure that TL(0)  T [0] and TL( R)  T [ N  1] .2 . R Figure F-3 illustrates the use of texture filtering to implement a table lookup with R  4 or R  1 from a one-dimensional texture with N  4 . Texture Fetching F.

1 gives the features and technical specifications associated to each compute capability.5). Section G.2 reviews the compliance with the IEEE floating-point standard.3 and 0 give more details on the architecture of devices of compute capability 1. Section G. respectively.Appendix G.1 153 . Section G. CUDA C Programming Guide Version 3.x and 2. Compute Capabilities The general specifications and features of a compute device depend on its compute capability (see Section 2.x.

0 1.11) __ballot() (Section B.11) Integer atomic functions operating on 32-bit words in shared memory (Section B.x 1024 1024 154 CUDA C Programming Guide Version 3.1 1.11) Warp vote functions (Section B.2 65535 1.1 Features and Technical Specifications Compute Capability Feature Support (Unlisted features are supported for all compute capabilities) Integer atomic functions operating on 32-bit words in global memory (Section B.or y-dimension of a grid of thread blocks Maximum number of threads per block Maximum x. Compute Capabilities G.Appendix G.or y-dimension of a block Maximum z-dimension of a block Warp size Maximum number of resident blocks per multiprocessor Maximum number of resident warps per multiprocessor Maximum number of resident threads per multiprocessor Number of 32-bit registers per multiprocessor Maximum amount of shared memory 24 768 8K 16 KB 512 512 64 32 8 32 1024 16 K 48 1536 32 K 48 KB 1.x Compute Capability Technical Specifications Maximum x.6) Surface functions (Section B.11) Integer atomic functions operating on 64-bit words in global memory (Section B.2 .2 1. __syncthreads_and().12) __threadfence_system() (Section B. __syncthreads_or() (Section B.0 1.12) Double-precision floating-point numbers Floating-point atomic addition operating on 32-bit words in global and shared memory (Section B.5) __syncthreads_count().1 1.9) No Yes No Yes No Yes No yes 1.3 2.3 2.

Appendix G. while SNaN encodings are supported.x 2048 x 2048 x 2048 128 8192 8192 x 8192 8 G.1 1. for the same reason. Compute Capabilities Compute Capability Technical Specifications per multiprocessor Number of shared memory banks Amount of local memory per thread Constant memory size Cache working set per multiprocessor for constant memory Cache working set per multiprocessor for texture memory Maximum width for a 1D texture reference bound to a CUDA array Maximum width for a 1D texture reference bound to linear memory Maximum width and height for a 2D texture reference bound to linear memory or to a CUDA array Maximum width. exposed via device intrinsics.2 Floating-Point Standard All compute devices follow the IEEE 754-2008 standard for binary floating-point arithmetic with the following deviations: There is no dynamically configurable rounding mode.  CUDA C Programming Guide Version 3.0 1. and deliver the masked response as defined by IEEE-754 if there is an exceptional event.2 1.3 2. and depth for a 3D texture reference bound to linear memory or a CUDA array Maximum number of textures that can be bound to a kernel Maximum width for a 1D surface reference bound to a CUDA array Maximum width and height for a 2D surface reference bound to a CUDA array Maximum number of surfaces that can be bound to a kernel Maximum number of instructions per kernel 2 million N/A 16 16 KB 64 KB 8 KB Device dependent.2 155 . they are not signaling and are handled as quiet. between 6 KB and 8 KB 8192 227 65536 x 32768 65536 x 65535 32768 32 512 KB 1. height.  The result of a single-precision floating-point operation involving one or more input NaNs is the quiet NaN of bit pattern 0x7fffffff. most of the operations support multiple IEEE rounding modes.  There is no mechanism for detecting that a floating-point exception has occurred and all operations behave as if the IEEE-754 exceptions are always masked. however.

2 . -prec-div=true.x.u. __fmul_r[u.e.d](float. floating-point arithmetic and comparison instructions convert denormalized operands to zero prior to the floating-point operation.d}(float. and 156 CUDA C Programming Guide Version 3.x:  Round-to-nearest-even is the only supported IEEE rounding mode for reciprocal.  To mitigate the impact of these restrictions.Appendix G. only round-to-nearest-even and round-towards-zero are supported via static rounding modes. For devices of compute capability 2. which truncates (i.d](float): single-precision square root with IEEE rounding modes.u. IEEE-compliant software (and therefore slower) implementations are provided through the following intrinsics (c.u.  Underflowed results are flushed to zero. float.e.z.u. __fadd_r[u. __frcp_r[n. float): single-precision addition with IEEE directed rounding. devices of compute capability 1.  For addition and multiplication. i. Section C.d](float. without rounding) the intermediate mantissa of the multiplication.x:  Denormalized numbers are not supported.  Division is implemented via the reciprocal in a non-standard-compliant way. code compiled with -ftz=true.z. __fdiv_r[n.  Square root is implemented via the reciprocal square root in a nonstandard-compliant way. these are passed through unchanged.z. and square root. each double variable is converted to single-precision floating-point format (but retains its size of 64 bits) and doubleprecision floating-point arithmetic gets demoted to single-precision floating-point arithmetic.z. Compute Capabilities Double-precision floating-point absolute value and negation are not compliant with IEEE-754 with respect to NaNs.  For single-precision floating-point numbers on devices of compute capability 1.d](float. see the nvcc user manual for description of these compilation flags). float): single-precision fused multiply-add with IEEE rounding modes.1):        __fmaf_r{n. directed rounding towards +/.infinity is not supported. float): single-precision multiplication with IEEE directed rounding.2 and lower. and -prec-sqrt=true to ensure IEEE compliance (this is the default setting. When compiling for devices without native double-precision floating-point support. code must be compiled with -ftz=false.2. -prec-div=false.  Some instructions are not IEEE-compliant:  Addition and multiplication are often combined into a single multiplyadd instruction (FMAD). __fsqrt_r[n. For double-precision floating-point numbers on devices of compute capability 1.d](float): single-precision reciprocal with IEEE rounding modes.f. division. float): single-precision division with IEEE rounding modes.

 16 clock cycles for a single-precision floating-point transcendental instruction. This is unlike the x86 architecture behavior.  32 clock cycles for a double-precision floating-point arithmetic instruction. on the other hand.3.  1 warp scheduler. fmin(). if one of the input parameters to fminf().  In accordance to the IEEE-754R standard.x Architecture For devices of compute capability 1. Addition and multiplication are often combined into a single multiply-add instruction: FMAD for single precision on devices of compute capability 1.  FFMA for single precision on devices of compute capability 2. To execute an instruction for all threads of a warp. which resides in device memory.x. The conversion of a floating-point value to an integer value in the case where the floating-point value falls outside the range of the integer format is left undefined by IEEE-754. FFMA.2 157 . While FFMA in general has superior numerical properties compared to FMAD.Appendix G. is an IEEE-754(2008) compliant fused multiply-add instruction. so the full-width product is being used in the addition and a single rounding occurs during generation of the final result.3 G.1 Compute Capability 1. the behavior is to clamp to the end of the supported range. a multiprocessor consists of: 8 CUDA cores for integer and single-precision floating-point arithmetic operations.x. or fmax() is NaN. fmaxf(). the switch from FMAD to FFMA can cause slight changes in numeric results and can in rare circumstances lead to slighty larger error in final results.  1 double-precision floating-point unit for double-precision floating-point arithmetic operations. Compute Capabilities -prec-sqrt=false comes closest to the code generated for devices of compute capability 1. A multiprocessor also has a read-only constant cache that is shared by all functional units and speeds up reads from the constant memory space. but not the other. the result is the non-NaN parameter. G.  2 special function units for single-precision floating-point transcendental functions (these units can also handle single-precision floating-point multiplications). the warp scheduler must therefore issue the instruction over:  4 clock cycles for an integer or single-precision floating-point arithmetic instruction. As mentioned above.x. FMAD truncates the mantissa prior to use it in the addition.x.  CUDA C Programming Guide Version 3. For compute devices.

 8.2 .1 To coalesce. or 16. respectively. all 16 words must lie in the same 64-byte segment. the memory request for a half-warp must satisfy the following conditions: The size of the words accessed by the threads must be 4. one for each half-warp. 8.2. Sections G. Figure G-1 shows some examples of global memory accesses and corresponding memory transactions based on compute capability. G. there are some inactive threads that do not actually access memory.2. Coalescing is achieved even if the warp is divergent.3. This is in contrast with devices of compute capabilities 1.2 and 1. a 128-byte memory transaction. Each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering mentioned in Section 3. that are issued independently. including the same words.  The local and global memory spaces reside in device memory and are not cached.   If the half-warp does not meet these requirements.2 Devices of Compute Capability 1.2.  3 for devices of compute capabilities 1.1.2 and 1.2 Global Memory A global memory request for a warp is split into two memory requests.4. and a single memory transaction for each segment addressed by the half-warp is issued.0 and 1. G. all 16 words must lie in the same 128-byte segment. or two 128-byte memory transactions are issued if the size of the words accessed by the threads is 4. which resides in device memory. a 64-byte memory transaction.3.3. If the half-warp meets these requirements. the first 8 words must lie in the same 128-byte segment and the last 8 words in the following 128-byte segment.3.3.2 describe how the memory accesses of threads within a half-warp are coalesced into one or more memory transactions depending on the compute capability of the device. The resulting memory transactions are serviced at the throughput of device memory. Each TPC has a read-only texture cache that is shared by all multiprocessors and speeds up reads from the texture memory space. 8.2. The number of multiprocessors per TPC is: 2 for devices of compute capabilities 1.1 Devices of Compute Capability 1. i. Compute Capabilities Multiprocessors are grouped into Texture Processor Clusters (TPCs). or 16 bytes.1 and G.Appendix G.  16.3 Threads can access any words in any order.0 and 1.3.2. 16 separate 32-byte memory transactions are issued.e. If this size is:  4.  Threads must access the words in sequence: The kth thread in the half-warp must access the kth word.1 where threads need to access words in sequence and coalescing only happens if the half-warp addresses a single segment. G. 158 CUDA C Programming Guide Version 3.0 and 1.

reduce the transaction size to 64 bytes. The same examples apply for devices of compute capability 1. Carry out the transaction and mark the serviced threads as inactive.3. Figure G-2 shows some examples of strided access for devices of compute capability 2. the following protocol is used to determine the memory transactions necessary to service all threads in a half-warp:      Find the memory segment that contains the address requested by the lowest numbered active thread.e. G.3 Shared Memory Shared memory has 16 banks that are organized such that successive 32-bit words are assigned to successive banks. 16) is less than or equal to 16/d. that are issued independently.e. G. i. that is only if d is equal to 1.and 16-byte words. As a consequence. A shared memory request for a warp is split into two memory requests. 16) or. interleaved. equivalently. whenever n is a multiple of 16/d where d is the greatest common divisor of 16 and s. if possible:  If the transaction size is 128 bytes and only the lower or upper half is used. Reduce the transaction size. i. there can be no bank conflict between a thread belonging to the first half of a warp and a thread belonging to the second half of the same warp.e. but with 16 banks instead of 32. Compute Capabilities More precisely. s is odd. Repeat until all threads in the half-warp are serviced. The segment size depends on the size of the words accessed by the threads:  32 bytes for 1-byte words.2 159 . one for each half-warp. Find all other active threads whose requested address lies in the same segment. As a consequence. only one thread per halfwarp performs a write and which thread performs the final write is undefined.1 32-Bit Strided Access A common access pattern is for each thread to access a 32-bit word from an array indexed by the thread ID tid and with some stride s: __shared__ float shared[32].x.  If the transaction size is 64 bytes (originally or after reduction from 128 bytes) and only the lower or upper half is used. threads tid and tid+n access the same bank whenever s*n is a multiple of the number of banks (i.x. Each bank has a bandwidth of 32 bits per two clock cycles. there will be no bank conflict only if half the warp size (i. 8. In this case. CUDA C Programming Guide Version 3.. If a non-atomic instruction executed by a warp writes to the same location in shared memory for more than one of the threads of the warp.  64 bytes for 2-byte words.Appendix G. float data = shared[BaseIndex + s * tid].3.3.e. reduce the transaction size to 32 bytes.  128 bytes for 4-.

3. The same examples apply for devices of compute capability 1.2 .4 Larger Than 32-Bit Access Accesses that are larger than 32-bit per thread are split into 32-bit accesses that typically generate bank conflicts. shared[2]. For example.3. but with 16 banks instead of 32. There are no bank conflicts however. as the memory request is compiled into two separate 32-bit requests with a stride of two. shared[1].  One address for each bank (other than the broadcasting bank) pointed to by the remaining addresses. and shared[3]. the subset is built from the remaining addresses that have yet to be serviced using the following procedure: Select one of the words pointed to by the remaining addresses as the broadcast word. if the same array is accessed the following way: char data = shared[BaseIndex + 4 * tid].3.2 32-Bit Broadcast Access Shared memory features a broadcast mechanism whereby a 32-bit word can be read and broadcast to several threads simultaneously when servicing one memory read request. for example. Compute Capabilities G.3 8-Bit and 16-Bit Access 8-bit and 16-bit accesses typically generate bank conflicts.  A common conflict-free case is when all threads of a half-warp read from an address within the same 32-bit word. at each step.3. Which word is selected as the broadcast word and which address is picked up for each bank at each cycle are unspecified. One way to avoid bank conflicts in this case is two split the double operands like in the following sample code: __shared__ int shared_lo[32].3. This reduces the number of bank conflicts when several threads read from an address within the same 32-bit word.x. double data = shared[BaseIndex + tid]. char data = shared[BaseIndex + tid].  Include in the subset:  All addresses that are within the broadcast word. because shared[0]. 160 CUDA C Programming Guide Version 3. there are 2-way bank conflicts for arrays of doubles accessed as follows: __shared__ double shared[32]. More precisely. G. Figure G-3 shows some examples of memory read accesses that involve the broadcast mechanism. belong to the same bank. G.3. a memory read request made of several addresses is serviced in several steps over time by servicing one conflict-free subset of these addresses per step until all addresses have been serviced. __shared__ int shared_hi[32]. For example.Appendix G. there are bank conflicts if an array of char is accessed the following way: __shared__ char shared[32].

x. The following code.Appendix G. shared_hi[BaseIndex + tid] = __double2hiint(dataIn). The first scheduler is in charge of the warps with an odd ID and the second scheduler is in charge of the warps with an  CUDA C Programming Guide Version 3. At every instruction issue time. y. struct type data = shared[BaseIndex + tid]. for some warp that is ready to execute.1 Compute Capability 2. Compute Capabilities double dataIn.0:  32 CUDA cores for integer and floating-point arithmetic operations. if any.4. This might not always improve performance however and does perform worse on devices of compute capabilities 2. }.  For devices of compute capability 2. each scheduler issues:  One instruction for devices of compute capability 2. }.2 161 . since each member is accessed with an odd stride of three 32-bit words.  4 special function units for single-precision floating-point transcendental functions.  Two separate reads with bank conflicts if type is defined as struct type { float x.1. results in:  Three separate reads without bank conflicts if type is defined as struct type { float x.0.x. shared_lo[BaseIndex + tid]). z.4 G.  8 special function units for single-precision floating-point transcendental functions. G.1:  48 CUDA cores for integer and floating-point arithmetic operations.  2 warp schedulers. shared_lo[BaseIndex + tid] = __double2loint(dataIn). The same applies to structure assignments.  Two instructions for devices of compute capability 2.x Architecture For devices of compute capability 2. double dataOut = __hiloint2double(shared_hi[BaseIndex + tid]. a multiprocessor consists of: For devices of compute capability 2. for example: __shared__ struct type shared[32]. since each member is accessed with an even stride of two 32-bit words. y.

..g. To execute an instruction for all threads of a warp. Multiprocessors are grouped into Graphics Processor Clusters (GPCs). The same on-chip memory is used for both L1 and shared memory: It can be configured as 48 KB of shared memory and 16 KB of L1 cache or as 16 KB of shared memory and 48 KB of L1 cache. then it will default to the preference of the current thread/context. A GPC includes four multiprocessors. whether reads are cached in both L1 and L2 or in L2 only) can be partially configured on a peraccess basis using modifiers to the load or store instruction. There is an L1 cache for each multiprocessor and an L2 cache shared by all multiprocessors. The cache behavior (e. A multiprocessor also has a read-only uniform cache that is shared by all functional units and speeds up reads from the constant memory space. If the current thread/context also has no preference (which is again the default setting). The initial configuration is 48KB of shared memory and 16KB of L1 cache. Compute Capabilities even ID.g. Note that when a scheduler issues a double-precision floating-point instruction. unless a different cache configuration is required to launch the kernel (e. cudaFuncCachePreferShared) // Driver API // CU_FUNC_CACHE_PREFER_SHARED: shared memory is 48 KB // CU_FUNC_CACHE_PREFER_L1: shared memory is 16 KB // CU_FUNC_CACHE_PREFER_NONE: no preference CUfunction myKernel. } // Host code // Runtime API // cudaFuncCachePreferShared: shared memory is 48 KB // cudaFuncCachePreferL1: shared memory is 16 KB // cudaFuncCachePreferNone: no preference cudaFuncSetCacheConfig(MyKernel." meaning "no preference. 162 CUDA C Programming Guide Version 3. which is set using cudaThreadSetCacheConfig()/cuCtxSetCacheConfig() (see the reference manual for details).2 . the other scheduler cannot issue any instruction. due to shared memory requirements). a warp scheduler must therefore issue the instruction over two clock cycles for an integer or floating-point arithmetic instruction.." If a kernel is configured to have no preference. using cudaFuncSetCacheConfig()/cuFuncSetCacheConfig(): // Device code __global__ void MyKernel() { . then whichever cache configuration was most recently used for any kernel will be the one that is used.Appendix G. which resides in device memory. including temporary register spills. A warp scheduler can issue an instruction to only half of the CUDA cores. CU_FUNC_CACHE_PREFER_SHARED) The default cache configuration is "prefer none. cuFuncSetCacheConfig(myKernel. both of which are used to cache accesses to local or global memory.

CUDA C Programming Guide Version 3. Memory accesses that are cached in both L1 and L2 are serviced with 128-byte memory transactions whereas memory accesses that are cached in L2 only are serviced with 32-byte memory transactions. only one thread performs a write and which thread does it is undefined.Appendix G. otherwise. Caching in L2 only can therefore reduce over-fetch. or at the throughput of device memory. A cache line request is serviced at the throughput of L1 or L2 cache in case of a cache hit. one for each half-warp. including the same words. a memory request by a warp is first split into separate 128-byte memory requests that are issued independently: Two memory requests.2. Using the –dlcm compilation flag.  Note that threads can access any words in any order. one for each quarter-warp. they can be configured at compile time to be cached in both L1 and L2 (-Xptxas -dlcm=ca) (this is the default setting) or in L2 only (-Xptxas -dlcm=cg). G.2 163 . If a non-atomic instruction executed by a warp writes to the same location in global memory for more than one of the threads of the warp.4. for example.2 Global Memory Global memory accesses are cached.  Four memory requests. if the size is 8 bytes. A cache line is 128 bytes and maps to a 128-byte aligned segment in device memory. If the size of the words accessed by each thread is more than 4 bytes. if the size is 16 bytes. It accesses the texture cache via a texture unit that implements the various addressing modes and data filtering mentioned in Section 3. Each memory request is then broken down into cache line requests that are issued independently.4. which resides in device memory. Compute Capabilities Each multiprocessor has a read-only texture cache to speed up reads from the texture memory space. in the case of scattered memory accesses.

3 31 2.Appendix G.3 31 2.0 Cached 1 x 128B at 128 1 x 128B at 256 Uncached 7x 8x 8x 8x 1x 32B at 128 32B at 160 32B at 192 32B at 224 32B at 256 1 x 128B at 128 1 x 64B at 192 1 x 32B at 256 Figure G-1.1 … 1.2 and 1.2 .2 and 1.0 and 1.3 31 2.2 and 1. 4-Byte Word per Thread.0 Cached 1 x 128B at 128 Uncached 8x 8x 8x 8x 32B at 128 32B at 160 32B at 192 32B at 224 1 x 64B at 128 1 x 64B at 192 Misaligned and sequential Addresses: 96 128 160 192 224 256 288 Threads: Compute capability: Memory transactions: 0 1. Compute Capabilities Aligned and sequential Addresses: 96 128 160 192 224 256 288 Threads: Compute capability: Memory transactions: 0 1.0 and 1.1 … 1. Examples of Global Memory Accesses by a Warp.0 and 1.0 Cached 1 x 128B at 128 Uncached 1 x 64B at 128 1 x 64B at 192 1 x 64B at 128 1 x 64B at 192 Aligned and non-sequential Addresses: 96 128 160 192 224 256 288 Threads: Compute capability: Memory transactions: 0 1.1 … 1. and Associated Memory Transactions Based on Compute Capability 164 CUDA C Programming Guide Version 3.

that is only if d is equal to 1.2 Larger Than 32-Bit Access 64-bit and 128-bit accesses are specifically handled to minimize bank conflicts as described below. there is no bank conflict between these threads: For read accesses.1 32-Bit Strided Access A common access pattern is for each thread to access a 32-bit word from an array indexed by the thread ID tid and with some stride s: __shared__ float shared[32]. 32) is less than or equal to 32/d. y. whenever n is a multiple of 32/d where d is the greatest common divisor of 32 and s. If two or more threads access any bytes within the same 32-bit word.2 165 . The following code.Appendix G. This means. Therefore. for example: struct type { float x. or 128-bit accesses. Other accesses larger than 32-bit are split into 32-bit.4. 64-Bit Accesses For 64-bit accesses. in particular.4. Compute Capabilities G. that unlike for devices of compute capability 1. float data = shared[BaseIndex + s * tid]. z. results in three separate 32-bit reads without bank conflicts since each member is accessed with a stride of three 32-bit words.x. each byte is written by only one of the threads (which thread performs the write is undefined). Figure G-2 shows some examples of strided access.4. __shared__ struct type shared[32]. Each bank has a bandwidth of 32 bits per two clock cycles. G. for write accesses. 32) or.e. As a consequence. CUDA C Programming Guide Version 3. i. for example: __shared__ char shared[32]. interleaved. }.e. unlike for devices of lower compute capability.e. G. a bank conflict only occurs if two or more threads in either of the half-warps access different addresses belonging to the same bank. A bank conflict only occurs if two or more threads access any bytes within different 32-bit words belonging to the same bank. char data = shared[BaseIndex + tid]. threads tid and tid+n access the same bank whenever s*n is a multiple of the number of banks (i. s is odd. there will be no bank conflict only if the warp size (i.e.3 Shared Memory Shared memory has 32 banks that are organized such that successive 32-bit words are assigned to successive banks. the word is broadcast to the requesting threads (unlike for devices of compute capability 1. there may be bank conflicts between a thread belonging to the first half of a warp and a thread belonging to the second half of the same warp. In this case.x. multiple words can be broadcast in a single transaction). 64-bit. i. there are no bank conflicts if an array of char is accessed as follows. equivalently.3. struct type data = shared[BaseIndex + tid]..3.

Compute Capabilities Unlike for devices of compute capability 1.  166 CUDA C Programming Guide Version 3. double data = shared[BaseIndex + tid]. to determine the ways of bank conflicts. even if no two threads in a quarter-warp access different addresses belonging to the same bank.  read-only in the kernel (programmer can enforce this using the const keyword).x. 128-Bit Accesses The majority of 128-bit accesses will cause 2-way bank conflicts.4 Constant Memory In addition to the constant memory space supported by devices of all compute capabilities (where __constant__ variables reside).2 .Appendix G. G. for example: __shared__ double shared[32].x support the LDU (LoaD Uniform) instruction that the compiler use to load any variable that is: pointing to global memory. devices of compute capability 2.  not dependent on thread ID. Therefore. one must add 1 to the maximum number of threads in a quarter-warp that access different addresses belonging to the same bank. there are no bank conflicts for arrays of doubles accessed as follows.4.

2 167 . Compute Capabilities Threads: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Banks: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Threads: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Banks: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Threads: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Banks: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Left: Linear addressing with a stride of one 32-bit word (no bank conflict).Appendix G. Middle: Linear addressing with a stride of two 32-bit words (2-way bank conflicts).x CUDA C Programming Guide Version 3. Right: Linear addressing with a stride of three 32-bit words (no bank conflict). Figure G-2 Examples of Strided Shared Memory Accesses for Devices of Compute Capability 2.

168 CUDA C Programming Guide Version 3.2 . and 9 access the same word within bank 5. 7. Right: Conflict-free broadcast access (all threads access the same word). Middle: Conflict-free access since threads 3.Appendix G. 4. Compute Capabilities Threads: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Banks: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Threads: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Banks: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Threads: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Banks: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Left: Conflict-free access via random permutation. 6.

x CUDA C Programming Guide Version 3.Appendix G. Compute Capabilities Figure G-3 Examples of Irregular and Colliding Shared Memory Accesses for Devices of Compute Capability 2.2 169 .

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