International journal of VLSI design & Communication Systems (VLSICS) Vol.1, No.

3, September 2010

STATISTICAL MODELLING OF ft TO PROCESS PARAMETERS IN 30 NM GATE LENGTH FINFETS
B. Lakshmi and R. Srinivasan
Department of Information Technology SSN College of Engineering, Kalavakkam – 603 110, Chennai, India
laxmi.balu@yahoo.com srinivasanr@ssn.edu.in

ABSTRACT
This paper investigates the effect of process variations on unity gain frequency (ft) in 30 nm gate length FinFET by performing extensive TCAD simulations. Six different geometrical parameters, channel doping, source/drain doping and gate electrode work function are studied for their sensitivity on ft. It is found that ft is more sensitive to gate length, underlap, gate-oxide thickness, channel and Source/Drain doping and less sensitive to source/drain width and length, and work function variations. Statistical modelling has been performed for ft through design of experiment with respect to sensitive parameters. The model has been validated through a comparison between random set of experimental data simulations and predicted values obtained from the model.

KEYWORDS
ft , FinFET, process variations, Statistical modelling, Design of Experiments

1. INTRODUCTION
The progress in CMOS technology has made it well suited for RF and microwave operations at high level of integration [1], and the continuous improvement of the device performance has made it a contender for low-power and, eventually, low-cost radio front end. In the area of multigate transistors, double-gate FinFETs are considered a serious contender for channel scaling [2], [3] because of their quasi-planar structure and the compatibility with CMOS. Several authors have already studied the low field mobility in fins of various widths [4]-[6]. RF performance of FinFETs is reported in [7], [8]. Unity gain frequency (ft) is one of the important metric in RF applications. ft is defined as the frequency at which the current gain of the device becomes unity. ft is calculated by

ft=

gm 2πC gg

(1)

where Cgg is the combination of Cgs, Cgd, overlap capacitance and any other fringing capacitance. In this article, nine different geometrical parameters related to FinFET are varied to capture their sensitivity on ft. This paper analyzes double-gate FinFETs as a downscaling option for CMOS technology from an RF perspective. The effect of various structural and doping parameters (9 parameters in total) on ft is studied and the five most sensitive parameters are identified. Using these sensitive parameters a 5 point DOE (design of experiments) is designed and the simulations are done. i.e. this work is based on design and simulation of the nominal device, design of experiment and running of the experiment, extraction of results, fitting the response surfaces (models) and testing of the models. We have modelled ft in terms of the most sensitive parameters like gate
DOI : 10.5121/vlsic.2010.1304 36

2. channel and source/drain doping. fin width (W).gate length (Lg). and Tox and these are shown in Fig. x2 is the underlap. six are geometrical parameters . Next section deals with the simulation methodology followed in this paper. SIMULATION METHODOOGY Sentaurus TCAD simulator from Synopsys [10] is used to perform all the simulations. b’s are the fitting parameters determined by the data obtained from the experiment. No. doping dependency of mobility. Figure 2 shows the schematic diagram of the device. x4 is the channel doping and x5 is the Source/Drain doping. y is the unity gain frequency. and velocity saturation.1. Table 1 also gives the dimensions of the nominal device. quantization of inversion layer charge. source/drain doping (NSD) and gate electrode work function (WF). gate oxide thickness. 2. source/drain length (SL). to define doping. effect of high and normal electric fields on mobility.International journal of VLSI design & Communication Systems (VLSICS) Vol. September 2010 length. 1. At various gate biases ft is calculated and the maximum of them is taken as ft. x3 is the gate oxide thickness. • Sentaurus structure editor (SDE): To create the device structure. underlap. The structure generated from SDE is shown in Fig 1. Doping and mesh information can also be observed in Fig. underlap (Lun). Totally nine different parameters are considered in this study. This simulator has many modules and the following are used in this study. The model that describe these quantities have an approximated form [9] as. and it strongly depends on the gate bias. The various process parameters considered in this study and their range are given in Table. Standard AC simulations are done in SDEVICE and ft is extracted from these results. Other three parameters are channel doping (Nch).3. 2 2 2 y = b 0 + b1 x 1 + b 2 x 2 + b 3 x 3 + b 4 x 4 + b 5 x 5 + b11x 1 + b 22 x 2 + b 33 x 3 + b 44 x 2 + b 55 x 5 2 4 + b12 x 1 x 2 + b13 x 1 x 3 + b14 x 1 x 4 + b15 x 1 x 5 + b 23 x 2 x 3 + b 24 x 2 x 4 + b 25 x 2 x 5 + b 34 x 3 x 4 + b 35 x 3 x 5 + b 45 x 4 x 5 (2) where x1 is the gate length. Finally section IV provides conclusions. The physics section of SDEVICE includes the appropriate models for band to band tunnelling. 1. to define contacts. Figure 1. Structure of the Dual-Gate FinFET 37 . Section III discusses the simulation results and statistical modelling. Supply voltage (Vdd) used in this study is 0.8 V. Out of them. source/drain width (SW). ft is the frequency at which |Y21/Y11| equals one. and to generate mesh for device simulation • Sentaurus device simulator (SDEVICE): To perform all DC and AC simulations • Inspect and Tecplot: To view the results.

Characteristics of the device Process parameter Gate length (Lg) Underlap (Lun) Fin Width (W) Source Length (SL) Source Width (SW) Channel Doping (Nch) Source Drain Doping (NSD) Oxide Thickness (Tox) Gate Work Function (WF) Nominal value 30 nm 3 nm 4 nm 15 nm 8 nm 1x1016/cm3 1x1020/cm3 Range 20 nm to 40 nm 1 nm to 8 nm 2 nm to 7 nm 10 nm to 20 nm 4 nm to 16 nm 1x1015/cm3to 1x1019/cm3 1x1018/cm3 to 2x20/cm3 0. Schematic view of Dual-Gate FinFET Table 1.13 eV to 4.9 eV 1 nm 4.1.International journal of VLSI design & Communication Systems (VLSICS) Vol. No.5 nm to 2 nm 4.337 eV 38 . September 2010 Figure 2.3.

Cgg shows a different behaviour i. Variation of ft with respect to Lg Figure 4. Cgs starts dominating and calls for the increase in Cgg. September 2010 3. At some point. ft is decided by both gm and Cgg.t. Lg. No. While gm degrades with Lg. RESULTS AND DISCUSSION 3. The combined behaviour of gm and Cgg contributes to the variation of ft w. As per (1).The initial decrease of Cgg can be attributed to the reduction of Cgd [11].1. 3.3.r.International journal of VLSI design & Communication Systems (VLSICS) Vol. according to the range given in Table 1 and their sensitivity to ft is analysed in this section.1 Sensitivity Analysis of Process Parameters The nine different process parameters are varied one at a time.e.1 Variation in Gate Length Figure 3 shows the variation of ft against Lg. Figure 3. initially decreases with Lg and then increases (Fig 4). Variation of Cgs with respect to Lg 39 . It can be observed from Fig.1. 3 that ft initially increases and then decreases.

2. Figure 6 shows this kind of behaviour between ft and W. Csi is the silicon body capacitance.r. It can be seen from Fig 5 that ft initially increases and then decreases w.International journal of VLSI design & Communication Systems (VLSICS) Vol. depending upon the channel doping levels. the increase in W increases current and thereby gm and ft.3. Figure 5.1. 5.Variation in Fin Width When W is varied we may either face volume inversion or may not.Variation of ft with respect to Lun 3.r. When the channel doping is 1x1016/cm3 volume inversion is not seen [14].t W. September 2010 3.5x1018/cm3.3 . volume inversion effect is seen which causes ft to decrease initially and then to increase w. For the channel doping around 1. Therefore. 40 . Lun. Increasing Lun reduces the fringing capacitance.The Cgg in DGMOS can be expressed as C gg = Series (C ox . Variation in Underlap Figure 5 depicts the plot between ft and Lun. No. 7. Cov is the gate to source/drain overlap capacitance and Cfringing is the fringing capacitance and is given by L −T − un ox L +T e un ox C fringing = WK ∈di πW ln 2 2 π L un + Tox (4) When Lun increases current degrades and thereby gm monotonically decreases. The combined behavior of gm and Cgg is responsible for the ft trend seen in Fig. [13].1. and thereby decreases Cgg [12]. This is depicted in Fig. C si ) || C ov || C fringing (3) where Cox is the oxide capacitance.1.t.

t W with volume inversion 3. Variation of ft w. Figure 8.International journal of VLSI design & Communication Systems (VLSICS) Vol.4.3.1. Variation of ft with respect to SL 41 .r. Increasing source length increases the parasitic resistance associated with the channel and degrades gm which in turn decreases ft.t W without volume inversion Figure 7. September 2010 Figure 6.1.r. Variation of ft w. No. Variation in Source Length Figure 8 shows the ft versus source length plot.

42 .Variation in Source Width Figure 9 shows ft as a function of source width. The same is seen in Fig.Variation in Channel Doping Figure 11 shows the variation of ft against Nch.1.5 .3. The combined effect of gm and Cgg decides ft behaviour with respect to Tox. Both gm and Cgg together control ft. Variation of ft with respect to Tox 3. September 2010 3. Figure 9.1. Cgg always decreases when Tox increases whereas gm may go down or high depending on whether we are driven by short channel effects or not. Threshold voltage of DGFET/FinFET is insensitive up to 1x1017/cm3 [15]. ft increases initially w.r. ft decreases due to gm degradation. No. It can be noticed from Fig.6 ..Variation in Oxide Thickness Figure 10 shows the variation of ft with Tox. 11.t Tox.1. From which it can be reasoned out that ft is also insensitive at lower channel doping levels.International journal of VLSI design & Communication Systems (VLSICS) Vol. Figure 10. 9 that ft is almost independent of SW. Variation of ft with respect to SW 3.1.7 . At higher doping levels.

t work function. Figure 13 shows ft versus gate work function plot and it can be noticed that ft exhibits a flat behaviour w. 3.12 Figure 12.Variation in Work Function High frequency characteristics are less sensitive to work function variation [16].8 . No. Variation of ft with respect to NSD 3. and thereby ft increases. Therefore. Variation of ft with respect to Nch.International journal of VLSI design & Communication Systems (VLSICS) Vol.Variation in Source/drain Doping Figure 12 shows the variation of ft with source/drain doping. 43 .3.r. This is reflected in Fig. ft is expected to be indifferent to gate electrode work function.1.1.1. When NSD increases Ion and gm increase due to the lowered parasitic series resistance values.9 . September 2010 Figure 11.

Nch and NSD.2 nm 1X1016 /cm3 to 1X1019 /cm3 5X1018/cm3 to 2X1020 /cm3 Points in the range 20. Table 2 . No. 1X1018 and 1X1019 (/cm3) 5X1018. September 2010 Figure 13.The regression coefficients for the second order polynomial of the process parameters are shown in Table 3. 5. 25.5.1X1020 and 2X1020 (/cm3) \ 44 . 35 and 40 (nm) 1. These sensitive parameters are made to undergo a variability study with the help of design of experiments. The range of these sensitive parameters for the variability study is given in Table 2 which results in 2500 simulations. Variation of ft with respect to WF 3. Tox. 1. Lun.5 nm to 2. 1X1017.1.3.5X1019.Range of Sensitive Parameters Process parameters Gate length (Lg) Underlap (Lun) Oxide Thickness (Tox) Channel Doping (Nch) Source Drain Doping (NSD) Range 20 nm to 40 nm 1nm to 9 nm 0.2 and 2. 1.2 (nm) 1X1016. 9. The model that has been obtained by the regression technique is generated with the help of SPSS [17].1. 5X1019. 30.2 Statistical modelling: The sensitive parameters are chosen as Lg.7 and 9 (nm) 0.International journal of VLSI design & Communication Systems (VLSICS) Vol.2.3.

International journal of VLSI design & Communication Systems (VLSICS) Vol.3. To have a correlation plot TCAD values are plotted against model values and the same is depicted in Fig.052 .639E27 1266894.540 -100967.164E27 -4.884 -124191. we have generated 35 (=243) uniformly distributed pseudo-random numbers for each of these sensitive parameters and ft values are predicted from the generated model.007E19 -.568 -4.765E12 -1. The correlation coefficient is found out as r=0. September 2010 Table 3. 14.992.698E-16 -1.1.210E27 -3.874E27 1.009 1. No. TCAD simulations are carried out and the ft values are extracted. Process parameters along with their corresponding regression coefficients Factor Constant Lg Lun Tox Nch NSD Lg2 Lun2 Tox2 Nch2 NSD2 LgLun LgTox LgNch LgNSD LunTox LunNch LunNSD ToxNch ToxNSD NchNSD Coefficient bo b1 b2 b3 b4 b5 b11 b22 b33 b44 b55 b12 b13 b14 b15 b23 b24 b25 b34 b35 b45 Factor values 2.069 -1672454.539 7.265 23534.103E20 -3.964E19 4.489E-17 1.564E28 9. 45 .137E27 -3105744.254E-17 In order to study the statistical nature of the device output with respect to sensitive parameters. For the same set of random numbers generated.

46 [4] . 50. SW. pp. Lun. Dennard. 259-288. "Device scaling limits of Si MOSFETs and their application dependencies. Gamiz. Taur. J. M. P. vol. 6854-6863. 683–699.” IEEE Trans. 2003. Phys. pp.net/Links/2005ITRS/PIDS2005. ACKNOWLEDGEMENT This work is supported by Department of Science & Technology. no. Cartujo-Cassinello. It was found that Lg. S. source/drain length and width are less sensitive parameters. Wong. Frank. Lun. Correlation coefficient r is depicted here 4. Mar. 3. and J. Nowak. Lopez-Villanueva. 12. P." J. E. 2001." Proc. and WF) have been varied over a range and their effect on ft have been studied through TCAD simulations. Solomon. September 2010 Fig. J. Larson. Nch and NSD are more sensitive parameters whereas gate electrode work function. International Technology Roadmap for Semiconductor (ITRS). H.1.3. statistical modelling has been performed. Government of India under SERC scheme REFERENCES [1] L. Tox. F. 3. 1999. Electron Devices.pdf [2] [3] D. and Tox). 86. Dec. Mar. [Online]. P. Carceller. vol. R. 89..International journal of VLSI design & Communication Systems (VLSICS) Vol. “Silicon technology tradeoffs for radio-frequency/mixed signal systems-on-a-chip. vol.992 was got while running the simulations with random set of values for sensitive parameters. and three non-geometrical parameters (Nch. E. Available: www. No. Correlation coefficient around 0. Y. CONCLUSION Six geometrical parameters (Lg. W. By running DOE using the sensitive parameters in TCAD.itrs. no. no. NSD. Appl. and H. J. SL. Roldan. "Surface roughness at the Si?SiO2 interfaces in fully depleted silicon-on-insulator inversion layers. 14: Correlation plot between TCAD simulated data and model predicted data for ft. pp. IEEE.

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